@code{AMD_STIBP} -- Single thread indirect branch predictors (STIBP) for AMD cpus.
@item
+@code{AMD_VIRT_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus (older systems).
+
+@item
@code{AMX_BF16} -- Tile computational operations on bfloat16 numbers.
@item
x86_cpu_AMD_IBRS = x86_cpu_index_80000008_ebx + 14,
x86_cpu_AMD_STIBP = x86_cpu_index_80000008_ebx + 15,
x86_cpu_AMD_SSBD = x86_cpu_index_80000008_ebx + 24,
+ x86_cpu_AMD_VIRT_SSBD = x86_cpu_index_80000008_ebx + 25,
x86_cpu_index_7_ecx_1_eax
= (CPUID_INDEX_7_ECX_1 * 8 * 4 * sizeof (unsigned int)
#define bit_cpu_AMD_IBRS (1u << 14)
#define bit_cpu_AMD_STIBP (1u << 15)
#define bit_cpu_AMD_SSBD (1u << 24)
+#define bit_cpu_AMD_VIRT_SSBD (1u << 25)
/* CPUID_INDEX_7_ECX_1. */
#define index_cpu_AMD_IBRS CPUID_INDEX_80000008
#define index_cpu_AMD_STIBP CPUID_INDEX_80000008
#define index_cpu_AMD_SSBD CPUID_INDEX_80000008
+#define index_cpu_AMD_VIRT_SSBD CPUID_INDEX_80000008
/* CPUID_INDEX_7_ECX_1. */
#define reg_AMD_IBRS ebx
#define reg_AMD_STIBP ebx
#define reg_AMD_SSBD ebx
+#define reg_AMD_VIRT_SSBD ebx
/* CPUID_INDEX_7_ECX_1. */
if (cpu_features->basic.kind == arch_kind_intel)
fails += CHECK_PROC (ssbd, SSBD);
else if (cpu_features->basic.kind == arch_kind_amd)
- fails += CHECK_PROC (ssbd, AMD_SSBD);
+ {
+ /* This feature is implemented in 2 different ways on AMD processors:
+ newer systems provides AMD_SSBD (function 8000_0008, EBX[24]),
+ while older system proviseds AMD_VIRT_SSBD (function 8000_008,
+ EBX[25]). However for AMD_VIRT_SSBD, kernel shows both 'ssbd'
+ and 'virt_ssbd' on /proc/cpuinfo; while for AMD_SSBD only 'ssbd'
+ is provided. */
+ if (HAS_CPU_FEATURE (AMD_SSBD))
+ fails += CHECK_PROC (ssbd, AMD_SSBD);
+ else if (HAS_CPU_FEATURE (AMD_VIRT_SSBD))
+ fails += CHECK_PROC (virt_ssbd, AMD_VIRT_SSBD);
+ }
fails += CHECK_PROC (sse, SSE);
fails += CHECK_PROC (sse2, SSE2);
fails += CHECK_PROC (pni, SSE3);