ARM: dts: meson8b: add support for booting the secondary CPU cores

Booting the secondary CPU cores involves the following nodes/devices:
- SCU (Snoop-Control-Unit, for which we already have a DT node)
- a reset line for each CPU core, provided by the reset-controller
  which is built into the clock-controller
- the PMU (power management unit) which controls the power of the CPU
  cores
- a range in the SRAM specifically reserved for booting secondary CPU
  cores
- the "enable-method" which activates booting the secondary CPU cores

This adds all required nodes and properties to boot the secondary CPU
cores.

Signed-off-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Linus Lüssing <linus.luessing@c0d3.blue>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 283c68c..1e06e2c 100644 (file)
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -47,6 +47,7 @@
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8b-gpio.h>
 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 #include "meson.dtsi"
 
 / {
@@ -59,6 +60,8 @@
                        compatible = "arm,cortex-a5";
                        next-level-cache = <&L2>;
                        reg = <0x200>;
+                       enable-method = "amlogic,meson8b-smp";
+                       resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
                };
 
                cpu@201 {
@@ -66,6 +69,8 @@
                        compatible = "arm,cortex-a5";
                        next-level-cache = <&L2>;
                        reg = <0x201>;
+                       enable-method = "amlogic,meson8b-smp";
+                       resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
                };
 
                cpu@202 {
@@ -73,6 +78,8 @@
                        compatible = "arm,cortex-a5";
                        next-level-cache = <&L2>;
                        reg = <0x202>;
+                       enable-method = "amlogic,meson8b-smp";
+                       resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
                };
 
                cpu@203 {
@@ -80,6 +87,8 @@
                        compatible = "arm,cortex-a5";
                        next-level-cache = <&L2>;
                        reg = <0x203>;
+                       enable-method = "amlogic,meson8b-smp";
+                       resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
                };
        };
 
@@ -102,6 +111,11 @@
 }; /* end of / */
 
 &aobus {
+       pmu: pmu@e0 {
+               compatible = "amlogic,meson8b-pmu", "syscon";
+               reg = <0xe0 0x18>;
+       };
+
        pinctrl_aobus: pinctrl@84 {
                compatible = "amlogic,meson8b-aobus-pinctrl";
                reg = <0x84 0xc>;
@@ -174,6 +188,13 @@
        };
 };
 
+&ahb_sram {
+       smp-sram@1ff80 {
+               compatible = "amlogic,meson8b-smp-sram";
+               reg = <0x1ff80 0x8>;
+       };
+};
+
 &ethmac {
        clocks = <&clkc CLKID_ETH>;
        clock-names = "stmmaceth";