ac/nir: Store only lowest 8 bits for task draw ring DWORD3.

When writing the draw ready bit, don't write the high 24 bits
of DWORD3, because that is used by the HW for something else
according to LLPC.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22211>

diff --git a/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c b/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c
index 0384623..e88088f 100644 (file)
--- a/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c
+++ b/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c
@@ -108,7 +108,7 @@ task_draw_ready_bit(nir_builder *b,
    nir_ssa_def *workgroup_index = task_workgroup_index(b, s);
 
    nir_ssa_def *idx = nir_iadd_nuw(b, ring_entry, workgroup_index);
-   return nir_ubfe(b, idx, nir_imm_int(b, util_bitcount(s->num_entries - 1)), nir_imm_int(b, 1));
+   return nir_u2u8(b, nir_ubfe(b, idx, nir_imm_int(b, util_bitcount(s->num_entries - 1)), nir_imm_int(b, 1)));
 }
 
 static nir_ssa_def *
@@ -185,9 +185,13 @@ lower_task_launch_mesh_workgroups(nir_builder *b,
       nir_ssa_def *x = nir_channel(b, dimensions, 0);
       nir_ssa_def *y = nir_channel(b, dimensions, 1);
       nir_ssa_def *z = nir_channel(b, dimensions, 2);
-      nir_ssa_def *rdy = task_draw_ready_bit(b, s);
-      nir_ssa_def *store_val = nir_vec4(b, x, y, z, rdy);
-      task_write_draw_ring(b, store_val, 0, s);
+
+      /* Dispatch dimensions of mesh shader workgroups. */
+      task_write_draw_ring(b, nir_vec3(b, x, y, z), 0, s);
+      /* Prevent the two stores from being reordered. */
+      nir_scoped_memory_barrier(b, NIR_SCOPE_INVOCATION, NIR_MEMORY_RELEASE, nir_var_shader_out);
+      /* Ready bit, only write the low 8 bits. */
+      task_write_draw_ring(b, task_draw_ready_bit(b, s), 12, s);
    }
    nir_pop_if(b, if_invocation_index_zero);