MIPS: mm: c-r4k: Flush scache to avoid cache aliases

There is a chance for the secondary cache to have memory
aliases. This can happen if the bootloader is in a non-EVA mode
(or even in EVA mode but with different mapping from the kernel)
and the kernel switching to EVA afterwards. It's best to flush
the icache to avoid having the secondary CPUs fetching stale
data from it.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 9b223e0..8fc713f 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -640,6 +640,17 @@ static inline void local_r4k_flush_icache_range(unsigned long start, unsigned lo
                        break;
                }
        }
+#ifdef CONFIG_EVA
+       /*
+        * Due to all possible segment mappings, there might cache aliases
+        * caused by the bootloader being in non-EVA mode, and the CPU switching
+        * to EVA during early kernel init. It's best to flush the scache
+        * to avoid having secondary cores fetching stale data and lead to
+        * kernel crashes.
+        */
+       bc_wback_inv(start, (end - start));
+       __sync();
+#endif
 }
 
 static inline void local_r4k_flush_icache_range_ipi(void *args)