ARM: dts: exynos: Add DT nodes for PRNG in Exynos5 SoCs
authorŁukasz Stelmach <l.stelmach@samsung.com>
Mon, 11 Dec 2017 08:54:15 +0000 (09:54 +0100)
committerKrzysztof Kozlowski <krzk@kernel.org>
Mon, 11 Dec 2017 18:43:12 +0000 (19:43 +0100)
Add nodes for Pseudo Random Number Generator in dts files describing
Exynos5 chips.

Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
arch/arm/boot/dts/exynos5.dtsi
arch/arm/boot/dts/exynos5250.dtsi
arch/arm/boot/dts/exynos5410.dtsi
arch/arm/boot/dts/exynos5420.dtsi

index 3472245..6cc5c37 100644 (file)
                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               prng: rng@10830400 {
+                     compatible = "samsung,exynos5250-prng";
+                     reg = <0x10830400 0x200>;
+               };
+
                g2d: g2d@10850000 {
                        compatible = "samsung,exynos5250-g2d";
                        reg = <0x10850000 0x1000>;
index 232d880..e557487 100644 (file)
        pinctrl-0 = <&i2c3_bus>;
 };
 
+&prng {
+       clocks = <&clock CLK_SSS>;
+       clock-names = "secss";
+};
+
 &pwm {
        clocks = <&clock CLK_PWM>;
        clock-names = "timers";
index 7b34970..f554100 100644 (file)
        clock-names = "fin_pll", "mct";
 };
 
+&prng {
+       clocks = <&clock CLK_SSS>;
+       clock-names = "secss";
+};
+
 &pwm {
        clocks = <&clock CLK_PWM>;
        clock-names = "timers";
index a44aec3..3611f5c 100644 (file)
        clock-names = "fin_pll", "mct";
 };
 
+&prng {
+       clocks = <&clock CLK_SSS>;
+       clock-names = "secss";
+};
+
 &pwm {
        clocks = <&clock CLK_PWM>;
        clock-names = "timers";