start_time_lock_stage = drxbsp_hst_clock();
/* Start polling loop, checking for lock & timeout */
- while (done_waiting == false) {
+ while (!done_waiting) {
if (drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_state) !=
DRX_STS_OK) {
common_attr->scan_ready = true;
}
} while ((next_frequency < tuner_min_frequency) &&
- (common_attr->scan_ready == false));
+ (!common_attr->scan_ready));
/* Store new values */
common_attr->scan_freq_plan_index = table_index;
/* done with this channel, move to next one */
*get_next_channel = true;
- if (is_locked == false) {
+ if (!is_locked) {
/* no channel found */
return DRX_STS_BUSY;
}
num_tries = common_attr->scan_param->num_tries;
scan_ready = &(common_attr->scan_ready);
- for (i = 0; ((i < num_tries) && ((*scan_ready) == false)); i++) {
+ for (i = 0; ((i < num_tries) && (!(*scan_ready))); i++) {
struct drx_channel scan_channel = { 0 };
int status = DRX_STS_ERROR;
struct drx_frequency_plan *freq_plan = (struct drx_frequency_plan *) (NULL);
&next_channel);
/* Proceed to next channel if requested */
- if (next_channel == true) {
+ if (next_channel) {
int next_status = DRX_STS_ERROR;
s32 skip = 0;
}
} /* for ( i = 0; i < ( ... num_tries); i++) */
- if ((*scan_ready) == true) {
+ if ((*scan_ready)) {
/* End of scan reached: call stop-scan, ignore any error */
ctrl_scan_stop(demod);
common_attr->scan_active = false;
DRX_STS_OK) {
return DRX_STS_ERROR;
} /* if */
- };
+ }
break;
/*================================================================*/
bytes_left_to_compare -=
((u32) bytes_to_compare);
} /* while( bytes_to_compare > DRX_UCODE_MAX_BUF_SIZE ) */
- };
+ }
break;
/*================================================================*/
(demod->my_common_attr == NULL) ||
(demod->my_ext_attr == NULL) ||
(demod->my_i2c_dev_addr == NULL) ||
- (demod->my_common_attr->is_opened == true)) {
+ (demod->my_common_attr->is_opened)) {
return DRX_STS_INVALID_ARG;
}
(demod->my_common_attr == NULL) ||
(demod->my_ext_attr == NULL) ||
(demod->my_i2c_dev_addr == NULL) ||
- (demod->my_common_attr->is_opened == false)) {
+ (!demod->my_common_attr->is_opened)) {
return DRX_STS_INVALID_ARG;
}
return DRX_STS_INVALID_ARG;
}
- if (((demod->my_common_attr->is_opened == false) &&
+ if (((!demod->my_common_attr->is_opened) &&
(ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_VERSION))
) {
return DRX_STS_INVALID_ARG;
if (stat != DRX_STS_OK) {
break;
- };
+ }
current_timer = drxbsp_hst_clock();
delta_timer = current_timer - start_timer;
if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
stat = DRX_STS_ERROR;
break;
- };
+ }
} while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
&tr_status, 0x0000);
if (stat != DRX_STS_OK) {
break;
- };
+ }
current_timer = drxbsp_hst_clock();
delta_timer = current_timer - start_timer;
if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
stat = DRX_STS_ERROR;
break;
- };
+ }
} /* while ( ... ) */
}
data, &tr_status);
if (stat != DRX_STS_OK) {
break;
- };
+ }
current_timer = drxbsp_hst_clock();
delta_timer = current_timer - start_timer;
if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
stat = DRX_STS_ERROR;
break;
- };
+ }
} while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
hi_cmd.param2 =
(u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START);
hi_cmd.param3 = (u16) ((datasize / 2) - 1);
- if (read_flag == false) {
+ if (!read_flag) {
hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE;
} else {
hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ;
DRXDAP_FASI_ADDR2BANK(addr));
hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);
- if (read_flag == false) {
+ if (!read_flag) {
/* write data to buffer */
for (i = 0; i < (datasize / 2); i++) {
goto rw_error;
}
- if (read_flag == true) {
+ if (read_flag) {
/* read data from buffer */
for (i = 0; i < (datasize / 2); i++) {
drxj_dap_read_reg16(dev_addr,
(((cmd->
param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M)
== SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
- if (powerdown_cmd == false) {
+ if (!powerdown_cmd) {
/* Wait until command rdy */
do {
nr_retries++;
if (nr_retries > DRXJ_MAX_RETRIES) {
goto rw_error;
- };
+ }
rc = DRXJ_DAP.read_reg16func(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);
if (rc != DRX_STS_OK) {
FEC_OC_SNC_MODE_CORR_DISABLE__M));
fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M);
- if (ext_attr->disable_te_ihandling == true) {
+ if (ext_attr->disable_te_ihandling) {
/* do not change TEI bit */
fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M;
fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M |
/* reset to default (normal bit order) */
fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M);
- if (ext_attr->bit_reverse_mpeg_outout == true) {
+ if (ext_attr->bit_reverse_mpeg_outout) {
/* reverse bit order */
fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M;
}
/*====================================================================*/
case DRX_UIO1:
/* DRX_UIO1: SMA_TX UIO-1 */
- if (ext_attr->has_smatx != true)
+ if (!ext_attr->has_smatx)
return DRX_STS_ERROR;
switch (uio_cfg->mode) {
case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */
/*====================================================================*/
case DRX_UIO2:
/* DRX_UIO2: SMA_RX UIO-2 */
- if (ext_attr->has_smarx != true)
+ if (!ext_attr->has_smarx)
return DRX_STS_ERROR;
switch (uio_cfg->mode) {
case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
/*====================================================================*/
case DRX_UIO3:
/* DRX_UIO3: GPIO UIO-3 */
- if (ext_attr->has_gpio != true)
+ if (!ext_attr->has_gpio)
return DRX_STS_ERROR;
switch (uio_cfg->mode) {
case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
/*====================================================================*/
case DRX_UIO4:
/* DRX_UIO4: IRQN UIO-4 */
- if (ext_attr->has_irqn != true)
+ if (!ext_attr->has_irqn)
return DRX_STS_ERROR;
switch (uio_cfg->mode) {
case DRX_UIO_MODE_READWRITE:
return DRX_STS_INVALID_ARG;
}
- if (*uio_available[uio_cfg->uio] == false) {
+ if (!*uio_available[uio_cfg->uio]) {
return DRX_STS_ERROR;
}
/*====================================================================*/
case DRX_UIO1:
/* DRX_UIO1: SMA_TX UIO-1 */
- if (ext_attr->has_smatx != true)
+ if (!ext_attr->has_smatx)
return DRX_STS_ERROR;
if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE)
&& (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) {
/*======================================================================*/
case DRX_UIO2:
/* DRX_UIO2: SMA_RX UIO-2 */
- if (ext_attr->has_smarx != true)
+ if (!ext_attr->has_smarx)
return DRX_STS_ERROR;
if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) {
return DRX_STS_ERROR;
/*====================================================================*/
case DRX_UIO3:
/* DRX_UIO3: ASEL UIO-3 */
- if (ext_attr->has_gpio != true)
+ if (!ext_attr->has_gpio)
return DRX_STS_ERROR;
if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) {
return DRX_STS_ERROR;
/*=====================================================================*/
case DRX_UIO4:
/* DRX_UIO4: IRQN UIO-4 */
- if (ext_attr->has_irqn != true)
+ if (!ext_attr->has_irqn)
return DRX_STS_ERROR;
if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) {
/*====================================================================*/
case DRX_UIO1:
/* DRX_UIO1: SMA_TX UIO-1 */
- if (ext_attr->has_smatx != true)
+ if (!ext_attr->has_smatx)
return DRX_STS_ERROR;
if (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) {
/*======================================================================*/
case DRX_UIO2:
/* DRX_UIO2: SMA_RX UIO-2 */
- if (ext_attr->has_smarx != true)
+ if (!ext_attr->has_smarx)
return DRX_STS_ERROR;
if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) {
/*=====================================================================*/
case DRX_UIO3:
/* DRX_UIO3: GPIO UIO-3 */
- if (ext_attr->has_gpio != true)
+ if (!ext_attr->has_gpio)
return DRX_STS_ERROR;
if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) {
/*=====================================================================*/
case DRX_UIO4:
/* DRX_UIO4: IRQN UIO-4 */
- if (ext_attr->has_irqn != true)
+ if (!ext_attr->has_irqn)
return DRX_STS_ERROR;
if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) {
hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL;
hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
- if (*bridge_closed == true) {
+ if (*bridge_closed) {
hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED;
} else {
hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN;
goto rw_error;
}
- if (read_flag == true) {
+ if (read_flag) {
int i = 0;
/* read data from buffer */
for (i = 0; i < (datasize / 2); i++) {
goto rw_error;
}
- if (*enable == true) {
+ if (*enable) {
bool bridge_enabled = false;
/* MPEG pins to input */
}
intermediate_freq = demod->my_common_attr->intermediate_freq;
sampling_frequency = demod->my_common_attr->sys_clock_freq / 3;
- if (tuner_mirror == true) {
+ if (tuner_mirror) {
/* tuner doesn't mirror */
if_freq_actual =
intermediate_freq + rf_freq_residual + fm_frequency_shift;
pr_err("error %d\n", rc);
goto rw_error;
}
- if (ext_attr->reset_pkt_err_acc == true) {
+ if (ext_attr->reset_pkt_err_acc) {
last_pkt_err = data;
pkt_err = 0;
ext_attr->reset_pkt_err_acc = false;
goto rw_error;
}
- if (ext_attr->pos_image == true) {
+ if (ext_attr->pos_image) {
/* negative image */
carrier_frequency_shift = nominal_frequency - current_frequency;
} else {
pr_err("error %d\n", rc);
goto rw_error;
}
- if (primary == true) {
+ if (primary) {
rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
if (rc != DRX_STS_OK) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* B-Input to ADC, PGA+filter in standby */
- if (ext_attr->has_lna == false) {
+ if (!ext_attr->has_lna) {
rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
if (rc != DRX_STS_OK) {
pr_err("error %d\n", rc);
goto rw_error;
}
- };
+ }
/* turn on IQMAF. It has to be in front of setAgc**() */
rc = set_iqm_af(demod, true);
goto rw_error;
}
- if (primary == true) {
+ if (primary) {
rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
if (rc != DRX_STS_OK) {
pr_err("error %d\n", rc);
}
if (op & QAM_SET_OP_ALL) {
- if (ext_attr->has_lna == false) {
+ if (!ext_attr->has_lna) {
rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
if (rc != DRX_STS_OK) {
pr_err("error %d\n", rc);
pr_err("error %d\n", rc);
goto rw_error;
}
- if (primary == true) {
+ if (primary) {
rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
if (rc != DRX_STS_OK) {
pr_err("error %d\n", rc);
}
/* Common initializations FM & NTSC & B/G & D/K & I & L & LP */
- if (ext_attr->has_lna == false) {
+ if (!ext_attr->has_lna) {
rc = DRXJ_DAP.write_reg16func(dev_addr, IQM_AF_AMUX__A, 0x01, 0);
if (rc != DRX_STS_OK) {
pr_err("error %d\n", rc);
goto rw_error;
}
- if (set_standard == true) {
+ if (set_standard) {
rc = aud_ctrl_set_standard(demod, &aud_standard);
if (rc != DRX_STS_OK) {
pr_err("error %d\n", rc);
/* signal is transmitted inverted */
((oob_param->spectrum_inverted == true) &
/* and tuner is not mirroring the signal */
- (mirror_freq_spectOOB == false)) |
+ (!mirror_freq_spectOOB)) |
/* or */
/* signal is transmitted noninverted */
((oob_param->spectrum_inverted == false) &
/* and tuner is mirroring the signal */
- (mirror_freq_spectOOB == true))
+ (mirror_freq_spectOOB))
)
set_param_parameters[0] =
SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC;
/* signal is transmitted inverted */
((oob_param->spectrum_inverted == true) &
/* and tuner is not mirroring the signal */
- (mirror_freq_spectOOB == false)) |
+ (!mirror_freq_spectOOB)) |
/* or */
/* signal is transmitted noninverted */
((oob_param->spectrum_inverted == false) &
/* and tuner is mirroring the signal */
- (mirror_freq_spectOOB == true))
+ (mirror_freq_spectOOB))
)
set_param_parameters[0] =
SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC;
/* signal is transmitted inverted */
((oob_param->spectrum_inverted == true) &
/* and tuner is not mirroring the signal */
- (mirror_freq_spectOOB == false)) |
+ (!mirror_freq_spectOOB)) |
/* or */
/* signal is transmitted noninverted */
((oob_param->spectrum_inverted == false) &
/* and tuner is mirroring the signal */
- (mirror_freq_spectOOB == true))
+ (mirror_freq_spectOOB))
)
set_param_parameters[0] =
SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC;
return DRX_STS_INVALID_ARG;
}
- if (ext_attr->oob_power_on == false)
+ if (!ext_attr->oob_power_on)
return DRX_STS_ERROR;
rc = DRXJ_DAP.read_reg16func(dev_addr, ORX_DDC_OFO_SET_W__A, &data, 0);
goto rw_error;
}
tuner_freq_offset = channel->frequency - ext_attr->frequency;
- if (tuner_mirror == true) {
+ if (tuner_mirror) {
/* positive image */
channel->frequency += tuner_freq_offset;
} else {
DRX_STS_OK) {
return DRX_STS_ERROR;
}
- };
+ }
break;
/*===================================================================*/
if (result != 0) {
return DRX_STS_ERROR;
- };
+ }
curr_addr +=
((dr_xaddr_t)
bytes_left_to_compare -=
((u32) bytes_to_compare);
} /* while( bytes_to_compare > DRXJ_UCODE_MAX_BUF_SIZE ) */
- };
+ }
break;
/*===================================================================*/
mc_data += mc_block_nr_bytes;
} /* for( i = 0 ; i<mc_nr_of_blks ; i++ ) */
- if (upload_audio_mc == false) {
+ if (!upload_audio_mc) {
ext_attr->flag_aud_mc_uploaded = false;
}
goto rw_error;
}
}
- };
+ }
rc = DRXJ_DAP.write_reg16func(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
if (rc != DRX_STS_OK) {