+2009-06-23 DJ Delorie <dj@redhat.com>
+
+ * MAINTAINERS: Add myself as mep maintainer.
+
2009-06-23 Ian Lance Taylor <iant@google.com>
* configure.ac: Add --enable-build-with-cxx. When set, add c++ to
m68k port Andreas Schwab schwab@linux-m68k.org
m68k-motorola-sysv port Philippe De Muyter phdm@macqel.be
mcore port Nick Clifton nickc@redhat.com
+mep port DJ Delorie dj@redhat.com
mips port Eric Christopher echristo@apple.com
mips port Richard Sandiford rdsandiford@googlemail.com
mmix port Hans-Peter Nilsson hp@bitrange.com
+2009-06-23 DJ Delorie <dj@redhat.com>
+
+ Add MeP port.
+ * config.gcc: Add mep support.
+ * recog.c: Resurrect validate_replace_rtx_subexp().
+ * recog.h: Likewise.
+ * config/mep/: Add new port:
+ * config/mep/constraints.md: New file.
+ * config/mep/default.h: New file.
+ * config/mep/intrinsics.h: New file.
+ * config/mep/intrinsics.md: New file.
+ * config/mep/ivc2-template.h: New file.
+ * config/mep/mep-c5.cpu: New file.
+ * config/mep/mep-core.cpu: New file.
+ * config/mep/mep-default.cpu: New file.
+ * config/mep/mep-ext-cop.cpu: New file.
+ * config/mep/mep-intrin.h: New file.
+ * config/mep/mep-ivc2.cpu: New file.
+ * config/mep/mep-lib1.asm: New file.
+ * config/mep/mep-lib2.c: New file.
+ * config/mep/mep-pragma.c: New file.
+ * config/mep/mep-protos.h: New file.
+ * config/mep/mep-tramp.c: New file.
+ * config/mep/mep.c: New file.
+ * config/mep/mep.cpu: New file.
+ * config/mep/mep.h: New file.
+ * config/mep/mep.md: New file.
+ * config/mep/mep.opt: New file.
+ * config/mep/predicates.md: New file.
+ * config/mep/t-mep: New file.
+
2009-06-23 Ian Lance Taylor <iant@google.com>
* configure.ac: Invoke AC_PROG_CXX. Separate C specific warnings
inhibit_libc=true
use_gcc_stdint=wrap
;;
+mep-*-*)
+ tm_file="dbxelf.h elfos.h svr4.h ${tm_file}"
+ tmake_file=mep/t-mep
+ extra_parts="crtbegin.o crtend.o"
+ c_target_objs="mep-pragma.o"
+ cxx_target_objs="mep-pragma.o"
+ if test -d "${srcdir}/../newlib/libc/include" &&
+ test "x$with_headers" = x; then
+ with_headers=yes
+ fi
+ use_gcc_stdint=wrap
+ ;;
mips-sgi-irix[56]*)
tm_file="elfos.h ${tm_file} mips/iris.h"
tmake_file="mips/t-iris mips/t-slibgcc-irix"
--- /dev/null
+;; Toshiba Media Processor Machine constraints
+;; Copyright (C) 2009 Free Software Foundation, Inc.
+;; Contributed by Red Hat Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>. */
+
+
+
+(define_register_constraint "a" "SP_REGS"
+ "The $sp register.")
+
+(define_register_constraint "b" "TP_REGS"
+ "The $tp register.")
+
+(define_register_constraint "c" "CONTROL_REGS"
+ "Any control register.")
+
+(define_register_constraint "d" "HILO_REGS"
+ "Either the $hi or the $lo register.")
+
+(define_register_constraint "em" "LOADABLE_CR_REGS"
+ "Coprocessor registers that can be directly loaded ($c0-$c15).")
+
+(define_register_constraint "ex" "mep_have_copro_copro_moves_p ? CR_REGS : NO_REGS"
+ "Coprocessor registers that can be moved to each other.")
+
+(define_register_constraint "er" "mep_have_core_copro_moves_p ? CR_REGS : NO_REGS"
+ "Coprocessor registers that can be moved to core registers.")
+
+(define_register_constraint "h" "HI_REGS"
+ "The $hi register.")
+
+(define_register_constraint "j" "RPC_REGS"
+ "The $rpc register.")
+
+(define_register_constraint "l" "LO_REGS"
+ "The $lo register.")
+
+(define_register_constraint "t" "TPREL_REGS"
+ "Registers which can be used in $tp-relative addressing.")
+
+(define_register_constraint "v" "GP_REGS"
+ "The $gp register.")
+
+(define_register_constraint "x" "CR_REGS"
+ "The coprocessor registers.")
+
+(define_register_constraint "y" "CCR_REGS"
+ "The coprocessor control registers.")
+
+(define_register_constraint "z" "R0_REGS"
+ "The $0 register.")
+
+(define_register_constraint "A" "USER0_REGS"
+ "User-defined register set A.")
+
+(define_register_constraint "B" "USER1_REGS"
+ "User-defined register set B.")
+
+(define_register_constraint "C" "USER2_REGS"
+ "User-defined register set C.")
+
+(define_register_constraint "D" "USER3_REGS"
+ "User-defined register set D.")
+
+
+
+(define_constraint "I"
+ "Offsets for $gp-rel addressing."
+ (and (match_code "const_int")
+ (match_test "ival >= -32768 && ival < 32768")))
+
+(define_constraint "J"
+ "Constants that can be used directly with boolean insns."
+ (and (match_code "const_int")
+ (match_test "ival >= 0 && ival < 65536")))
+
+(define_constraint "K"
+ "Constants that can be moved directly to registers."
+ (and (match_code "const_int")
+ (match_test "ival >= 0 && ival < 0x01000000")))
+
+(define_constraint "L"
+ "Small constants that can be added to registers."
+ (and (match_code "const_int")
+ (match_test "ival >= -32 && ival < 32")))
+
+(define_constraint "M"
+ "Long shift counts."
+ (and (match_code "const_int")
+ (match_test "ival >= 0 && ival < 32")))
+
+(define_constraint "N"
+ "Small constants that can be compared to registers."
+ (and (match_code "const_int")
+ (match_test "ival >= 0 && ival < 16")))
+
+(define_constraint "O"
+ "Constants that can be loaded into the top half of registers."
+ (and (match_code "const_int")
+ (match_test "!(ival & 0xffff) && ival >= -2147483647-1 && ival <= 2147483647")))
+
+(define_constraint "S"
+ "Signed 8-bit immediates."
+ (and (match_code "const_int")
+ (match_test "ival >= -128 && ival < 127")))
+
+
+
+;; This must only be used with mep_call_address_operand() as the predicate.
+(define_constraint "R"
+ "@internal
+Near symbols that can be used as addresses for CALL."
+ (not (match_code "reg")))
+
+(define_constraint "T"
+ "Symbols encoded for $tp-rel or $gp-rel addressing."
+ (ior (ior
+ (and (match_code "unspec")
+ (match_code "symbol_ref" "a"))
+ (and (match_code "const")
+ (and (match_code "unspec" "0")
+ (match_code "symbol_ref" "0a"))))
+ (and (match_code "const")
+ (and (match_code "plus" "0")
+ (and (match_code "unspec" "00")
+ (match_code "symbol_ref" "00a"))))))
+
+(define_constraint "U"
+ "Non-constant addresses for loading/saving coprocessor registers."
+ (and (match_code "mem")
+ (match_test "! CONSTANT_P (XEXP (op, 0))")))
+
+(define_constraint "W"
+ "The top half of a symbol's value."
+ (and (match_code "high")
+ (match_code "symbol_ref" "0")))
+
+(define_constraint "Y"
+ "A register indirect address without offset."
+ (and (match_code "mem")
+ (match_code "reg" "0")))
+
+(define_constraint "Z"
+ "Symbolic references to the control bus."
+ (and (and (match_code "mem")
+ (match_code "symbol_ref" "0"))
+ (match_test "mep_section_tag (op) == 'c'")))
--- /dev/null
+/* Header created by MeP-Integrator */
+#undef __section
+#define __section(_secname) __attribute__((section(#_secname)))
+#undef mep_nop
+#define mep_nop() __asm__ volatile ("nop")
+
+#pragma GCC coprocessor available $c0...$c31
+#pragma GCC coprocessor call_saved $c6...$c7
+
+#include <intrinsics.h>
--- /dev/null
+
+
+/* DO NOT EDIT: This file is automatically generated by CGEN.
+ Any changes you make will be discarded when it is next regenerated.
+*/
+
+/* GCC defines these internally, as follows...
+#if __MEP_CONFIG_CP_DATA_BUS_WIDTH == 64
+ typedef long long cp_data_bus_int;
+#else
+ typedef long cp_data_bus_int;
+#endif
+typedef char cp_v8qi __attribute__((vector_size(8)));
+typedef unsigned char cp_v8uqi __attribute__((vector_size(8)));
+typedef short cp_v4hi __attribute__((vector_size(8)));
+typedef unsigned short cp_v4uhi __attribute__((vector_size(8)));
+typedef int cp_v2si __attribute__((vector_size(8)));
+typedef unsigned int cp_v2usi __attribute__((vector_size(8)));
+*/
+
+
+// default
+void mep_cpfmadila1_h (cp_v4hi, cp_v4hi, long, long);
+void mep_cpfmadiua1_h (cp_v4hi, cp_v4hi, long, long);
+void mep_cpfmadia1_b (cp_v8qi, cp_v8qi, long, long);
+void mep_cpfmadia1u_b (cp_v8uqi, cp_v8uqi, long, long);
+void mep_cpfmulila1_h (cp_v4hi, cp_v4hi, long, long);
+void mep_cpfmuliua1_h (cp_v4hi, cp_v4hi, long, long);
+void mep_cpfmulia1_b (cp_v8qi, cp_v8qi, long, long);
+void mep_cpfmulia1u_b (cp_v8uqi, cp_v8uqi, long, long);
+void mep_cpamadila1_h (cp_v4hi, cp_v4hi, long);
+void mep_cpamadiua1_h (cp_v4hi, cp_v4hi, long);
+void mep_cpamadia1_b (cp_v8qi, cp_v8qi, long);
+void mep_cpamadia1u_b (cp_v8uqi, cp_v8uqi, long);
+void mep_cpamulila1_h (cp_v4hi, cp_v4hi, long);
+void mep_cpamuliua1_h (cp_v4hi, cp_v4hi, long);
+void mep_cpamulia1_b (cp_v8qi, cp_v8qi, long);
+void mep_cpamulia1u_b (cp_v8uqi, cp_v8uqi, long);
+void mep_cpfmadila1s1_h (cp_v4hi, cp_v4hi, long);
+void mep_cpfmadiua1s1_h (cp_v4hi, cp_v4hi, long);
+void mep_cpfmadia1s1_b (cp_v8qi, cp_v8qi, long);
+void mep_cpfmadia1s1u_b (cp_v8uqi, cp_v8uqi, long);
+void mep_cpfmulila1s1_h (cp_v4hi, cp_v4hi, long);
+void mep_cpfmuliua1s1_h (cp_v4hi, cp_v4hi, long);
+void mep_cpfmulia1s1_b (cp_v8qi, cp_v8qi, long);
+void mep_cpfmulia1s1u_b (cp_v8uqi, cp_v8uqi, long);
+void mep_cpfmadila1s0_h (cp_v4hi, cp_v4hi, long);
+void mep_cpfmadiua1s0_h (cp_v4hi, cp_v4hi, long);
+void mep_cpfmadia1s0_b (cp_v8qi, cp_v8qi, long);
+void mep_cpfmadia1s0u_b (cp_v8uqi, cp_v8uqi, long);
+void mep_cpfmulila1s0_h (cp_v4hi, cp_v4hi, long);
+void mep_cpfmuliua1s0_h (cp_v4hi, cp_v4hi, long);
+void mep_cpfmulia1s0_b (cp_v8qi, cp_v8qi, long);
+void mep_cpfmulia1s0u_b (cp_v8uqi, cp_v8uqi, long);
+void mep_cpacswp (); // volatile
+void mep_cpaccpa1 ();
+void mep_cpacsuma1 ();
+void mep_c1nop (); // volatile
+void mep_cpfacla0s1_h (cp_v4hi, cp_v4hi);
+void mep_cpfacua0s1_h (cp_v4hi, cp_v4hi);
+void mep_cpfaca0s1_b (cp_v8qi, cp_v8qi);
+void mep_cpfaca0s1u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpfsftbla0s1_h (cp_v4hi, cp_v4hi);
+void mep_cpfsftbua0s1_h (cp_v4hi, cp_v4hi);
+void mep_cpfsftba0s1_b (cp_v8qi, cp_v8qi);
+void mep_cpfsftba0s1u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpfacla0s0_h (cp_v4hi, cp_v4hi);
+void mep_cpfacua0s0_h (cp_v4hi, cp_v4hi);
+void mep_cpfaca0s0_b (cp_v8qi, cp_v8qi);
+void mep_cpfaca0s0u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpfsftbla0s0_h (cp_v4hi, cp_v4hi);
+void mep_cpfsftbua0s0_h (cp_v4hi, cp_v4hi);
+void mep_cpfsftba0s0_b (cp_v8qi, cp_v8qi);
+void mep_cpfsftba0s0u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpsllia0 (long);
+void mep_cpsraia0 (long);
+void mep_cpsrlia0 (long);
+void mep_cpslla0 (cp_data_bus_int);
+void mep_cpsraa0 (cp_data_bus_int);
+void mep_cpsrla0 (cp_data_bus_int);
+void mep_cpaccpa0 ();
+void mep_cpacsuma0 ();
+cp_v2si mep_cpmovhla0_w ();
+cp_v2si mep_cpmovhua0_w ();
+cp_v2si mep_cppackla0_w ();
+cp_v2si mep_cppackua0_w ();
+cp_v4hi mep_cppackla0_h ();
+cp_v4hi mep_cppackua0_h ();
+cp_v8qi mep_cppacka0_b ();
+cp_v8uqi mep_cppacka0u_b ();
+cp_v2si mep_cpmovlla0_w ();
+cp_v2si mep_cpmovlua0_w ();
+cp_v2si mep_cpmovula0_w ();
+cp_v2si mep_cpmovuua0_w ();
+cp_v4hi mep_cpmovla0_h ();
+cp_v4hi mep_cpmovua0_h ();
+cp_v8qi mep_cpmova0_b ();
+void mep_cpsetla0_w (cp_v2si, cp_v2si);
+void mep_cpsetua0_w (cp_v2si, cp_v2si);
+void mep_cpseta0_h (cp_v4hi, cp_v4hi);
+void mep_cpsadla0_h (cp_v4hi, cp_v4hi);
+void mep_cpsadua0_h (cp_v4hi, cp_v4hi);
+void mep_cpsada0_b (cp_v8qi, cp_v8qi);
+void mep_cpsada0u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpabsla0_h (cp_v4hi, cp_v4hi);
+void mep_cpabsua0_h (cp_v4hi, cp_v4hi);
+void mep_cpabsa0_b (cp_v8qi, cp_v8qi);
+void mep_cpabsa0u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpsubacla0_h (cp_v4hi, cp_v4hi);
+void mep_cpsubacua0_h (cp_v4hi, cp_v4hi);
+void mep_cpsubaca0_b (cp_v8qi, cp_v8qi);
+void mep_cpsubaca0u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpsubla0_h (cp_v4hi, cp_v4hi);
+void mep_cpsubua0_h (cp_v4hi, cp_v4hi);
+void mep_cpsuba0_b (cp_v8qi, cp_v8qi);
+void mep_cpsuba0u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpaddacla0_h (cp_v4hi, cp_v4hi);
+void mep_cpaddacua0_h (cp_v4hi, cp_v4hi);
+void mep_cpaddaca0_b (cp_v8qi, cp_v8qi);
+void mep_cpaddaca0u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpaddla0_h (cp_v4hi, cp_v4hi);
+void mep_cpaddua0_h (cp_v4hi, cp_v4hi);
+void mep_cpadda0_b (cp_v8qi, cp_v8qi);
+void mep_cpadda0u_b (cp_v8uqi, cp_v8uqi);
+void mep_c0nop (); // volatile
+void mep_cpsmsbslla1_w (cp_v2si, cp_v2si);
+void mep_cpsmsbslua1_w (cp_v2si, cp_v2si);
+void mep_cpsmsbslla1_h (cp_v4hi, cp_v4hi);
+void mep_cpsmsbslua1_h (cp_v4hi, cp_v4hi);
+void mep_cpsmadslla1_w (cp_v2si, cp_v2si);
+void mep_cpsmadslua1_w (cp_v2si, cp_v2si);
+void mep_cpsmadslla1_h (cp_v4hi, cp_v4hi);
+void mep_cpsmadslua1_h (cp_v4hi, cp_v4hi);
+void mep_cpmulslla1_w (cp_v2si, cp_v2si);
+void mep_cpmulslua1_w (cp_v2si, cp_v2si);
+void mep_cpmulslla1_h (cp_v4hi, cp_v4hi);
+void mep_cpmulslua1_h (cp_v4hi, cp_v4hi);
+void mep_cpsmsbla1_w (cp_v2si, cp_v2si);
+void mep_cpsmsbua1_w (cp_v2si, cp_v2si);
+void mep_cpsmsbla1_h (cp_v4hi, cp_v4hi);
+void mep_cpsmsbua1_h (cp_v4hi, cp_v4hi);
+void mep_cpsmadla1_w (cp_v2si, cp_v2si);
+void mep_cpsmadua1_w (cp_v2si, cp_v2si);
+void mep_cpsmadla1_h (cp_v4hi, cp_v4hi);
+void mep_cpsmadua1_h (cp_v4hi, cp_v4hi);
+void mep_cpmsbla1_w (cp_v2si, cp_v2si);
+void mep_cpmsbua1_w (cp_v2si, cp_v2si);
+void mep_cpmsbla1u_w (cp_v2usi, cp_v2usi);
+void mep_cpmsbua1u_w (cp_v2usi, cp_v2usi);
+void mep_cpmsbla1_h (cp_v4hi, cp_v4hi);
+void mep_cpmsbua1_h (cp_v4hi, cp_v4hi);
+void mep_cpmadla1_w (cp_v2si, cp_v2si);
+void mep_cpmadua1_w (cp_v2si, cp_v2si);
+void mep_cpmadla1u_w (cp_v2usi, cp_v2usi);
+void mep_cpmadua1u_w (cp_v2usi, cp_v2usi);
+void mep_cpmadla1_h (cp_v4hi, cp_v4hi);
+void mep_cpmadua1_h (cp_v4hi, cp_v4hi);
+void mep_cpmada1_b (cp_v8qi, cp_v8qi);
+void mep_cpmada1u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpmulla1_w (cp_v2si, cp_v2si);
+void mep_cpmulua1_w (cp_v2si, cp_v2si);
+void mep_cpmulla1u_w (cp_v2usi, cp_v2usi);
+void mep_cpmulua1u_w (cp_v2usi, cp_v2usi);
+void mep_cpmulla1_h (cp_v4hi, cp_v4hi);
+void mep_cpmulua1_h (cp_v4hi, cp_v4hi);
+void mep_cpmula1_b (cp_v8qi, cp_v8qi);
+void mep_cpmula1u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpssda1_b (cp_v8qi, cp_v8qi);
+void mep_cpssda1u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpssqa1_b (cp_v8qi, cp_v8qi);
+void mep_cpssqa1u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpsllia1 (long);
+void mep_cpsraia1 (long);
+void mep_cpsrlia1 (long);
+void mep_cpslla1 (cp_data_bus_int);
+void mep_cpsraa1 (cp_data_bus_int);
+void mep_cpsrla1 (cp_data_bus_int);
+cp_v2si mep_cpmovhla1_w ();
+cp_v2si mep_cpmovhua1_w ();
+cp_v2si mep_cppackla1_w ();
+cp_v2si mep_cppackua1_w ();
+cp_v4hi mep_cppackla1_h ();
+cp_v4hi mep_cppackua1_h ();
+cp_v8qi mep_cppacka1_b ();
+cp_v8uqi mep_cppacka1u_b ();
+cp_v2si mep_cpmovlla1_w ();
+cp_v2si mep_cpmovlua1_w ();
+cp_v2si mep_cpmovula1_w ();
+cp_v2si mep_cpmovuua1_w ();
+cp_v4hi mep_cpmovla1_h ();
+cp_v4hi mep_cpmovua1_h ();
+cp_v8qi mep_cpmova1_b ();
+void mep_cpsetla1_w (cp_v2si, cp_v2si);
+void mep_cpsetua1_w (cp_v2si, cp_v2si);
+void mep_cpseta1_h (cp_v4hi, cp_v4hi);
+void mep_cpsadla1_h (cp_v4hi, cp_v4hi);
+void mep_cpsadua1_h (cp_v4hi, cp_v4hi);
+void mep_cpsada1_b (cp_v8qi, cp_v8qi);
+void mep_cpsada1u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpabsla1_h (cp_v4hi, cp_v4hi);
+void mep_cpabsua1_h (cp_v4hi, cp_v4hi);
+void mep_cpabsa1_b (cp_v8qi, cp_v8qi);
+void mep_cpabsa1u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpsubacla1_h (cp_v4hi, cp_v4hi);
+void mep_cpsubacua1_h (cp_v4hi, cp_v4hi);
+void mep_cpsubaca1_b (cp_v8qi, cp_v8qi);
+void mep_cpsubaca1u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpsubla1_h (cp_v4hi, cp_v4hi);
+void mep_cpsubua1_h (cp_v4hi, cp_v4hi);
+void mep_cpsuba1_b (cp_v8qi, cp_v8qi);
+void mep_cpsuba1u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpaddacla1_h (cp_v4hi, cp_v4hi);
+void mep_cpaddacua1_h (cp_v4hi, cp_v4hi);
+void mep_cpaddaca1_b (cp_v8qi, cp_v8qi);
+void mep_cpaddaca1u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpaddla1_h (cp_v4hi, cp_v4hi);
+void mep_cpaddua1_h (cp_v4hi, cp_v4hi);
+void mep_cpadda1_b (cp_v8qi, cp_v8qi);
+void mep_cpadda1u_b (cp_v8uqi, cp_v8uqi);
+cp_data_bus_int mep_cdmovi (long);
+cp_data_bus_int mep_cdmoviu (long);
+cp_v2si mep_cpmovi_w (long);
+cp_v2usi mep_cpmoviu_w (long);
+cp_v4hi mep_cpmovi_h (long);
+cp_v4uhi mep_cpmoviu_h (long);
+cp_v8qi mep_cpmovi_b (long);
+cp_data_bus_int mep_cdclipi3 (cp_data_bus_int, long);
+cp_data_bus_int mep_cdclipiu3 (cp_data_bus_int, long);
+cp_v2si mep_cpclipi3_w (cp_v2si, long);
+cp_v2si mep_cpclipiu3_w (cp_v2si, long);
+cp_v2si mep_cpslai3_w (cp_v2si, long);
+cp_v4hi mep_cpslai3_h (cp_v4hi, long);
+cp_data_bus_int mep_cdslli3 (cp_data_bus_int, long);
+cp_v2si mep_cpslli3_w (cp_v2si, long);
+cp_v4hi mep_cpslli3_h (cp_v4hi, long);
+cp_v8qi mep_cpslli3_b (cp_v8qi, long);
+cp_data_bus_int mep_cdsrai3 (cp_data_bus_int, long);
+cp_v2si mep_cpsrai3_w (cp_v2si, long);
+cp_v4hi mep_cpsrai3_h (cp_v4hi, long);
+cp_v8qi mep_cpsrai3_b (cp_v8qi, long);
+cp_data_bus_int mep_cdsrli3 (cp_data_bus_int, long);
+cp_v2si mep_cpsrli3_w (cp_v2si, long);
+cp_v4hi mep_cpsrli3_h (cp_v4hi, long);
+cp_v8qi mep_cpsrli3_b (cp_v8qi, long);
+void mep_cpocmpge_w (cp_v2si, cp_v2si); // volatile
+void mep_cpocmpgeu_w (cp_v2usi, cp_v2usi); // volatile
+void mep_cpocmpge_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpocmpge_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpocmpgeu_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpocmpgt_w (cp_v2si, cp_v2si); // volatile
+void mep_cpocmpgtu_w (cp_v2usi, cp_v2usi); // volatile
+void mep_cpocmpgt_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpocmpgt_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpocmpgtu_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpocmpne_w (cp_v2si, cp_v2si); // volatile
+void mep_cpocmpne_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpocmpne_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpocmpeq_w (cp_v2si, cp_v2si); // volatile
+void mep_cpocmpeq_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpocmpeq_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpacmpge_w (cp_v2si, cp_v2si); // volatile
+void mep_cpacmpgeu_w (cp_v2usi, cp_v2usi); // volatile
+void mep_cpacmpge_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpacmpge_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpacmpgeu_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpacmpgt_w (cp_v2si, cp_v2si); // volatile
+void mep_cpacmpgtu_w (cp_v2usi, cp_v2usi); // volatile
+void mep_cpacmpgt_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpacmpgt_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpacmpgtu_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpacmpne_w (cp_v2si, cp_v2si); // volatile
+void mep_cpacmpne_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpacmpne_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpacmpeq_w (cp_v2si, cp_v2si); // volatile
+void mep_cpacmpeq_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpacmpeq_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpcmpge_w (cp_v2si, cp_v2si);
+void mep_cpcmpgeu_w (cp_v2usi, cp_v2usi);
+void mep_cpcmpge_h (cp_v4hi, cp_v4hi);
+void mep_cpcmpge_b (cp_v8qi, cp_v8qi);
+void mep_cpcmpgeu_b (cp_v8uqi, cp_v8uqi);
+void mep_cpcmpgt_w (cp_v2si, cp_v2si);
+void mep_cpcmpgtu_w (cp_v2usi, cp_v2usi);
+void mep_cpcmpgt_h (cp_v4hi, cp_v4hi);
+void mep_cpcmpgt_b (cp_v8qi, cp_v8qi);
+void mep_cpcmpgtu_b (cp_v8uqi, cp_v8uqi);
+void mep_cpcmpne_w (cp_v2si, cp_v2si);
+void mep_cpcmpne_h (cp_v4hi, cp_v4hi);
+void mep_cpcmpne_b (cp_v8qi, cp_v8qi);
+void mep_cpcmpeq_w (cp_v2si, cp_v2si);
+void mep_cpcmpeq_h (cp_v4hi, cp_v4hi);
+void mep_cpcmpeq_b (cp_v8qi, cp_v8qi);
+void mep_cpcmpeqz_b (cp_v8qi, cp_v8qi);
+cp_data_bus_int mep_cdcastw (cp_data_bus_int);
+cp_data_bus_int mep_cdcastuw (cp_data_bus_int);
+cp_v2si mep_cpcasth_w (cp_v2si);
+cp_v2si mep_cpcastuh_w (cp_v2si);
+cp_v2si mep_cpcastb_w (cp_v2si);
+cp_v2si mep_cpcastub_w (cp_v2si);
+cp_v4hi mep_cpcastb_h (cp_v4hi);
+cp_v4hi mep_cpcastub_h (cp_v4hi);
+cp_v4hi mep_cpextl_h (cp_v4hi);
+cp_v4uhi mep_cpextlu_h (cp_v4uhi);
+cp_v8qi mep_cpextl_b (cp_v8qi);
+cp_v8uqi mep_cpextlu_b (cp_v8uqi);
+cp_v4uhi mep_cpextu_h (cp_v4uhi);
+cp_v4uhi mep_cpextuu_h (cp_v4uhi);
+cp_v8uqi mep_cpextu_b (cp_v8uqi);
+cp_v8uqi mep_cpextuu_b (cp_v8uqi);
+cp_v2si mep_cpbcast_w (cp_v2si);
+cp_v4hi mep_cpbcast_h (cp_v4hi);
+cp_v8qi mep_cpbcast_b (cp_v8qi);
+void mep_cpccadd_b (cp_v8qi*);
+cp_v2si mep_cphadd_w (cp_v2si);
+cp_v4hi mep_cphadd_h (cp_v4hi);
+cp_v8qi mep_cphadd_b (cp_v8qi);
+cp_v8uqi mep_cphaddu_b (cp_v8uqi);
+cp_v2si mep_cpnorm_w (cp_v2si);
+cp_v4hi mep_cpnorm_h (cp_v4hi);
+cp_v2si mep_cpldz_w (cp_v2si);
+cp_v4hi mep_cpldz_h (cp_v4hi);
+cp_v2si mep_cpabsz_w (cp_v2si);
+cp_v4hi mep_cpabsz_h (cp_v4hi);
+cp_v8qi mep_cpabsz_b (cp_v8qi);
+void mep_cpmovtocc (cp_data_bus_int); // volatile
+void mep_cpmovtocsar1 (cp_data_bus_int); // volatile
+void mep_cpmovtocsar0 (cp_data_bus_int); // volatile
+cp_data_bus_int mep_cpmovfrcc ();
+cp_data_bus_int mep_cpmovfrcsar1 ();
+cp_data_bus_int mep_cpmovfrcsar0 ();
+cp_v2si mep_cpmin3_w (cp_v2si, cp_v2si);
+cp_v2si mep_cpminu3_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpmin3_h (cp_v4hi, cp_v4hi);
+cp_v8qi mep_cpmin3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpminu3_b (cp_v8qi, cp_v8qi);
+cp_v2si mep_cpmax3_w (cp_v2si, cp_v2si);
+cp_v2si mep_cpmaxu3_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpmax3_h (cp_v4hi, cp_v4hi);
+cp_v8qi mep_cpmax3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpmaxu3_b (cp_v8qi, cp_v8qi);
+cp_v4hi mep_cpabs3_h (cp_v4hi, cp_v4hi);
+cp_v8qi mep_cpabs3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpabsu3_b (cp_v8qi, cp_v8qi);
+cp_v2si mep_cpaddsr3_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpaddsr3_h (cp_v4hi, cp_v4hi);
+cp_v8qi mep_cpaddsr3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpaddsru3_b (cp_v8qi, cp_v8qi);
+cp_v2si mep_cpave3_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpave3_h (cp_v4hi, cp_v4hi);
+cp_v8qi mep_cpave3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpaveu3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpextlsub3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpextlsubu3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpextusub3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpextusubu3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpextladd3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpextladdu3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpextuadd3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpextuaddu3_b (cp_v8qi, cp_v8qi);
+cp_v2si mep_cpssub3_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpssub3_h (cp_v4hi, cp_v4hi);
+cp_v2si mep_cpsadd3_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpsadd3_h (cp_v4hi, cp_v4hi);
+cp_v2si mep_cpsla3_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpsla3_h (cp_v4hi, cp_v4hi);
+cp_data_bus_int mep_cdsll3 (cp_data_bus_int, cp_data_bus_int);
+cp_v2si mep_cpssll3_w (cp_v2si, cp_v2si);
+cp_v2si mep_cpsll3_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpssll3_h (cp_v4hi, cp_v4hi);
+cp_v4hi mep_cpsll3_h (cp_v4hi, cp_v4hi);
+cp_v8qi mep_cpssll3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpsll3_b (cp_v8qi, cp_v8qi);
+cp_data_bus_int mep_cdsra3 (cp_data_bus_int, cp_data_bus_int);
+cp_v2si mep_cpssra3_w (cp_v2si, cp_v2si);
+cp_v2si mep_cpsra3_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpssra3_h (cp_v4hi, cp_v4hi);
+cp_v4hi mep_cpsra3_h (cp_v4hi, cp_v4hi);
+cp_v8qi mep_cpssra3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpsra3_b (cp_v8qi, cp_v8qi);
+cp_data_bus_int mep_cdsrl3 (cp_data_bus_int, cp_data_bus_int);
+cp_v2si mep_cpssrl3_w (cp_v2si, cp_v2si);
+cp_v2si mep_cpsrl3_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpssrl3_h (cp_v4hi, cp_v4hi);
+cp_v4hi mep_cpsrl3_h (cp_v4hi, cp_v4hi);
+cp_v8qi mep_cpssrl3_b (cp_v8qi, cp_v8qi);
+cp_v8qi mep_cpsrl3_b (cp_v8qi, cp_v8qi);
+cp_v4hi mep_cppack_h (cp_v4hi, cp_v4hi);
+cp_v8qi mep_cppack_b (cp_v8qi, cp_v8qi);
+cp_v8uqi mep_cppacku_b (cp_v8uqi, cp_v8uqi);
+cp_v2si mep_cpunpackl_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpunpackl_h (cp_v4hi, cp_v4hi);
+cp_v8qi mep_cpunpackl_b (cp_v8qi, cp_v8qi);
+cp_v2usi mep_cpunpacku_w (cp_v2usi, cp_v2usi);
+cp_v4uhi mep_cpunpacku_h (cp_v4uhi, cp_v4uhi);
+cp_v8uqi mep_cpunpacku_b (cp_v8uqi, cp_v8uqi);
+cp_data_bus_int mep_cpfsftbs1 (cp_data_bus_int, cp_data_bus_int);
+cp_data_bus_int mep_cpfsftbs0 (cp_data_bus_int, cp_data_bus_int);
+cp_data_bus_int mep_cpfsftbi (cp_data_bus_int, cp_data_bus_int, long);
+cp_data_bus_int mep_cpsel (cp_data_bus_int, cp_data_bus_int);
+cp_vector mep_cpxor3 (cp_vector, cp_vector);
+cp_vector mep_cpnor3 (cp_vector, cp_vector);
+cp_vector mep_cpor3 (cp_vector, cp_vector);
+cp_vector mep_cpand3 (cp_vector, cp_vector);
+cp_data_bus_int mep_cdsub3 (cp_data_bus_int, cp_data_bus_int);
+cp_v2si mep_cpsub3_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpsub3_h (cp_v4hi, cp_v4hi);
+cp_v8qi mep_cpsub3_b (cp_v8qi, cp_v8qi);
+cp_data_bus_int mep_cdadd3 (cp_data_bus_int, cp_data_bus_int);
+cp_v2si mep_cpadd3_w (cp_v2si, cp_v2si);
+cp_v4hi mep_cpadd3_h (cp_v4hi, cp_v4hi);
+cp_v8qi mep_cpadd3_b (cp_v8qi, cp_v8qi);
+void mep_cmovh_rn_crm_p0 (long, long); // volatile
+void mep_cmovh_crn_rm_p0 (long, long); // volatile
+void mep_cmovc_rn_ccrm_p0 (long, long); // volatile
+void mep_cmovc_ccrn_rm_p0 (long, long); // volatile
+void mep_cmov_rn_crm_p0 (long, long); // volatile
+void mep_cmov_crn_rm_p0 (long, long); // volatile
+void mep_bsrv (void *);
+void mep_jsrv (long);
+void mep_synccp (); // volatile
+void mep_bcpaf (long, void *);
+void mep_bcpat (long, void *);
+void mep_bcpne (long, void *);
+void mep_bcpeq (long, void *);
+void mep_lmcpm1 (cp_data_bus_int*, long **, long);
+void mep_smcpm1 (cp_data_bus_int, long **, long);
+void mep_lwcpm1 (cp_data_bus_int*, long **, long);
+void mep_swcpm1 (cp_data_bus_int, long **, long);
+void mep_lhcpm1 (cp_data_bus_int*, long **, long);
+void mep_shcpm1 (cp_data_bus_int, long **, long);
+void mep_lbcpm1 (cp_data_bus_int*, long **, long);
+void mep_sbcpm1 (cp_data_bus_int, long **, long);
+void mep_lmcpm0 (cp_data_bus_int*, long **, long);
+void mep_smcpm0 (cp_data_bus_int, long **, long);
+void mep_lwcpm0 (cp_data_bus_int*, long **, long);
+void mep_swcpm0 (cp_data_bus_int, long **, long);
+void mep_lhcpm0 (cp_data_bus_int*, long **, long);
+void mep_shcpm0 (cp_data_bus_int, long **, long);
+void mep_lbcpm0 (cp_data_bus_int*, long **, long);
+void mep_sbcpm0 (cp_data_bus_int, long **, long);
+void mep_lmcpa (cp_data_bus_int*, long **, long);
+void mep_smcpa (cp_data_bus_int, long **, long);
+void mep_lwcpa (cp_data_bus_int*, long **, long);
+void mep_swcpa (cp_data_bus_int, long **, long);
+void mep_lhcpa (cp_data_bus_int*, long **, long);
+void mep_shcpa (cp_data_bus_int, long **, long);
+void mep_lbcpa (cp_data_bus_int*, long **, long);
+void mep_sbcpa (cp_data_bus_int, long **, long);
+void mep_lmcp16 (cp_data_bus_int*, long, long *);
+void mep_smcp16 (cp_data_bus_int, long, long *); // volatile
+void mep_lwcp16 (cp_data_bus_int*, long, long *);
+void mep_swcp16 (cp_data_bus_int, long, long *);
+void mep_lmcpi (cp_data_bus_int*, long **);
+void mep_smcpi (cp_data_bus_int, long **);
+void mep_lwcpi (cp_data_bus_int*, long **);
+void mep_swcpi (cp_data_bus_int, long **);
+void mep_lmcp (cp_data_bus_int*, long *);
+void mep_smcp (cp_data_bus_int, long *); // volatile
+void mep_lwcp (cp_data_bus_int*, long *);
+void mep_swcp (cp_data_bus_int, long *);
+void mep_ssubu (long*, long);
+void mep_saddu (long*, long);
+void mep_ssub (long*, long);
+void mep_sadd (long*, long);
+void mep_clipu (long*, long);
+void mep_clip (long*, long);
+void mep_maxu (long*, long);
+void mep_minu (long*, long);
+void mep_max (long*, long);
+void mep_min (long*, long);
+void mep_ave (long*, long);
+void mep_abs (long*, long);
+void mep_ldz (long*, long);
+void mep_dbreak (); // volatile
+void mep_dret ();
+void mep_divu (long, long);
+void mep_div (long, long);
+void mep_maddru (long*, long);
+void mep_maddr (long*, long);
+void mep_maddu (long, long);
+void mep_madd (long, long);
+void mep_mulru (long*, long);
+void mep_mulr (long*, long);
+void mep_mulu (long, long);
+void mep_mul (long, long);
+void mep_cache (long, long *); // volatile
+void mep_tas (long*, long *);
+void mep_btstm (long*, long *, long);
+void mep_bnotm (long *, long);
+void mep_bclrm (long *, long);
+void mep_bsetm (long *, long);
+void mep_ldcb (long*, long); // volatile
+void mep_stcb (long, long); // volatile
+void mep_syncm (); // volatile
+void mep_break (); // volatile
+void mep_swi (long); // volatile
+void mep_sleep (); // volatile
+void mep_halt (); // volatile
+void mep_reti ();
+void mep_ei (); // volatile
+void mep_di (); // volatile
+void mep_ldc (long*, long); // volatile
+void mep_ldc_lo (long*);
+void mep_ldc_hi (long*);
+void mep_ldc_lp (long*);
+void mep_stc (long, long); // volatile
+void mep_stc_lo (long);
+void mep_stc_hi (long);
+void mep_stc_lp (long);
+void mep_erepeat (void *);
+void mep_repeat (long, void *);
+void mep_ret ();
+void mep_jsr (long);
+void mep_jmp24 (void *);
+void mep_jmp (long);
+void mep_bsr24 (void *);
+void mep_bsr12 (void *);
+void mep_bne (long, long, void *);
+void mep_beq (long, long, void *);
+void mep_bgei (long, long, void *);
+void mep_blti (long, long, void *);
+void mep_bnei (long, long, void *);
+void mep_beqi (long, long, void *);
+void mep_bnez (long, void *);
+void mep_beqz (long, void *);
+void mep_bra (void *);
+void mep_fsft (long*, long);
+void mep_sll3 (long*, long, long);
+void mep_slli (long*, long);
+void mep_srli (long*, long);
+void mep_srai (long*, long);
+void mep_sll (long*, long);
+void mep_srl (long*, long);
+void mep_sra (long*, long);
+void mep_xor3 (long*, long, long);
+void mep_and3 (long*, long, long);
+void mep_or3 (long*, long, long);
+void mep_nor (long*, long);
+void mep_xor (long*, long);
+void mep_and (long*, long);
+void mep_or (long*, long);
+void mep_sltu3x (long*, long, long);
+void mep_slt3x (long*, long, long);
+void mep_add3x (long*, long, long);
+void mep_sl2ad3 (long*, long, long);
+void mep_sl1ad3 (long*, long, long);
+void mep_sltu3i (long*, long, long);
+void mep_slt3i (long*, long, long);
+void mep_sltu3 (long*, long, long);
+void mep_slt3 (long*, long, long);
+void mep_neg (long*, long);
+void mep_sbvck3 (long*, long, long);
+void mep_sub (long*, long);
+void mep_advck3 (long*, long, long);
+void mep_add3i (long*, long);
+void mep_add (long*, long);
+void mep_add3 (long*, long, long);
+void mep_movh (long*, long);
+void mep_movu16 (long*, long);
+void mep_movu24 (long*, long);
+void mep_movi16 (long*, long);
+void mep_movi8 (long*, long);
+void mep_mov (long*, long);
+void mep_ssarb (long, long);
+void mep_extuh (long*);
+void mep_extub (long*);
+void mep_exth (long*);
+void mep_extb (long*);
+void mep_lw24 (long*, long);
+void mep_sw24 (long, long);
+void mep_lhu16 (long*, long, long *);
+void mep_lbu16 (long*, long, long *);
+void mep_lw16 (long*, long, long *);
+void mep_lh16 (long*, long, long *);
+void mep_lb16 (long*, long, long *);
+void mep_sw16 (long, long, long *);
+void mep_sh16 (long, long, long *);
+void mep_sb16 (long, long, long *);
+void mep_lhu_tp (long*, long);
+void mep_lbu_tp (long*, long);
+void mep_lw_tp (long*, long);
+void mep_lh_tp (long*, long);
+void mep_lb_tp (long*, long);
+void mep_sw_tp (long, long);
+void mep_sh_tp (long, long);
+void mep_sb_tp (long, long);
+void mep_lw_sp (long*, long);
+void mep_sw_sp (long, long);
+void mep_lhu (long*, long *);
+void mep_lbu (long*, long *);
+void mep_lw (long*, long *);
+void mep_lh (long*, long *);
+void mep_lb (long*, long *);
+void mep_sw (long, long *);
+void mep_sh (long, long *);
+void mep_sb (long, long *);
+void mep_dsp1 (long*, long); // volatile
+void mep_dsp0 (long); // volatile
+void mep_dsp (long*, long, long); // volatile
+void mep_uci (long*, long, long); // volatile
+void mep_lhucpm1 (cp_data_bus_int*, long **, long);
+void mep_lbucpm1 (cp_data_bus_int*, long **, long);
+void mep_lhucpm0 (cp_data_bus_int*, long **, long);
+void mep_lbucpm0 (cp_data_bus_int*, long **, long);
+void mep_lhucpa (cp_data_bus_int*, long **, long);
+void mep_lbucpa (cp_data_bus_int*, long **, long);
+void mep_lhucp (cp_data_bus_int*, long, long *);
+void mep_lhcp (cp_data_bus_int*, long, long *);
+void mep_shcp (cp_data_bus_int, long, long *);
+void mep_lbucp (cp_data_bus_int*, long, long *);
+void mep_lbcp (cp_data_bus_int*, long, long *);
+void mep_sbcp (cp_data_bus_int, long, long *);
+void mep_casw3 (long*, long, long); // volatile
+void mep_cash3 (long*, long, long); // volatile
+void mep_casb3 (long*, long, long); // volatile
+void mep_prefd (long, long, long *); // volatile
+void mep_pref (long, long *); // volatile
+void mep_ldcb_r (long*, long *); // volatile
+void mep_stcb_r (long, long *); // volatile
+void mep_cmovh2 (long*, cp_data_bus_int);
+void mep_cmovh1 (cp_data_bus_int*, long);
+void mep_cmovc2 (long*, long); // volatile
+void mep_cmovc1 (long, long); // volatile
+void mep_cmov2 (long*, cp_data_bus_int);
+void mep_cmov1 (cp_data_bus_int*, long);
+cp_data_bus_int mep_cpmov (cp_data_bus_int);
--- /dev/null
+
+
+;; DO NOT EDIT: This file is automatically generated by CGEN.
+;; Any changes you make will be discarded when it is next regenerated.
+
+
+(define_predicate "cgen_h_sint_12a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= -2048
+ && INTVAL (op) < 2048")))
+
+(define_predicate "cgen_h_uint_20a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 1048576")))
+
+(define_predicate "cgen_h_uint_7a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 128")))
+
+(define_predicate "cgen_h_uint_6a2_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 1) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 128")))
+
+(define_predicate "cgen_h_uint_22a4_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 3) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 33554432")))
+
+(define_predicate "cgen_h_sint_2a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= -2
+ && INTVAL (op) < 2")))
+
+(define_predicate "cgen_h_uint_24a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 16777216")))
+
+(define_predicate "cgen_h_sint_6a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= -32
+ && INTVAL (op) < 32")))
+
+(define_predicate "cgen_h_uint_5a4_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 3) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 256")))
+
+(define_predicate "cgen_h_uint_2a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 4")))
+
+(define_predicate "cgen_h_sint_10a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= -512
+ && INTVAL (op) < 512")))
+
+(define_predicate "cgen_h_uint_4a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 16")))
+
+(define_predicate "cgen_h_uint_6a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 64")))
+
+(define_predicate "cgen_h_uint_16a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 65536")))
+
+(define_predicate "cgen_h_uint_8a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 256")))
+
+(define_predicate "cgen_h_sint_16a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= -32768
+ && INTVAL (op) < 32768")))
+
+(define_predicate "cgen_h_uint_5a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 32")))
+
+(define_predicate "cgen_h_sint_8a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= -128
+ && INTVAL (op) < 128")))
+
+(define_predicate "cgen_h_uint_3a1_immediate"
+ (and (match_code "const_int")
+ (match_test "(INTVAL (op) & 0) == 0
+ && INTVAL (op) >= 0
+ && INTVAL (op) < 8")))
+
+
+
+(define_insn "cgen_intrinsic_cpsmsbslla1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2198))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2199))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2200))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2201))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2202))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2203))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2204))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2205))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2206))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2207))]
+ "CGEN_ENABLE_INSN_P (0)"
+ "cpsmsbslla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbslla1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2198))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2199))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2200))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2201))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2202))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2203))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2204))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2205))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2206))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2207))]
+ "CGEN_ENABLE_INSN_P (1)"
+ "cpsmsbslla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbslua1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2208))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2209))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2210))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2211))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2212))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2213))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2214))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2215))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2216))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2217))]
+ "CGEN_ENABLE_INSN_P (2)"
+ "cpsmsbslua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbslua1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2208))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2209))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2210))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2211))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2212))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2213))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2214))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2215))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2216))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2217))]
+ "CGEN_ENABLE_INSN_P (3)"
+ "cpsmsbslua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbslla1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2218))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2219))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2220))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2221))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2222))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2223))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2224))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2225))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2226))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2227))]
+ "CGEN_ENABLE_INSN_P (4)"
+ "cpsmsbslla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbslla1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2218))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2219))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2220))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2221))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2222))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2223))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2224))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2225))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2226))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2227))]
+ "CGEN_ENABLE_INSN_P (5)"
+ "cpsmsbslla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbslua1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2228))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2229))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2230))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2231))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2232))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2233))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2234))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2235))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2236))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2237))]
+ "CGEN_ENABLE_INSN_P (6)"
+ "cpsmsbslua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbslua1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2228))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2229))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2230))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2231))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2232))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2233))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2234))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2235))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2236))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2237))]
+ "CGEN_ENABLE_INSN_P (7)"
+ "cpsmsbslua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadslla1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2238))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2239))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2240))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2241))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2242))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2243))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2244))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2245))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2246))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2247))]
+ "CGEN_ENABLE_INSN_P (8)"
+ "cpsmadslla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadslla1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2238))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2239))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2240))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2241))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2242))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2243))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2244))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2245))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2246))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2247))]
+ "CGEN_ENABLE_INSN_P (9)"
+ "cpsmadslla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadslua1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2248))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2249))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2250))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2251))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2252))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2253))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2254))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2255))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2256))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2257))]
+ "CGEN_ENABLE_INSN_P (10)"
+ "cpsmadslua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadslua1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2248))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2249))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2250))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2251))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2252))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2253))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2254))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2255))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2256))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2257))]
+ "CGEN_ENABLE_INSN_P (11)"
+ "cpsmadslua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadslla1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2258))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2259))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2260))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2261))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2262))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2263))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2264))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2265))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2266))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2267))]
+ "CGEN_ENABLE_INSN_P (12)"
+ "cpsmadslla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadslla1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2258))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2259))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2260))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2261))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2262))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2263))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2264))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2265))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2266))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2267))]
+ "CGEN_ENABLE_INSN_P (13)"
+ "cpsmadslla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadslua1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2268))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2269))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2270))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2271))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2272))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2273))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2274))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2275))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2276))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2277))]
+ "CGEN_ENABLE_INSN_P (14)"
+ "cpsmadslua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadslua1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2268))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2269))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2270))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2271))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2272))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2273))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2274))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2275))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2276))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2277))]
+ "CGEN_ENABLE_INSN_P (15)"
+ "cpsmadslua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulslla1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2278))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2279))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2280))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2281))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2282))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2283))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2284))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2285))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2286))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2287))]
+ "CGEN_ENABLE_INSN_P (16)"
+ "cpmulslla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulslla1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2278))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2279))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2280))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2281))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2282))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2283))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2284))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2285))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2286))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2287))]
+ "CGEN_ENABLE_INSN_P (17)"
+ "cpmulslla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulslua1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2288))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2289))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2290))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2291))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2292))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2293))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2294))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2295))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2296))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2297))]
+ "CGEN_ENABLE_INSN_P (18)"
+ "cpmulslua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulslua1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2288))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2289))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2290))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2291))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2292))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2293))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2294))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2295))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2296))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2297))]
+ "CGEN_ENABLE_INSN_P (19)"
+ "cpmulslua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulslla1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2298))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2299))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2300))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2301))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2302))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2303))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2304))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2305))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2306))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2307))]
+ "CGEN_ENABLE_INSN_P (20)"
+ "cpmulslla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulslla1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2298))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2299))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2300))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2301))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2302))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2303))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2304))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2305))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2306))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2307))]
+ "CGEN_ENABLE_INSN_P (21)"
+ "cpmulslla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulslua1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2308))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2309))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2310))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2311))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2312))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2313))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2314))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2315))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2316))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2317))]
+ "CGEN_ENABLE_INSN_P (22)"
+ "cpmulslua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulslua1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2308))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2309))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2310))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2311))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2312))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2313))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2314))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2315))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2316))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2317))]
+ "CGEN_ENABLE_INSN_P (23)"
+ "cpmulslua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbla1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2318))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2319))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2320))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2321))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2322))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2323))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2324))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2325))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2326))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2327))]
+ "CGEN_ENABLE_INSN_P (24)"
+ "cpsmsbla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbla1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2318))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2319))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2320))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2321))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2322))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2323))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2324))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2325))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2326))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2327))]
+ "CGEN_ENABLE_INSN_P (25)"
+ "cpsmsbla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbua1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2328))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2329))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2330))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2331))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2332))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2333))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2334))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2335))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2336))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2337))]
+ "CGEN_ENABLE_INSN_P (26)"
+ "cpsmsbua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbua1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2328))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2329))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2330))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2331))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2332))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2333))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2334))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2335))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2336))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2337))]
+ "CGEN_ENABLE_INSN_P (27)"
+ "cpsmsbua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbla1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2338))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2339))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2340))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2341))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2342))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2343))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2344))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2345))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2346))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2347))]
+ "CGEN_ENABLE_INSN_P (28)"
+ "cpsmsbla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbla1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2338))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2339))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2340))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2341))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2342))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2343))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2344))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2345))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2346))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2347))]
+ "CGEN_ENABLE_INSN_P (29)"
+ "cpsmsbla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbua1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2348))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2349))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2350))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2351))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2352))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2353))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2354))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2355))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2356))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2357))]
+ "CGEN_ENABLE_INSN_P (30)"
+ "cpsmsbua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmsbua1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2348))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2349))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2350))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2351))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2352))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2353))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2354))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2355))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2356))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2357))]
+ "CGEN_ENABLE_INSN_P (31)"
+ "cpsmsbua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadla1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2358))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2359))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2360))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2361))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2362))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2363))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2364))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2365))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2366))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2367))]
+ "CGEN_ENABLE_INSN_P (32)"
+ "cpsmadla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadla1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2358))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2359))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2360))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2361))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2362))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2363))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2364))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2365))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2366))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2367))]
+ "CGEN_ENABLE_INSN_P (33)"
+ "cpsmadla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadua1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2368))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2369))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2370))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2371))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2372))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2373))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2374))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2375))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2376))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2377))]
+ "CGEN_ENABLE_INSN_P (34)"
+ "cpsmadua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadua1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2368))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2369))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2370))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2371))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2372))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2373))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2374))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2375))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2376))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2377))]
+ "CGEN_ENABLE_INSN_P (35)"
+ "cpsmadua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadla1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2378))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2379))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2380))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2381))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2382))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2383))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2384))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2385))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2386))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2387))]
+ "CGEN_ENABLE_INSN_P (36)"
+ "cpsmadla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadla1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2378))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2379))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2380))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2381))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2382))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2383))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2384))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2385))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2386))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2387))]
+ "CGEN_ENABLE_INSN_P (37)"
+ "cpsmadla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadua1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2388))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2389))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2390))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2391))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2392))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2393))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2394))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2395))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2396))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2397))]
+ "CGEN_ENABLE_INSN_P (38)"
+ "cpsmadua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsmadua1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2388))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2389))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2390))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2391))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2392))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2393))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2394))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2395))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2396))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2397))]
+ "CGEN_ENABLE_INSN_P (39)"
+ "cpsmadua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmsbla1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2398))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2399))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2400))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2401))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2402))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2403))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2404))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2405))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2406))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2407))]
+ "CGEN_ENABLE_INSN_P (40)"
+ "cpmsbla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmsbla1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2398))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2399))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2400))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2401))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2402))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2403))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2404))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2405))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2406))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2407))]
+ "CGEN_ENABLE_INSN_P (41)"
+ "cpmsbla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmsbua1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2408))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2409))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2410))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2411))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2412))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2413))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2414))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2415))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2416))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2417))]
+ "CGEN_ENABLE_INSN_P (42)"
+ "cpmsbua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmsbua1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2408))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2409))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2410))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2411))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2412))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2413))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2414))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2415))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2416))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2417))]
+ "CGEN_ENABLE_INSN_P (43)"
+ "cpmsbua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmsbla1u_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2418))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2419))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2420))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2421))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2422))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2423))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2424))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2425))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2426))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2427))]
+ "CGEN_ENABLE_INSN_P (44)"
+ "cpmsbla1u.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmsbla1u_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2418))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2419))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2420))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2421))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2422))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2423))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2424))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2425))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2426))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2427))]
+ "CGEN_ENABLE_INSN_P (45)"
+ "cpmsbla1u.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmsbua1u_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2428))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2429))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2430))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2431))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2432))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2433))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2434))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2435))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2436))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2437))]
+ "CGEN_ENABLE_INSN_P (46)"
+ "cpmsbua1u.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmsbua1u_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2428))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2429))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2430))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2431))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2432))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2433))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2434))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2435))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2436))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2437))]
+ "CGEN_ENABLE_INSN_P (47)"
+ "cpmsbua1u.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmsbla1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2438))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2439))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2440))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2441))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2442))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2443))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2444))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2445))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2446))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2447))]
+ "CGEN_ENABLE_INSN_P (48)"
+ "cpmsbla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmsbla1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2438))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2439))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2440))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2441))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2442))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2443))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2444))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2445))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2446))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2447))]
+ "CGEN_ENABLE_INSN_P (49)"
+ "cpmsbla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmsbua1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2448))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2449))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2450))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2451))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2452))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2453))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2454))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2455))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2456))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2457))]
+ "CGEN_ENABLE_INSN_P (50)"
+ "cpmsbua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmsbua1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2448))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2449))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2450))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2451))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2452))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2453))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2454))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2455))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2456))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2457))]
+ "CGEN_ENABLE_INSN_P (51)"
+ "cpmsbua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmadla1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2458))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2459))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2460))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2461))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2462))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2463))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2464))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2465))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2466))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2467))]
+ "CGEN_ENABLE_INSN_P (52)"
+ "cpmadla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmadla1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2458))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2459))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2460))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2461))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2462))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2463))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2464))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2465))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2466))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2467))]
+ "CGEN_ENABLE_INSN_P (53)"
+ "cpmadla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmadua1_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2468))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2469))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2470))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2471))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2472))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2473))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2474))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2475))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2476))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2477))]
+ "CGEN_ENABLE_INSN_P (54)"
+ "cpmadua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmadua1_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2468))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2469))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2470))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2471))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2472))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2473))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2474))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2475))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2476))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2477))]
+ "CGEN_ENABLE_INSN_P (55)"
+ "cpmadua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmadla1u_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2478))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2479))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2480))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2481))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2482))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2483))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2484))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2485))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2486))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2487))]
+ "CGEN_ENABLE_INSN_P (56)"
+ "cpmadla1u.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmadla1u_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2478))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2479))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2480))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2481))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2482))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2483))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2484))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2485))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2486))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2487))]
+ "CGEN_ENABLE_INSN_P (57)"
+ "cpmadla1u.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmadua1u_w_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2488))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2489))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2490))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2491))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2492))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2493))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2494))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2495))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2496))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2497))]
+ "CGEN_ENABLE_INSN_P (58)"
+ "cpmadua1u.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmadua1u_w_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2488))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2489))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2490))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2491))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2492))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2493))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2494))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2495))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2496))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2497))]
+ "CGEN_ENABLE_INSN_P (59)"
+ "cpmadua1u.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmadla1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2498))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2499))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2500))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2501))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2502))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2503))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2504))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2505))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2506))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2507))]
+ "CGEN_ENABLE_INSN_P (60)"
+ "cpmadla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmadla1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2498))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2499))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2500))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2501))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2502))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2503))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2504))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2505))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2506))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2507))]
+ "CGEN_ENABLE_INSN_P (61)"
+ "cpmadla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmadua1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2508))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2509))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2510))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2511))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2512))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2513))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2514))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2515))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2516))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2517))]
+ "CGEN_ENABLE_INSN_P (62)"
+ "cpmadua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmadua1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2508))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2509))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2510))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2511))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2512))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2513))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2514))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2515))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2516))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2517))]
+ "CGEN_ENABLE_INSN_P (63)"
+ "cpmadua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmada1_b_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2518))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2519))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2520))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2521))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2522))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2523))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2524))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2525))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2526))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2527))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2528))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2529))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2530))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2531))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2532))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2533))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2534))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2535))]
+ "CGEN_ENABLE_INSN_P (64)"
+ "cpmada1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmada1_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2518))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2519))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2520))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2521))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2522))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2523))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2524))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2525))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2526))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2527))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2528))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2529))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2530))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2531))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2532))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2533))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2534))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2535))]
+ "CGEN_ENABLE_INSN_P (65)"
+ "cpmada1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmada1u_b_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2536))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2537))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2538))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2539))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2540))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2541))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2542))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2543))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2544))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2545))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2546))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2547))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2548))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2549))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2550))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2551))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2552))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2553))]
+ "CGEN_ENABLE_INSN_P (66)"
+ "cpmada1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmada1u_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2536))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2537))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2538))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2539))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2540))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2541))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2542))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2543))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2544))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2545))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2546))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2547))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2548))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2549))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2550))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2551))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2552))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2553))]
+ "CGEN_ENABLE_INSN_P (67)"
+ "cpmada1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulla1_w_C3"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2554))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2555))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2556))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2557))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2558))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2559))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2560))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2561))]
+ "CGEN_ENABLE_INSN_P (68)"
+ "cpmulla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulla1_w_P1"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2554))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2555))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2556))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2557))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2558))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2559))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2560))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2561))]
+ "CGEN_ENABLE_INSN_P (69)"
+ "cpmulla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulua1_w_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2562))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2563))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2564))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2565))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2566))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2567))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2568))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2569))]
+ "CGEN_ENABLE_INSN_P (70)"
+ "cpmulua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulua1_w_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2562))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2563))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2564))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2565))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2566))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2567))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2568))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2569))]
+ "CGEN_ENABLE_INSN_P (71)"
+ "cpmulua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulla1u_w_C3"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2570))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2571))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2572))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2573))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2574))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2575))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2576))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2577))]
+ "CGEN_ENABLE_INSN_P (72)"
+ "cpmulla1u.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulla1u_w_P1"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2570))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2571))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2572))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2573))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2574))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2575))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2576))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2577))]
+ "CGEN_ENABLE_INSN_P (73)"
+ "cpmulla1u.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulua1u_w_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2578))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2579))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2580))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2581))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2582))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2583))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2584))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2585))]
+ "CGEN_ENABLE_INSN_P (74)"
+ "cpmulua1u.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulua1u_w_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2578))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2579))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2580))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2581))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2582))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2583))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2584))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2585))]
+ "CGEN_ENABLE_INSN_P (75)"
+ "cpmulua1u.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulla1_h_C3"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2586))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2587))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2588))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2589))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2590))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2591))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2592))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2593))]
+ "CGEN_ENABLE_INSN_P (76)"
+ "cpmulla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulla1_h_P1"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2586))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2587))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2588))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2589))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2590))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2591))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2592))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2593))]
+ "CGEN_ENABLE_INSN_P (77)"
+ "cpmulla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulua1_h_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2594))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2595))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2596))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2597))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2598))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2599))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2600))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2601))]
+ "CGEN_ENABLE_INSN_P (78)"
+ "cpmulua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmulua1_h_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2594))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2595))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2596))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2597))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2598))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2599))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2600))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2601))]
+ "CGEN_ENABLE_INSN_P (79)"
+ "cpmulua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmula1_b_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2602))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2603))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2604))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2605))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2606))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2607))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2608))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2609))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2610))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2611))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2612))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2613))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2614))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2615))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2616))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2617))]
+ "CGEN_ENABLE_INSN_P (80)"
+ "cpmula1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmula1_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2602))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2603))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2604))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2605))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2606))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2607))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2608))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2609))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2610))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2611))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2612))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2613))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2614))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2615))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2616))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2617))]
+ "CGEN_ENABLE_INSN_P (81)"
+ "cpmula1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmula1u_b_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2618))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2619))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2620))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2621))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2622))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2623))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2624))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2625))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2626))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2627))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2628))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2629))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2630))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2631))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2632))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2633))]
+ "CGEN_ENABLE_INSN_P (82)"
+ "cpmula1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmula1u_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2618))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2619))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2620))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2621))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2622))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2623))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2624))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2625))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2626))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2627))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2628))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2629))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2630))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2631))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2632))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2633))]
+ "CGEN_ENABLE_INSN_P (83)"
+ "cpmula1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssda1_b_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2634))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2635))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2636))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2637))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2638))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2639))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2640))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2641))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2642))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2643))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2644))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2645))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2646))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2647))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2648))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2649))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2650))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2651))]
+ "CGEN_ENABLE_INSN_P (84)"
+ "cpssda1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssda1_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2634))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2635))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2636))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2637))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2638))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2639))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2640))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2641))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2642))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2643))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2644))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2645))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2646))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2647))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2648))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2649))]
+ "CGEN_ENABLE_INSN_P (85)"
+ "cpssda1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssda1u_b_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2650))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2651))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2652))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2653))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2654))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2655))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2656))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2657))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2658))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2659))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2660))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2661))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2662))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2663))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2664))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2665))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2666))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2667))]
+ "CGEN_ENABLE_INSN_P (86)"
+ "cpssda1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssda1u_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2650))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2651))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2652))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2653))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2654))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2655))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2656))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2657))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2658))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2659))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2660))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2661))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2662))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2663))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2664))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2665))]
+ "CGEN_ENABLE_INSN_P (87)"
+ "cpssda1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssqa1_b_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2666))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2667))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2668))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2669))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2670))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2671))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2672))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2673))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2674))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2675))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2676))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2677))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2678))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2679))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2680))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2681))]
+ "CGEN_ENABLE_INSN_P (88)"
+ "cpssqa1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssqa1_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2666))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2667))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2668))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2669))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2670))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2671))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2672))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2673))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2674))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2675))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2676))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2677))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2678))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2679))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2680))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2681))]
+ "CGEN_ENABLE_INSN_P (89)"
+ "cpssqa1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssqa1u_b_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2682))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2683))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2684))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2685))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2686))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2687))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2688))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2689))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2690))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2691))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2692))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2693))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2694))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2695))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2696))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2697))]
+ "CGEN_ENABLE_INSN_P (90)"
+ "cpssqa1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssqa1u_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2682))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2683))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2684))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2685))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2686))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2687))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2688))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2689))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2690))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2691))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2692))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2693))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2694))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2695))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2696))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2697))]
+ "CGEN_ENABLE_INSN_P (91)"
+ "cpssqa1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmadila1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
+ (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
+ ] 1000))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1001))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1002))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1003))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1004))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1005))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1006))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1007))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1008))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1009))]
+ "CGEN_ENABLE_INSN_P (92)"
+ "cpfmadila1.h\\t%0,%1,%2,%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmadiua1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
+ (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
+ ] 1010))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1011))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1012))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1013))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1014))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1015))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1016))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1017))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1018))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1019))]
+ "CGEN_ENABLE_INSN_P (93)"
+ "cpfmadiua1.h\\t%0,%1,%2,%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmadia1_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
+ (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
+ ] 1020))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1021))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1022))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1023))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1024))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1025))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1026))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1027))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1028))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1029))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1030))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1031))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1032))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1033))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1034))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1035))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1036))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1037))]
+ "CGEN_ENABLE_INSN_P (94)"
+ "cpfmadia1.b\\t%0,%1,%2,%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmadia1u_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
+ (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
+ ] 1038))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1039))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1040))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1041))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1042))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1043))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1044))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1045))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1046))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1047))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1048))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1049))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1050))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1051))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1052))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1053))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1054))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1055))]
+ "CGEN_ENABLE_INSN_P (95)"
+ "cpfmadia1u.b\\t%0,%1,%2,%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmulila1_h_P1"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
+ (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
+ ] 1056))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1057))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1058))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1059))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1060))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1061))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1062))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1063))]
+ "CGEN_ENABLE_INSN_P (96)"
+ "cpfmulila1.h\\t%0,%1,%2,%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmuliua1_h_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
+ (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
+ ] 1064))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1065))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1066))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1067))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1068))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1069))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1070))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1071))]
+ "CGEN_ENABLE_INSN_P (97)"
+ "cpfmuliua1.h\\t%0,%1,%2,%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmulia1_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
+ (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
+ ] 1072))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1073))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1074))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1075))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1076))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1077))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1078))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1079))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1080))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1081))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1082))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1083))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1084))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1085))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1086))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1087))]
+ "CGEN_ENABLE_INSN_P (98)"
+ "cpfmulia1.b\\t%0,%1,%2,%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmulia1u_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
+ (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
+ ] 1088))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1089))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1090))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1091))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1092))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1093))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1094))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1095))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1096))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1097))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1098))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1099))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1100))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1101))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1102))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 1103))]
+ "CGEN_ENABLE_INSN_P (99)"
+ "cpfmulia1u.b\\t%0,%1,%2,%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpamadila1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1104))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1105))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1106))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1107))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1108))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1109))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1110))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1111))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1112))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1113))]
+ "CGEN_ENABLE_INSN_P (100)"
+ "cpamadila1.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpamadiua1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1114))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1115))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1116))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1117))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1118))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1119))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1120))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1121))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1122))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1123))]
+ "CGEN_ENABLE_INSN_P (101)"
+ "cpamadiua1.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpamadia1_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1124))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1125))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1126))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1127))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1128))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1129))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1130))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1131))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1132))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1133))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1134))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1135))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1136))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1137))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1138))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1139))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1140))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1141))]
+ "CGEN_ENABLE_INSN_P (102)"
+ "cpamadia1.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpamadia1u_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1142))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1143))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1144))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1145))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1146))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1147))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1148))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1149))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1150))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1151))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1152))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1153))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1154))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1155))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1156))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1157))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1158))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1159))]
+ "CGEN_ENABLE_INSN_P (103)"
+ "cpamadia1u.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpamulila1_h_P1"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1160))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1161))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1162))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1163))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1164))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1165))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1166))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1167))]
+ "CGEN_ENABLE_INSN_P (104)"
+ "cpamulila1.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpamuliua1_h_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1168))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1169))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1170))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1171))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1172))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1173))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1174))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1175))]
+ "CGEN_ENABLE_INSN_P (105)"
+ "cpamuliua1.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpamulia1_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1176))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1177))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1178))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1179))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1180))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1181))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1182))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1183))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1184))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1185))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1186))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1187))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1188))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1189))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1190))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1191))]
+ "CGEN_ENABLE_INSN_P (106)"
+ "cpamulia1.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpamulia1u_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1192))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1193))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1194))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1195))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1196))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1197))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1198))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1199))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1200))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1201))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1202))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1203))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1204))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1205))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1206))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1207))]
+ "CGEN_ENABLE_INSN_P (107)"
+ "cpamulia1u.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmadila1s1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1208))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1209))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1210))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1211))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1212))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1213))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1214))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1215))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1216))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1217))]
+ "CGEN_ENABLE_INSN_P (108)"
+ "cpfmadila1s1.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmadiua1s1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1218))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1219))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1220))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1221))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1222))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1223))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1224))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1225))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1226))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1227))]
+ "CGEN_ENABLE_INSN_P (109)"
+ "cpfmadiua1s1.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmadia1s1_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1228))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1229))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1230))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1231))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1232))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1233))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1234))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1235))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1236))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1237))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1238))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1239))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1240))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1241))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1242))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1243))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1244))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1245))]
+ "CGEN_ENABLE_INSN_P (110)"
+ "cpfmadia1s1.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmadia1s1u_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1246))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1247))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1248))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1249))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1250))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1251))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1252))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1253))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1254))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1255))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1256))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1257))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1258))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1259))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1260))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1261))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1262))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1263))]
+ "CGEN_ENABLE_INSN_P (111)"
+ "cpfmadia1s1u.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmulila1s1_h_P1"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1264))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1265))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1266))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1267))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1268))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1269))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1270))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1271))]
+ "CGEN_ENABLE_INSN_P (112)"
+ "cpfmulila1s1.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmuliua1s1_h_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1272))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1273))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1274))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1275))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1276))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1277))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1278))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1279))]
+ "CGEN_ENABLE_INSN_P (113)"
+ "cpfmuliua1s1.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmulia1s1_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1280))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1281))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1282))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1283))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1284))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1285))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1286))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1287))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1288))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1289))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1290))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1291))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1292))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1293))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1294))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1295))]
+ "CGEN_ENABLE_INSN_P (114)"
+ "cpfmulia1s1.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmulia1s1u_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1296))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1297))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1298))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1299))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1300))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1301))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1302))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1303))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1304))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1305))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1306))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1307))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1308))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1309))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1310))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1311))]
+ "CGEN_ENABLE_INSN_P (115)"
+ "cpfmulia1s1u.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmadila1s0_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1312))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1313))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1314))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1315))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1316))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1317))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1318))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1319))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1320))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1321))]
+ "CGEN_ENABLE_INSN_P (116)"
+ "cpfmadila1s0.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmadiua1s0_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1322))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1323))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1324))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1325))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1326))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1327))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1328))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1329))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1330))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1331))]
+ "CGEN_ENABLE_INSN_P (117)"
+ "cpfmadiua1s0.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmadia1s0_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1332))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1333))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1334))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1335))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1336))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1337))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1338))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1339))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1340))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1341))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1342))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1343))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1344))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1345))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1346))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1347))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1348))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1349))]
+ "CGEN_ENABLE_INSN_P (118)"
+ "cpfmadia1s0.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmadia1s0u_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1350))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1351))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1352))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1353))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1354))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1355))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1356))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1357))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1358))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1359))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1360))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1361))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1362))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1363))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1364))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1365))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1366))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1367))]
+ "CGEN_ENABLE_INSN_P (119)"
+ "cpfmadia1s0u.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmulila1s0_h_P1"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1368))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1369))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1370))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1371))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1372))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1373))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1374))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1375))]
+ "CGEN_ENABLE_INSN_P (120)"
+ "cpfmulila1s0.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmuliua1s0_h_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1376))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1377))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1378))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1379))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1380))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1381))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1382))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1383))]
+ "CGEN_ENABLE_INSN_P (121)"
+ "cpfmuliua1s0.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmulia1s0_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1384))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1385))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1386))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1387))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1388))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1389))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1390))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1391))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1392))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1393))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1394))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1395))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1396))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1397))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1398))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1399))]
+ "CGEN_ENABLE_INSN_P (122)"
+ "cpfmulia1s0.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfmulia1s0u_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
+ ] 1400))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1401))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1402))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1403))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1404))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1405))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1406))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1407))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1408))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1409))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1410))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1411))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1412))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1413))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1414))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ ] 1415))]
+ "CGEN_ENABLE_INSN_P (123)"
+ "cpfmulia1s0u.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsllia1_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
+ ] 2698))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2699))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2700))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2701))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2702))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2703))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2704))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2705))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2706))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2707))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2708))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2709))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2710))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2711))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2712))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2713))]
+ "CGEN_ENABLE_INSN_P (124)"
+ "cpsllia1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsllia1_1_p1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
+ ] 2698))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2699))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2700))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2701))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2702))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2703))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2704))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2705))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2706))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2707))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2708))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2709))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2710))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2711))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2712))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2713))]
+ "CGEN_ENABLE_INSN_P (125)"
+ "cpsllia1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsraia1_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
+ ] 2714))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2715))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2716))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2717))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2718))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2719))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2720))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2721))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2722))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2723))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2724))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2725))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2726))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2727))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2728))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2729))]
+ "CGEN_ENABLE_INSN_P (126)"
+ "cpsraia1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsraia1_1_p1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
+ ] 2714))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2715))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2716))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2717))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2718))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2719))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2720))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2721))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2722))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2723))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2724))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2725))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2726))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2727))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2728))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2729))]
+ "CGEN_ENABLE_INSN_P (127)"
+ "cpsraia1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrlia1_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
+ ] 2730))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2731))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2732))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2733))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2734))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2735))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2736))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2737))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2738))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2739))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2740))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2741))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2742))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2743))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2744))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2745))]
+ "CGEN_ENABLE_INSN_P (128)"
+ "cpsrlia1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrlia1_1_p1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
+ ] 2730))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2731))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2732))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2733))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2734))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2735))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2736))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2737))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2738))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2739))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2740))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2741))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2742))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2743))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2744))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2745))]
+ "CGEN_ENABLE_INSN_P (129)"
+ "cpsrlia1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslla1_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 2746))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2747))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2748))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2749))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2750))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2751))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2752))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2753))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2754))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2755))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2756))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2757))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2758))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2759))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2760))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2761))]
+ "CGEN_ENABLE_INSN_P (130)"
+ "cpslla1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslla1_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 2746))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2747))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2748))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2749))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2750))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2751))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2752))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2753))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2754))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2755))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2756))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2757))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2758))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2759))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2760))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2761))]
+ "CGEN_ENABLE_INSN_P (131)"
+ "cpslla1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsraa1_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 2762))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2763))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2764))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2765))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2766))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2767))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2768))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2769))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2770))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2771))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2772))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2773))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2774))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2775))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2776))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2777))]
+ "CGEN_ENABLE_INSN_P (132)"
+ "cpsraa1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsraa1_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 2762))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2763))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2764))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2765))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2766))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2767))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2768))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2769))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2770))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2771))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2772))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2773))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2774))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2775))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2776))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2777))]
+ "CGEN_ENABLE_INSN_P (133)"
+ "cpsraa1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrla1_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 2778))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2779))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2780))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2781))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2782))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2783))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2784))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2785))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2786))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2787))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2788))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2789))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2790))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2791))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2792))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2793))]
+ "CGEN_ENABLE_INSN_P (134)"
+ "cpsrla1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrla1_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 2778))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2779))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2780))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2781))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2782))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2783))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2784))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2785))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2786))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2787))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2788))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2789))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2790))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2791))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2792))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ ] 2793))]
+ "CGEN_ENABLE_INSN_P (135)"
+ "cpsrla1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacswp_P1"
+ [(set (reg:SI 111)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1416))
+ (set (reg:SI 110)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1418))
+ (set (reg:SI 109)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1420))
+ (set (reg:SI 108)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1422))
+ (set (reg:SI 107)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1424))
+ (set (reg:SI 106)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1426))
+ (set (reg:SI 105)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1428))
+ (set (reg:SI 104)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1430))
+ (set (reg:SI 103)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1432))
+ (set (reg:SI 102)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1434))
+ (set (reg:SI 101)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1436))
+ (set (reg:SI 100)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1438))
+ (set (reg:SI 99)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1440))
+ (set (reg:SI 98)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1442))
+ (set (reg:SI 97)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1444))
+ (set (reg:SI 96)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 1446))]
+ "CGEN_ENABLE_INSN_P (136)"
+ "cpacswp"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaccpa1_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (const_int 0)
+ ] 1448))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (const_int 0)
+ ] 1449))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (const_int 0)
+ ] 1450))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (const_int 0)
+ ] 1451))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (const_int 0)
+ ] 1452))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (const_int 0)
+ ] 1453))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (const_int 0)
+ ] 1454))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (const_int 0)
+ ] 1455))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (const_int 0)
+ ] 1456))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (const_int 0)
+ ] 1457))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (const_int 0)
+ ] 1458))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (const_int 0)
+ ] 1459))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (const_int 0)
+ ] 1460))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (const_int 0)
+ ] 1461))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (const_int 0)
+ ] 1462))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (const_int 0)
+ ] 1463))]
+ "CGEN_ENABLE_INSN_P (137)"
+ "cpaccpa1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacsuma1_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (const_int 0)
+ ] 1464))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (const_int 0)
+ ] 1465))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (const_int 0)
+ ] 1466))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (const_int 0)
+ ] 1467))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (const_int 0)
+ ] 1468))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (const_int 0)
+ ] 1469))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (const_int 0)
+ ] 1470))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (const_int 0)
+ ] 1471))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (const_int 0)
+ ] 1472))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (const_int 0)
+ ] 1473))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (const_int 0)
+ ] 1474))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (const_int 0)
+ ] 1475))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (const_int 0)
+ ] 1476))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (const_int 0)
+ ] 1477))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (const_int 0)
+ ] 1478))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (const_int 0)
+ ] 1479))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (const_int 0)
+ ] 1480))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (const_int 0)
+ ] 1481))]
+ "CGEN_ENABLE_INSN_P (138)"
+ "cpacsuma1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovhla1_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2794))]
+ "CGEN_ENABLE_INSN_P (139)"
+ "cpmovhla1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovhla1_w_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2794))]
+ "CGEN_ENABLE_INSN_P (140)"
+ "cpmovhla1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovhua1_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2796))]
+ "CGEN_ENABLE_INSN_P (141)"
+ "cpmovhua1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovhua1_w_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2796))]
+ "CGEN_ENABLE_INSN_P (142)"
+ "cpmovhua1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppackla1_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2798))]
+ "CGEN_ENABLE_INSN_P (143)"
+ "cppackla1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppackla1_w_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2798))]
+ "CGEN_ENABLE_INSN_P (144)"
+ "cppackla1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppackua1_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2800))]
+ "CGEN_ENABLE_INSN_P (145)"
+ "cppackua1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppackua1_w_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2800))]
+ "CGEN_ENABLE_INSN_P (146)"
+ "cppackua1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppackla1_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2802))]
+ "CGEN_ENABLE_INSN_P (147)"
+ "cppackla1.h\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppackla1_h_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2802))]
+ "CGEN_ENABLE_INSN_P (148)"
+ "cppackla1.h\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppackua1_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2804))]
+ "CGEN_ENABLE_INSN_P (149)"
+ "cppackua1.h\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppackua1_h_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2804))]
+ "CGEN_ENABLE_INSN_P (150)"
+ "cppackua1.h\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppacka1_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2806))]
+ "CGEN_ENABLE_INSN_P (151)"
+ "cppacka1.b\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppacka1_b_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2806))]
+ "CGEN_ENABLE_INSN_P (152)"
+ "cppacka1.b\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppacka1u_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2808))]
+ "CGEN_ENABLE_INSN_P (153)"
+ "cppacka1u.b\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppacka1u_b_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2808))]
+ "CGEN_ENABLE_INSN_P (154)"
+ "cppacka1u.b\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovlla1_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2810))]
+ "CGEN_ENABLE_INSN_P (155)"
+ "cpmovlla1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovlla1_w_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2810))]
+ "CGEN_ENABLE_INSN_P (156)"
+ "cpmovlla1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovlua1_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2812))]
+ "CGEN_ENABLE_INSN_P (157)"
+ "cpmovlua1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovlua1_w_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2812))]
+ "CGEN_ENABLE_INSN_P (158)"
+ "cpmovlua1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovula1_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2814))]
+ "CGEN_ENABLE_INSN_P (159)"
+ "cpmovula1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovula1_w_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2814))]
+ "CGEN_ENABLE_INSN_P (160)"
+ "cpmovula1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovuua1_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2816))]
+ "CGEN_ENABLE_INSN_P (161)"
+ "cpmovuua1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovuua1_w_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2816))]
+ "CGEN_ENABLE_INSN_P (162)"
+ "cpmovuua1.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovla1_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2818))]
+ "CGEN_ENABLE_INSN_P (163)"
+ "cpmovla1.h\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovla1_h_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2818))]
+ "CGEN_ENABLE_INSN_P (164)"
+ "cpmovla1.h\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovua1_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2820))]
+ "CGEN_ENABLE_INSN_P (165)"
+ "cpmovua1.h\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovua1_h_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2820))]
+ "CGEN_ENABLE_INSN_P (166)"
+ "cpmovua1.h\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmova1_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2822))]
+ "CGEN_ENABLE_INSN_P (167)"
+ "cpmova1.b\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmova1_b_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 2822))]
+ "CGEN_ENABLE_INSN_P (168)"
+ "cpmova1.b\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsetla1_w_C3"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2824))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2825))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2826))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2827))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2828))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2829))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2830))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2831))]
+ "CGEN_ENABLE_INSN_P (169)"
+ "cpsetla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsetla1_w_P1"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2824))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2825))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2826))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2827))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2828))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2829))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2830))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2831))]
+ "CGEN_ENABLE_INSN_P (170)"
+ "cpsetla1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsetua1_w_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2832))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2833))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2834))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2835))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2836))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2837))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2838))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2839))]
+ "CGEN_ENABLE_INSN_P (171)"
+ "cpsetua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsetua1_w_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2832))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2833))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2834))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2835))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2836))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2837))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2838))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2839))]
+ "CGEN_ENABLE_INSN_P (172)"
+ "cpsetua1.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpseta1_h_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2840))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2841))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2842))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2843))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2844))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2845))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2846))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2847))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2848))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2849))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2850))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2851))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2852))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2853))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2854))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2855))]
+ "CGEN_ENABLE_INSN_P (173)"
+ "cpseta1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpseta1_h_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2840))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2841))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2842))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2843))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2844))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2845))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2846))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2847))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2848))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2849))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2850))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2851))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2852))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2853))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2854))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2855))]
+ "CGEN_ENABLE_INSN_P (174)"
+ "cpseta1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsadla1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2856))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2857))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2858))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2859))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2860))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2861))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2862))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2863))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2864))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2865))]
+ "CGEN_ENABLE_INSN_P (175)"
+ "cpsadla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsadla1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2856))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2857))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2858))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2859))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2860))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2861))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2862))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2863))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2864))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2865))]
+ "CGEN_ENABLE_INSN_P (176)"
+ "cpsadla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsadua1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2866))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2867))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2868))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2869))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2870))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2871))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2872))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2873))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2874))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2875))]
+ "CGEN_ENABLE_INSN_P (177)"
+ "cpsadua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsadua1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2866))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2867))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2868))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2869))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2870))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2871))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2872))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2873))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2874))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2875))]
+ "CGEN_ENABLE_INSN_P (178)"
+ "cpsadua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsada1_b_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2876))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2877))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2878))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2879))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2880))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2881))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2882))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2883))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2884))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2885))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2886))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2887))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2888))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2889))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2890))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2891))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2892))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2893))]
+ "CGEN_ENABLE_INSN_P (179)"
+ "cpsada1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsada1_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2876))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2877))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2878))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2879))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2880))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2881))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2882))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2883))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2884))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2885))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2886))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2887))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2888))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2889))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2890))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2891))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2892))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2893))]
+ "CGEN_ENABLE_INSN_P (180)"
+ "cpsada1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsada1u_b_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2894))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2895))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2896))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2897))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2898))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2899))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2900))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2901))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2902))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2903))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2904))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2905))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2906))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2907))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2908))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2909))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2910))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2911))]
+ "CGEN_ENABLE_INSN_P (181)"
+ "cpsada1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsada1u_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2894))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2895))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2896))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2897))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2898))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2899))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2900))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2901))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2902))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2903))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2904))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2905))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2906))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2907))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2908))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2909))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2910))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2911))]
+ "CGEN_ENABLE_INSN_P (182)"
+ "cpsada1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsla1_h_C3"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2912))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2913))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2914))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2915))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2916))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2917))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2918))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2919))]
+ "CGEN_ENABLE_INSN_P (183)"
+ "cpabsla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsla1_h_P1"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2912))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2913))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2914))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2915))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2916))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2917))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2918))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2919))]
+ "CGEN_ENABLE_INSN_P (184)"
+ "cpabsla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsua1_h_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2920))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2921))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2922))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2923))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2924))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2925))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2926))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2927))]
+ "CGEN_ENABLE_INSN_P (185)"
+ "cpabsua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsua1_h_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2920))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2921))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2922))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2923))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2924))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2925))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2926))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2927))]
+ "CGEN_ENABLE_INSN_P (186)"
+ "cpabsua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsa1_b_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2928))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2929))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2930))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2931))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2932))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2933))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2934))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2935))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2936))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2937))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2938))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2939))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2940))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2941))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2942))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2943))]
+ "CGEN_ENABLE_INSN_P (187)"
+ "cpabsa1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsa1_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2928))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2929))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2930))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2931))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2932))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2933))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2934))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2935))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2936))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2937))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2938))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2939))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2940))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2941))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2942))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2943))]
+ "CGEN_ENABLE_INSN_P (188)"
+ "cpabsa1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsa1u_b_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2944))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2945))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2946))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2947))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2948))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2949))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2950))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2951))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2952))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2953))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2954))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2955))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2956))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2957))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2958))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2959))]
+ "CGEN_ENABLE_INSN_P (189)"
+ "cpabsa1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsa1u_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2944))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2945))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2946))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2947))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2948))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2949))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2950))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2951))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2952))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2953))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2954))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2955))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2956))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2957))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2958))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2959))]
+ "CGEN_ENABLE_INSN_P (190)"
+ "cpabsa1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubacla1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2960))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2961))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2962))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2963))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2964))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2965))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2966))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2967))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2968))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2969))]
+ "CGEN_ENABLE_INSN_P (191)"
+ "cpsubacla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubacla1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2960))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2961))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2962))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2963))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2964))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2965))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2966))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2967))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2968))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2969))]
+ "CGEN_ENABLE_INSN_P (192)"
+ "cpsubacla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubacua1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2970))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2971))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2972))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2973))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2974))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2975))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2976))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2977))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2978))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2979))]
+ "CGEN_ENABLE_INSN_P (193)"
+ "cpsubacua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubacua1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2970))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2971))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2972))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2973))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2974))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2975))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2976))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2977))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2978))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2979))]
+ "CGEN_ENABLE_INSN_P (194)"
+ "cpsubacua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubaca1_b_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2980))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2981))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2982))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2983))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2984))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2985))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2986))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2987))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2988))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2989))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2990))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2991))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2992))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2993))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2994))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2995))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2996))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2997))]
+ "CGEN_ENABLE_INSN_P (195)"
+ "cpsubaca1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubaca1_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2980))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2981))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2982))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2983))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2984))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2985))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2986))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2987))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2988))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2989))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2990))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2991))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2992))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2993))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2994))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2995))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2996))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2997))]
+ "CGEN_ENABLE_INSN_P (196)"
+ "cpsubaca1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubaca1u_b_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2998))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2999))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3000))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3001))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3002))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3003))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3004))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3005))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3006))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3007))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3008))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3009))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3010))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3011))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3012))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3013))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3014))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3015))]
+ "CGEN_ENABLE_INSN_P (197)"
+ "cpsubaca1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubaca1u_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2998))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2999))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3000))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3001))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3002))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3003))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3004))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3005))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3006))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3007))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3008))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3009))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3010))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3011))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3012))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3013))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3014))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3015))]
+ "CGEN_ENABLE_INSN_P (198)"
+ "cpsubaca1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubla1_h_C3"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3016))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3017))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3018))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3019))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3020))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3021))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3022))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3023))]
+ "CGEN_ENABLE_INSN_P (199)"
+ "cpsubla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubla1_h_P1"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3016))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3017))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3018))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3019))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3020))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3021))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3022))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3023))]
+ "CGEN_ENABLE_INSN_P (200)"
+ "cpsubla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubua1_h_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3024))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3025))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3026))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3027))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3028))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3029))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3030))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3031))]
+ "CGEN_ENABLE_INSN_P (201)"
+ "cpsubua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubua1_h_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3024))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3025))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3026))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3027))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3028))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3029))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3030))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3031))]
+ "CGEN_ENABLE_INSN_P (202)"
+ "cpsubua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsuba1_b_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3032))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3033))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3034))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3035))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3036))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3037))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3038))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3039))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3040))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3041))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3042))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3043))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3044))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3045))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3046))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3047))]
+ "CGEN_ENABLE_INSN_P (203)"
+ "cpsuba1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsuba1_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3032))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3033))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3034))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3035))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3036))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3037))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3038))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3039))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3040))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3041))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3042))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3043))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3044))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3045))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3046))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3047))]
+ "CGEN_ENABLE_INSN_P (204)"
+ "cpsuba1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsuba1u_b_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3048))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3049))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3050))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3051))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3052))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3053))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3054))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3055))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3056))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3057))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3058))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3059))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3060))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3061))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3062))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3063))]
+ "CGEN_ENABLE_INSN_P (205)"
+ "cpsuba1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsuba1u_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3048))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3049))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3050))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3051))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3052))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3053))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3054))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3055))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3056))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3057))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3058))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3059))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3060))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3061))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3062))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3063))]
+ "CGEN_ENABLE_INSN_P (206)"
+ "cpsuba1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddacla1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3064))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3065))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3066))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3067))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3068))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3069))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3070))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3071))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3072))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3073))]
+ "CGEN_ENABLE_INSN_P (207)"
+ "cpaddacla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddacla1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3064))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3065))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3066))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3067))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3068))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3069))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3070))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3071))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3072))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3073))]
+ "CGEN_ENABLE_INSN_P (208)"
+ "cpaddacla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddacua1_h_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3074))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3075))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3076))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3077))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3078))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3079))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3080))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3081))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3082))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3083))]
+ "CGEN_ENABLE_INSN_P (209)"
+ "cpaddacua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddacua1_h_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3074))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3075))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3076))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3077))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3078))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3079))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3080))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3081))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3082))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3083))]
+ "CGEN_ENABLE_INSN_P (210)"
+ "cpaddacua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddaca1_b_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3084))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3085))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3086))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3087))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3088))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3089))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3090))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3091))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3092))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3093))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3094))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3095))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3096))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3097))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3098))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3099))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3100))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3101))]
+ "CGEN_ENABLE_INSN_P (211)"
+ "cpaddaca1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddaca1_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3084))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3085))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3086))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3087))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3088))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3089))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3090))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3091))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3092))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3093))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3094))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3095))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3096))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3097))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3098))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3099))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3100))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3101))]
+ "CGEN_ENABLE_INSN_P (212)"
+ "cpaddaca1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddaca1u_b_C3"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3102))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3103))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3104))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3105))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3106))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3107))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3108))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3109))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3110))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3111))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3112))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3113))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3114))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3115))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3116))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3117))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3118))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3119))]
+ "CGEN_ENABLE_INSN_P (213)"
+ "cpaddaca1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddaca1u_b_P1"
+ [(set (reg:SI 87)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3102))
+ (set (reg:SI 113)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3103))
+ (set (reg:SI 111)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3104))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3105))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3106))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3107))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3108))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3109))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3110))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3111))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3112))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3113))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3114))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3115))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3116))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3117))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3118))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3119))]
+ "CGEN_ENABLE_INSN_P (214)"
+ "cpaddaca1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddla1_h_C3"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3120))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3121))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3122))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3123))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3124))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3125))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3126))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3127))]
+ "CGEN_ENABLE_INSN_P (215)"
+ "cpaddla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddla1_h_P1"
+ [(set (reg:SI 107)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3120))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3121))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3122))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3123))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3124))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3125))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3126))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3127))]
+ "CGEN_ENABLE_INSN_P (216)"
+ "cpaddla1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddua1_h_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3128))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3129))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3130))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3131))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3132))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3133))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3134))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3135))]
+ "CGEN_ENABLE_INSN_P (217)"
+ "cpaddua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddua1_h_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3128))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3129))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3130))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3131))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3132))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3133))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3134))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3135))]
+ "CGEN_ENABLE_INSN_P (218)"
+ "cpaddua1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpadda1_b_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3136))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3137))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3138))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3139))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3140))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3141))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3142))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3143))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3144))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3145))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3146))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3147))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3148))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3149))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3150))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3151))]
+ "CGEN_ENABLE_INSN_P (219)"
+ "cpadda1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpadda1_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3136))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3137))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3138))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3139))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3140))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3141))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3142))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3143))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3144))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3145))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3146))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3147))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3148))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3149))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3150))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3151))]
+ "CGEN_ENABLE_INSN_P (220)"
+ "cpadda1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpadda1u_b_C3"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3152))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3153))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3154))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3155))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3156))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3157))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3158))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3159))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3160))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3161))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3162))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3163))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3164))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3165))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3166))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3167))]
+ "CGEN_ENABLE_INSN_P (221)"
+ "cpadda1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpadda1u_b_P1"
+ [(set (reg:SI 111)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3152))
+ (set (reg:SI 118)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3153))
+ (set (reg:SI 110)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3154))
+ (set (reg:SI 119)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3155))
+ (set (reg:SI 109)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3156))
+ (set (reg:SI 120)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3157))
+ (set (reg:SI 108)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3158))
+ (set (reg:SI 121)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3159))
+ (set (reg:SI 107)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3160))
+ (set (reg:SI 114)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3161))
+ (set (reg:SI 106)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3162))
+ (set (reg:SI 115)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3163))
+ (set (reg:SI 105)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3164))
+ (set (reg:SI 116)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3165))
+ (set (reg:SI 104)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3166))
+ (set (reg:SI 117)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3167))]
+ "CGEN_ENABLE_INSN_P (222)"
+ "cpadda1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovi_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
+ ] 3180))]
+ "CGEN_ENABLE_INSN_P (223)"
+ "cpmovi.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovi_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
+ ] 3180))]
+ "CGEN_ENABLE_INSN_P (224)"
+ "cpmovi.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_c1nop_P1"
+ [(unspec_volatile [
+ (const_int 0)
+ ] 1482)]
+ "CGEN_ENABLE_INSN_P (225)"
+ "c1nop"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdmovi_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
+ ] 3168))]
+ "CGEN_ENABLE_INSN_P (226)"
+ "cdmovi\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdmovi_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
+ ] 3168))]
+ "CGEN_ENABLE_INSN_P (227)"
+ "cdmovi\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdmoviu_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_uint_8a1_immediate" "")
+ ] 3170))]
+ "CGEN_ENABLE_INSN_P (228)"
+ "cdmoviu\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdmoviu_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_uint_16a1_immediate" "")
+ ] 3170))]
+ "CGEN_ENABLE_INSN_P (229)"
+ "cdmoviu\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovi_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
+ ] 3172))]
+ "CGEN_ENABLE_INSN_P (230)"
+ "cpmovi.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovi_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
+ ] 3172))]
+ "CGEN_ENABLE_INSN_P (231)"
+ "cpmovi.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmoviu_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_uint_8a1_immediate" "")
+ ] 3174))]
+ "CGEN_ENABLE_INSN_P (232)"
+ "cpmoviu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmoviu_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_uint_16a1_immediate" "")
+ ] 3174))]
+ "CGEN_ENABLE_INSN_P (233)"
+ "cpmoviu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovi_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
+ ] 3176))]
+ "CGEN_ENABLE_INSN_P (234)"
+ "cpmovi.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovi_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
+ ] 3176))]
+ "CGEN_ENABLE_INSN_P (235)"
+ "cpmovi.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdclipi3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
+ ] 3182))]
+ "CGEN_ENABLE_INSN_P (236)"
+ "cdclipi3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdclipi3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
+ ] 3182))]
+ "CGEN_ENABLE_INSN_P (237)"
+ "cdclipi3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdclipiu3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
+ ] 3184))]
+ "CGEN_ENABLE_INSN_P (238)"
+ "cdclipiu3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdclipiu3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
+ ] 3184))]
+ "CGEN_ENABLE_INSN_P (239)"
+ "cdclipiu3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpclipi3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3186))]
+ "CGEN_ENABLE_INSN_P (240)"
+ "cpclipi3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpclipi3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3186))]
+ "CGEN_ENABLE_INSN_P (241)"
+ "cpclipi3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpclipiu3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3188))]
+ "CGEN_ENABLE_INSN_P (242)"
+ "cpclipiu3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpclipiu3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3188))]
+ "CGEN_ENABLE_INSN_P (243)"
+ "cpclipiu3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslai3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3190))]
+ "CGEN_ENABLE_INSN_P (244)"
+ "cpslai3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslai3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3190))]
+ "CGEN_ENABLE_INSN_P (245)"
+ "cpslai3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslai3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
+ ] 3192))]
+ "CGEN_ENABLE_INSN_P (246)"
+ "cpslai3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslai3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
+ ] 3192))]
+ "CGEN_ENABLE_INSN_P (247)"
+ "cpslai3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdslli3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
+ ] 3194))]
+ "CGEN_ENABLE_INSN_P (248)"
+ "cdslli3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdslli3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
+ ] 3194))]
+ "CGEN_ENABLE_INSN_P (249)"
+ "cdslli3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslli3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3196))]
+ "CGEN_ENABLE_INSN_P (250)"
+ "cpslli3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslli3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3196))]
+ "CGEN_ENABLE_INSN_P (251)"
+ "cpslli3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslli3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
+ ] 3198))]
+ "CGEN_ENABLE_INSN_P (252)"
+ "cpslli3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslli3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
+ ] 3198))]
+ "CGEN_ENABLE_INSN_P (253)"
+ "cpslli3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslli3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
+ ] 3200))]
+ "CGEN_ENABLE_INSN_P (254)"
+ "cpslli3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslli3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
+ ] 3200))]
+ "CGEN_ENABLE_INSN_P (255)"
+ "cpslli3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdsrai3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
+ ] 3202))]
+ "CGEN_ENABLE_INSN_P (256)"
+ "cdsrai3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdsrai3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
+ ] 3202))]
+ "CGEN_ENABLE_INSN_P (257)"
+ "cdsrai3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrai3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3204))]
+ "CGEN_ENABLE_INSN_P (258)"
+ "cpsrai3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrai3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3204))]
+ "CGEN_ENABLE_INSN_P (259)"
+ "cpsrai3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrai3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
+ ] 3206))]
+ "CGEN_ENABLE_INSN_P (260)"
+ "cpsrai3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrai3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
+ ] 3206))]
+ "CGEN_ENABLE_INSN_P (261)"
+ "cpsrai3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrai3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
+ ] 3208))]
+ "CGEN_ENABLE_INSN_P (262)"
+ "cpsrai3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrai3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
+ ] 3208))]
+ "CGEN_ENABLE_INSN_P (263)"
+ "cpsrai3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdsrli3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
+ ] 3210))]
+ "CGEN_ENABLE_INSN_P (264)"
+ "cdsrli3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdsrli3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
+ ] 3210))]
+ "CGEN_ENABLE_INSN_P (265)"
+ "cdsrli3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrli3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3212))]
+ "CGEN_ENABLE_INSN_P (266)"
+ "cpsrli3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrli3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3212))]
+ "CGEN_ENABLE_INSN_P (267)"
+ "cpsrli3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrli3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
+ ] 3214))]
+ "CGEN_ENABLE_INSN_P (268)"
+ "cpsrli3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrli3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
+ ] 3214))]
+ "CGEN_ENABLE_INSN_P (269)"
+ "cpsrli3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrli3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
+ ] 3216))]
+ "CGEN_ENABLE_INSN_P (270)"
+ "cpsrli3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrli3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
+ ] 3216))]
+ "CGEN_ENABLE_INSN_P (271)"
+ "cpsrli3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsla3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3460))]
+ "CGEN_ENABLE_INSN_P (272)"
+ "cpsla3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsla3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3460))]
+ "CGEN_ENABLE_INSN_P (273)"
+ "cpsla3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsla3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3462))]
+ "CGEN_ENABLE_INSN_P (274)"
+ "cpsla3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsla3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3462))]
+ "CGEN_ENABLE_INSN_P (275)"
+ "cpsla3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdsll3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3464))]
+ "CGEN_ENABLE_INSN_P (276)"
+ "cdsll3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdsll3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3464))]
+ "CGEN_ENABLE_INSN_P (277)"
+ "cdsll3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssll3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3466))]
+ "CGEN_ENABLE_INSN_P (278)"
+ "cpssll3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssll3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3466))]
+ "CGEN_ENABLE_INSN_P (279)"
+ "cpssll3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsll3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3468))]
+ "CGEN_ENABLE_INSN_P (280)"
+ "cpsll3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsll3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3468))]
+ "CGEN_ENABLE_INSN_P (281)"
+ "cpsll3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssll3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3470))]
+ "CGEN_ENABLE_INSN_P (282)"
+ "cpssll3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssll3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3470))]
+ "CGEN_ENABLE_INSN_P (283)"
+ "cpssll3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsll3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3472))]
+ "CGEN_ENABLE_INSN_P (284)"
+ "cpsll3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsll3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3472))]
+ "CGEN_ENABLE_INSN_P (285)"
+ "cpsll3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssll3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3474))]
+ "CGEN_ENABLE_INSN_P (286)"
+ "cpssll3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssll3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3474))]
+ "CGEN_ENABLE_INSN_P (287)"
+ "cpssll3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsll3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3476))]
+ "CGEN_ENABLE_INSN_P (288)"
+ "cpsll3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsll3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3476))]
+ "CGEN_ENABLE_INSN_P (289)"
+ "cpsll3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdsra3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3478))]
+ "CGEN_ENABLE_INSN_P (290)"
+ "cdsra3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdsra3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3478))]
+ "CGEN_ENABLE_INSN_P (291)"
+ "cdsra3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssra3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3480))]
+ "CGEN_ENABLE_INSN_P (292)"
+ "cpssra3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssra3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3480))]
+ "CGEN_ENABLE_INSN_P (293)"
+ "cpssra3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsra3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3482))]
+ "CGEN_ENABLE_INSN_P (294)"
+ "cpsra3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsra3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3482))]
+ "CGEN_ENABLE_INSN_P (295)"
+ "cpsra3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssra3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3484))]
+ "CGEN_ENABLE_INSN_P (296)"
+ "cpssra3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssra3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3484))]
+ "CGEN_ENABLE_INSN_P (297)"
+ "cpssra3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsra3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3486))]
+ "CGEN_ENABLE_INSN_P (298)"
+ "cpsra3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsra3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3486))]
+ "CGEN_ENABLE_INSN_P (299)"
+ "cpsra3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssra3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3488))]
+ "CGEN_ENABLE_INSN_P (300)"
+ "cpssra3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssra3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3488))]
+ "CGEN_ENABLE_INSN_P (301)"
+ "cpssra3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsra3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3490))]
+ "CGEN_ENABLE_INSN_P (302)"
+ "cpsra3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsra3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3490))]
+ "CGEN_ENABLE_INSN_P (303)"
+ "cpsra3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdsrl3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3492))]
+ "CGEN_ENABLE_INSN_P (304)"
+ "cdsrl3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdsrl3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3492))]
+ "CGEN_ENABLE_INSN_P (305)"
+ "cdsrl3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssrl3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3494))]
+ "CGEN_ENABLE_INSN_P (306)"
+ "cpssrl3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssrl3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3494))]
+ "CGEN_ENABLE_INSN_P (307)"
+ "cpssrl3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrl3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3496))]
+ "CGEN_ENABLE_INSN_P (308)"
+ "cpsrl3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrl3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3496))]
+ "CGEN_ENABLE_INSN_P (309)"
+ "cpsrl3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssrl3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3498))]
+ "CGEN_ENABLE_INSN_P (310)"
+ "cpssrl3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssrl3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3498))]
+ "CGEN_ENABLE_INSN_P (311)"
+ "cpssrl3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrl3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3500))]
+ "CGEN_ENABLE_INSN_P (312)"
+ "cpsrl3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrl3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3500))]
+ "CGEN_ENABLE_INSN_P (313)"
+ "cpsrl3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssrl3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3502))]
+ "CGEN_ENABLE_INSN_P (314)"
+ "cpssrl3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssrl3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3502))]
+ "CGEN_ENABLE_INSN_P (315)"
+ "cpssrl3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrl3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3504))]
+ "CGEN_ENABLE_INSN_P (316)"
+ "cpsrl3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrl3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3504))]
+ "CGEN_ENABLE_INSN_P (317)"
+ "cpsrl3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmin3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3390))]
+ "CGEN_ENABLE_INSN_P (318)"
+ "cpmin3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmin3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3390))]
+ "CGEN_ENABLE_INSN_P (319)"
+ "cpmin3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpminu3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3392))]
+ "CGEN_ENABLE_INSN_P (320)"
+ "cpminu3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpminu3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3392))]
+ "CGEN_ENABLE_INSN_P (321)"
+ "cpminu3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmin3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3394))]
+ "CGEN_ENABLE_INSN_P (322)"
+ "cpmin3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmin3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3394))]
+ "CGEN_ENABLE_INSN_P (323)"
+ "cpmin3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmin3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3396))]
+ "CGEN_ENABLE_INSN_P (324)"
+ "cpmin3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmin3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3396))]
+ "CGEN_ENABLE_INSN_P (325)"
+ "cpmin3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpminu3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3398))]
+ "CGEN_ENABLE_INSN_P (326)"
+ "cpminu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpminu3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3398))]
+ "CGEN_ENABLE_INSN_P (327)"
+ "cpminu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmax3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3400))]
+ "CGEN_ENABLE_INSN_P (328)"
+ "cpmax3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmax3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3400))]
+ "CGEN_ENABLE_INSN_P (329)"
+ "cpmax3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmaxu3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3402))]
+ "CGEN_ENABLE_INSN_P (330)"
+ "cpmaxu3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmaxu3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3402))]
+ "CGEN_ENABLE_INSN_P (331)"
+ "cpmaxu3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmax3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3404))]
+ "CGEN_ENABLE_INSN_P (332)"
+ "cpmax3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmax3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3404))]
+ "CGEN_ENABLE_INSN_P (333)"
+ "cpmax3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmax3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3406))]
+ "CGEN_ENABLE_INSN_P (334)"
+ "cpmax3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmax3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3406))]
+ "CGEN_ENABLE_INSN_P (335)"
+ "cpmax3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmaxu3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3408))]
+ "CGEN_ENABLE_INSN_P (336)"
+ "cpmaxu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmaxu3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3408))]
+ "CGEN_ENABLE_INSN_P (337)"
+ "cpmaxu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppack_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3506))]
+ "CGEN_ENABLE_INSN_P (338)"
+ "cppack.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppack_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3506))]
+ "CGEN_ENABLE_INSN_P (339)"
+ "cppack.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppack_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3508))]
+ "CGEN_ENABLE_INSN_P (340)"
+ "cppack.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppack_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3508))]
+ "CGEN_ENABLE_INSN_P (341)"
+ "cppack.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppacku_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3510))]
+ "CGEN_ENABLE_INSN_P (342)"
+ "cppacku.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppacku_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3510))]
+ "CGEN_ENABLE_INSN_P (343)"
+ "cppacku.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpxor3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3532))]
+ "CGEN_ENABLE_INSN_P (344)"
+ "cpxor3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpxor3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3532))]
+ "CGEN_ENABLE_INSN_P (345)"
+ "cpxor3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpnor3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3534))]
+ "CGEN_ENABLE_INSN_P (346)"
+ "cpnor3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpnor3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3534))]
+ "CGEN_ENABLE_INSN_P (347)"
+ "cpnor3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpor3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3536))]
+ "CGEN_ENABLE_INSN_P (348)"
+ "cpor3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpor3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3536))]
+ "CGEN_ENABLE_INSN_P (349)"
+ "cpor3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpand3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3538))]
+ "CGEN_ENABLE_INSN_P (350)"
+ "cpand3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpand3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3538))]
+ "CGEN_ENABLE_INSN_P (351)"
+ "cpand3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabs3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3410))]
+ "CGEN_ENABLE_INSN_P (352)"
+ "cpabs3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabs3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3410))]
+ "CGEN_ENABLE_INSN_P (353)"
+ "cpabs3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabs3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3412))]
+ "CGEN_ENABLE_INSN_P (354)"
+ "cpabs3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabs3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3412))]
+ "CGEN_ENABLE_INSN_P (355)"
+ "cpabs3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsu3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3414))]
+ "CGEN_ENABLE_INSN_P (356)"
+ "cpabsu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsu3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3414))]
+ "CGEN_ENABLE_INSN_P (357)"
+ "cpabsu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddsr3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3416))]
+ "CGEN_ENABLE_INSN_P (358)"
+ "cpaddsr3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddsr3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3416))]
+ "CGEN_ENABLE_INSN_P (359)"
+ "cpaddsr3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddsr3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3418))]
+ "CGEN_ENABLE_INSN_P (360)"
+ "cpaddsr3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddsr3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3418))]
+ "CGEN_ENABLE_INSN_P (361)"
+ "cpaddsr3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddsr3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3420))]
+ "CGEN_ENABLE_INSN_P (362)"
+ "cpaddsr3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddsr3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3420))]
+ "CGEN_ENABLE_INSN_P (363)"
+ "cpaddsr3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddsru3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3422))]
+ "CGEN_ENABLE_INSN_P (364)"
+ "cpaddsru3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddsru3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3422))]
+ "CGEN_ENABLE_INSN_P (365)"
+ "cpaddsru3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpave3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3424))]
+ "CGEN_ENABLE_INSN_P (366)"
+ "cpave3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpave3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3424))]
+ "CGEN_ENABLE_INSN_P (367)"
+ "cpave3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpave3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3426))]
+ "CGEN_ENABLE_INSN_P (368)"
+ "cpave3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpave3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3426))]
+ "CGEN_ENABLE_INSN_P (369)"
+ "cpave3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpave3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3428))]
+ "CGEN_ENABLE_INSN_P (370)"
+ "cpave3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpave3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3428))]
+ "CGEN_ENABLE_INSN_P (371)"
+ "cpave3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaveu3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3430))]
+ "CGEN_ENABLE_INSN_P (372)"
+ "cpaveu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaveu3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3430))]
+ "CGEN_ENABLE_INSN_P (373)"
+ "cpaveu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextlsub3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3432))]
+ "CGEN_ENABLE_INSN_P (374)"
+ "cpextlsub3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextlsub3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3432))]
+ "CGEN_ENABLE_INSN_P (375)"
+ "cpextlsub3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextlsubu3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3434))]
+ "CGEN_ENABLE_INSN_P (376)"
+ "cpextlsubu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextlsubu3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3434))]
+ "CGEN_ENABLE_INSN_P (377)"
+ "cpextlsubu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextusub3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3436))]
+ "CGEN_ENABLE_INSN_P (378)"
+ "cpextusub3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextusub3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3436))]
+ "CGEN_ENABLE_INSN_P (379)"
+ "cpextusub3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextusubu3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3438))]
+ "CGEN_ENABLE_INSN_P (380)"
+ "cpextusubu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextusubu3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3438))]
+ "CGEN_ENABLE_INSN_P (381)"
+ "cpextusubu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextladd3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3440))]
+ "CGEN_ENABLE_INSN_P (382)"
+ "cpextladd3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextladd3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3440))]
+ "CGEN_ENABLE_INSN_P (383)"
+ "cpextladd3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextladdu3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3442))]
+ "CGEN_ENABLE_INSN_P (384)"
+ "cpextladdu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextladdu3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3442))]
+ "CGEN_ENABLE_INSN_P (385)"
+ "cpextladdu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextuadd3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3444))]
+ "CGEN_ENABLE_INSN_P (386)"
+ "cpextuadd3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextuadd3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3444))]
+ "CGEN_ENABLE_INSN_P (387)"
+ "cpextuadd3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextuaddu3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3446))]
+ "CGEN_ENABLE_INSN_P (388)"
+ "cpextuaddu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextuaddu3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3446))]
+ "CGEN_ENABLE_INSN_P (389)"
+ "cpextuaddu3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssub3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3448))
+ (set (reg:SI 84)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3450))
+ (set (reg:SI 122)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3451))]
+ "CGEN_ENABLE_INSN_P (390)"
+ "cpssub3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssub3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3448))
+ (set (reg:SI 84)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3450))
+ (set (reg:SI 122)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3451))]
+ "CGEN_ENABLE_INSN_P (391)"
+ "cpssub3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssub3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3452))
+ (set (reg:SI 84)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3454))
+ (set (reg:SI 122)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3455))]
+ "CGEN_ENABLE_INSN_P (392)"
+ "cpssub3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpssub3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3452))
+ (set (reg:SI 84)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3454))
+ (set (reg:SI 122)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3455))]
+ "CGEN_ENABLE_INSN_P (393)"
+ "cpssub3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsadd3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3456))]
+ "CGEN_ENABLE_INSN_P (394)"
+ "cpsadd3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsadd3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3456))]
+ "CGEN_ENABLE_INSN_P (395)"
+ "cpsadd3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsadd3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3458))]
+ "CGEN_ENABLE_INSN_P (396)"
+ "cpsadd3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsadd3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3458))]
+ "CGEN_ENABLE_INSN_P (397)"
+ "cpsadd3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdsub3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3540))]
+ "CGEN_ENABLE_INSN_P (398)"
+ "cdsub3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdsub3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3540))]
+ "CGEN_ENABLE_INSN_P (399)"
+ "cdsub3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsub3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3542))]
+ "CGEN_ENABLE_INSN_P (400)"
+ "cpsub3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsub3_w_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3542))]
+ "CGEN_ENABLE_INSN_P (401)"
+ "cpsub3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsub3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3544))]
+ "CGEN_ENABLE_INSN_P (402)"
+ "cpsub3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsub3_h_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3544))]
+ "CGEN_ENABLE_INSN_P (403)"
+ "cpsub3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsub3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3546))]
+ "CGEN_ENABLE_INSN_P (404)"
+ "cpsub3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsub3_b_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3546))]
+ "CGEN_ENABLE_INSN_P (405)"
+ "cpsub3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdadd3_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3548))]
+ "CGEN_ENABLE_INSN_P (406)"
+ "cdadd3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdadd3_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3548))]
+ "CGEN_ENABLE_INSN_P (407)"
+ "cdadd3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpge_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3218))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3219))]
+ "CGEN_ENABLE_INSN_P (408)"
+ "cpocmpge.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpge_w_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3218)]
+ "CGEN_ENABLE_INSN_P (409)"
+ "cpocmpge.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgeu_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3220))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3221))]
+ "CGEN_ENABLE_INSN_P (410)"
+ "cpocmpgeu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgeu_w_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3220)]
+ "CGEN_ENABLE_INSN_P (411)"
+ "cpocmpgeu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpge_h_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3222))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3223))]
+ "CGEN_ENABLE_INSN_P (412)"
+ "cpocmpge.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpge_h_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3222)]
+ "CGEN_ENABLE_INSN_P (413)"
+ "cpocmpge.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpge_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3224))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3225))]
+ "CGEN_ENABLE_INSN_P (414)"
+ "cpocmpge.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpge_b_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3224)]
+ "CGEN_ENABLE_INSN_P (415)"
+ "cpocmpge.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgeu_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3226))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3227))]
+ "CGEN_ENABLE_INSN_P (416)"
+ "cpocmpgeu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgeu_b_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3226)]
+ "CGEN_ENABLE_INSN_P (417)"
+ "cpocmpgeu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgt_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3228))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3229))]
+ "CGEN_ENABLE_INSN_P (418)"
+ "cpocmpgt.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgt_w_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3228)]
+ "CGEN_ENABLE_INSN_P (419)"
+ "cpocmpgt.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgtu_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3230))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3231))]
+ "CGEN_ENABLE_INSN_P (420)"
+ "cpocmpgtu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgtu_w_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3230)]
+ "CGEN_ENABLE_INSN_P (421)"
+ "cpocmpgtu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgt_h_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3232))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3233))]
+ "CGEN_ENABLE_INSN_P (422)"
+ "cpocmpgt.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgt_h_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3232)]
+ "CGEN_ENABLE_INSN_P (423)"
+ "cpocmpgt.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgt_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3234))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3235))]
+ "CGEN_ENABLE_INSN_P (424)"
+ "cpocmpgt.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgt_b_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3234)]
+ "CGEN_ENABLE_INSN_P (425)"
+ "cpocmpgt.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgtu_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3236))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3237))]
+ "CGEN_ENABLE_INSN_P (426)"
+ "cpocmpgtu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpgtu_b_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3236)]
+ "CGEN_ENABLE_INSN_P (427)"
+ "cpocmpgtu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpne_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3238))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3239))]
+ "CGEN_ENABLE_INSN_P (428)"
+ "cpocmpne.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpne_w_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3238)]
+ "CGEN_ENABLE_INSN_P (429)"
+ "cpocmpne.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpne_h_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3240))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3241))]
+ "CGEN_ENABLE_INSN_P (430)"
+ "cpocmpne.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpne_h_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3240)]
+ "CGEN_ENABLE_INSN_P (431)"
+ "cpocmpne.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpne_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3242))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3243))]
+ "CGEN_ENABLE_INSN_P (432)"
+ "cpocmpne.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpne_b_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3242)]
+ "CGEN_ENABLE_INSN_P (433)"
+ "cpocmpne.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpeq_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3244))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3245))]
+ "CGEN_ENABLE_INSN_P (434)"
+ "cpocmpeq.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpeq_w_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3244)]
+ "CGEN_ENABLE_INSN_P (435)"
+ "cpocmpeq.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpeq_h_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3246))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3247))]
+ "CGEN_ENABLE_INSN_P (436)"
+ "cpocmpeq.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpeq_h_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3246)]
+ "CGEN_ENABLE_INSN_P (437)"
+ "cpocmpeq.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpeq_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3248))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3249))]
+ "CGEN_ENABLE_INSN_P (438)"
+ "cpocmpeq.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpocmpeq_b_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3248)]
+ "CGEN_ENABLE_INSN_P (439)"
+ "cpocmpeq.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpge_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3250))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3251))]
+ "CGEN_ENABLE_INSN_P (440)"
+ "cpacmpge.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpge_w_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3250)]
+ "CGEN_ENABLE_INSN_P (441)"
+ "cpacmpge.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgeu_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3252))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3253))]
+ "CGEN_ENABLE_INSN_P (442)"
+ "cpacmpgeu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgeu_w_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3252)]
+ "CGEN_ENABLE_INSN_P (443)"
+ "cpacmpgeu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpge_h_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3254))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3255))]
+ "CGEN_ENABLE_INSN_P (444)"
+ "cpacmpge.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpge_h_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3254)]
+ "CGEN_ENABLE_INSN_P (445)"
+ "cpacmpge.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpge_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3256))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3257))]
+ "CGEN_ENABLE_INSN_P (446)"
+ "cpacmpge.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpge_b_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3256)]
+ "CGEN_ENABLE_INSN_P (447)"
+ "cpacmpge.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgeu_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3258))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3259))]
+ "CGEN_ENABLE_INSN_P (448)"
+ "cpacmpgeu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgeu_b_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3258)]
+ "CGEN_ENABLE_INSN_P (449)"
+ "cpacmpgeu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgt_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3260))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3261))]
+ "CGEN_ENABLE_INSN_P (450)"
+ "cpacmpgt.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgt_w_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3260)]
+ "CGEN_ENABLE_INSN_P (451)"
+ "cpacmpgt.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgtu_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3262))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3263))]
+ "CGEN_ENABLE_INSN_P (452)"
+ "cpacmpgtu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgtu_w_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3262)]
+ "CGEN_ENABLE_INSN_P (453)"
+ "cpacmpgtu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgt_h_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3264))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3265))]
+ "CGEN_ENABLE_INSN_P (454)"
+ "cpacmpgt.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgt_h_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3264)]
+ "CGEN_ENABLE_INSN_P (455)"
+ "cpacmpgt.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgt_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3266))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3267))]
+ "CGEN_ENABLE_INSN_P (456)"
+ "cpacmpgt.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgt_b_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3266)]
+ "CGEN_ENABLE_INSN_P (457)"
+ "cpacmpgt.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgtu_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3268))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3269))]
+ "CGEN_ENABLE_INSN_P (458)"
+ "cpacmpgtu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpgtu_b_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3268)]
+ "CGEN_ENABLE_INSN_P (459)"
+ "cpacmpgtu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpne_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3270))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3271))]
+ "CGEN_ENABLE_INSN_P (460)"
+ "cpacmpne.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpne_w_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3270)]
+ "CGEN_ENABLE_INSN_P (461)"
+ "cpacmpne.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpne_h_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3272))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3273))]
+ "CGEN_ENABLE_INSN_P (462)"
+ "cpacmpne.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpne_h_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3272)]
+ "CGEN_ENABLE_INSN_P (463)"
+ "cpacmpne.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpne_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3274))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3275))]
+ "CGEN_ENABLE_INSN_P (464)"
+ "cpacmpne.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpne_b_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3274)]
+ "CGEN_ENABLE_INSN_P (465)"
+ "cpacmpne.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpeq_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3276))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3277))]
+ "CGEN_ENABLE_INSN_P (466)"
+ "cpacmpeq.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpeq_w_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3276)]
+ "CGEN_ENABLE_INSN_P (467)"
+ "cpacmpeq.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpeq_h_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3278))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3279))]
+ "CGEN_ENABLE_INSN_P (468)"
+ "cpacmpeq.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpeq_h_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3278)]
+ "CGEN_ENABLE_INSN_P (469)"
+ "cpacmpeq.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpeq_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3280))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3281))]
+ "CGEN_ENABLE_INSN_P (470)"
+ "cpacmpeq.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacmpeq_b_P0_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3280)]
+ "CGEN_ENABLE_INSN_P (471)"
+ "cpacmpeq.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftbi_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ (match_operand:DI 3 "cgen_h_uint_3a1_immediate" "")
+ ] 3528))]
+ "CGEN_ENABLE_INSN_P (472)"
+ "cpfsftbi\\t%0,%1,%2,%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftbi_P0_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ (match_operand:DI 3 "cgen_h_uint_3a1_immediate" "")
+ ] 3528))]
+ "CGEN_ENABLE_INSN_P (473)"
+ "cpfsftbi\\t%0,%1,%2,%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfacla0s1_h_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1484))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1485))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1486))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1487))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1488))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1489))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1490))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1491))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1492))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1493))]
+ "CGEN_ENABLE_INSN_P (474)"
+ "cpfacla0s1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfacua0s1_h_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1494))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1495))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1496))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1497))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1498))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1499))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1500))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1501))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1502))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1503))]
+ "CGEN_ENABLE_INSN_P (475)"
+ "cpfacua0s1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfaca0s1_b_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1504))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1505))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1506))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1507))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1508))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1509))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1510))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1511))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1512))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1513))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1514))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1515))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1516))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1517))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1518))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1519))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1520))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1521))]
+ "CGEN_ENABLE_INSN_P (476)"
+ "cpfaca0s1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfaca0s1u_b_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1522))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1523))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1524))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1525))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1526))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1527))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1528))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1529))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1530))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1531))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1532))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1533))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1534))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1535))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1536))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1537))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1538))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1539))]
+ "CGEN_ENABLE_INSN_P (477)"
+ "cpfaca0s1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftbla0s1_h_P0S"
+ [(set (reg:SI 99)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1540))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1541))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1542))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1543))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1544))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1545))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1546))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1547))]
+ "CGEN_ENABLE_INSN_P (478)"
+ "cpfsftbla0s1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftbua0s1_h_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1548))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1549))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1550))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1551))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1552))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1553))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1554))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1555))]
+ "CGEN_ENABLE_INSN_P (479)"
+ "cpfsftbua0s1.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftba0s1_b_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1556))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1557))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1558))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1559))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1560))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1561))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1562))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1563))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1564))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1565))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1566))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1567))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1568))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1569))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1570))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1571))]
+ "CGEN_ENABLE_INSN_P (480)"
+ "cpfsftba0s1.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftba0s1u_b_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1572))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1573))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1574))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1575))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1576))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1577))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1578))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1579))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1580))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1581))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1582))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1583))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1584))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1585))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1586))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1587))]
+ "CGEN_ENABLE_INSN_P (481)"
+ "cpfsftba0s1u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfacla0s0_h_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1588))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1589))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1590))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1591))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1592))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1593))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1594))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1595))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1596))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1597))]
+ "CGEN_ENABLE_INSN_P (482)"
+ "cpfacla0s0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfacua0s0_h_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1598))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1599))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1600))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1601))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1602))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1603))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1604))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1605))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1606))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1607))]
+ "CGEN_ENABLE_INSN_P (483)"
+ "cpfacua0s0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfaca0s0_b_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1608))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1609))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1610))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1611))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1612))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1613))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1614))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1615))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1616))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1617))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1618))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1619))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1620))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1621))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1622))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1623))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1624))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1625))]
+ "CGEN_ENABLE_INSN_P (484)"
+ "cpfaca0s0.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfaca0s0u_b_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1626))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1627))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1628))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1629))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1630))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1631))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1632))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1633))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1634))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1635))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1636))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1637))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1638))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1639))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1640))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1641))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1642))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1643))]
+ "CGEN_ENABLE_INSN_P (485)"
+ "cpfaca0s0u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftbla0s0_h_P0S"
+ [(set (reg:SI 99)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1644))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1645))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1646))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1647))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1648))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1649))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1650))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1651))]
+ "CGEN_ENABLE_INSN_P (486)"
+ "cpfsftbla0s0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftbua0s0_h_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1652))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1653))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1654))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1655))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1656))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1657))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1658))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1659))]
+ "CGEN_ENABLE_INSN_P (487)"
+ "cpfsftbua0s0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftba0s0_b_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1660))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1661))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1662))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1663))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1664))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1665))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1666))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1667))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1668))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1669))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1670))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1671))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1672))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1673))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1674))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1675))]
+ "CGEN_ENABLE_INSN_P (488)"
+ "cpfsftba0s0.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftba0s0u_b_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1676))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1677))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1678))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1679))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1680))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1681))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1682))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1683))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1684))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1685))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1686))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1687))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1688))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1689))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1690))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1691))]
+ "CGEN_ENABLE_INSN_P (489)"
+ "cpfsftba0s0u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsllia0_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
+ ] 1692))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1693))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1694))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1695))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1696))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1697))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1698))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1699))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1700))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1701))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1702))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1703))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1704))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1705))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1706))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1707))]
+ "CGEN_ENABLE_INSN_P (490)"
+ "cpsllia0\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsraia0_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
+ ] 1708))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1709))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1710))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1711))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1712))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1713))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1714))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1715))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1716))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1717))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1718))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1719))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1720))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1721))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1722))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1723))]
+ "CGEN_ENABLE_INSN_P (491)"
+ "cpsraia0\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrlia0_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
+ ] 1724))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1725))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1726))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1727))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1728))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1729))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1730))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1731))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1732))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1733))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1734))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1735))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1736))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1737))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1738))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1739))]
+ "CGEN_ENABLE_INSN_P (492)"
+ "cpsrlia0\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpslla0_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 1740))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1741))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1742))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1743))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1744))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1745))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1746))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1747))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1748))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1749))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1750))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1751))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1752))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1753))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1754))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1755))]
+ "CGEN_ENABLE_INSN_P (493)"
+ "cpslla0\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsraa0_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 1756))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1757))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1758))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1759))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1760))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1761))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1762))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1763))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1764))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1765))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1766))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1767))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1768))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1769))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1770))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1771))]
+ "CGEN_ENABLE_INSN_P (494)"
+ "cpsraa0\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsrla0_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 1772))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1773))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1774))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1775))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1776))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1777))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1778))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1779))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1780))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1781))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1782))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1783))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1784))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1785))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1786))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ ] 1787))]
+ "CGEN_ENABLE_INSN_P (495)"
+ "cpsrla0\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaccpa0_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (const_int 0)
+ ] 1788))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (const_int 0)
+ ] 1789))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (const_int 0)
+ ] 1790))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (const_int 0)
+ ] 1791))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (const_int 0)
+ ] 1792))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (const_int 0)
+ ] 1793))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (const_int 0)
+ ] 1794))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (const_int 0)
+ ] 1795))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (const_int 0)
+ ] 1796))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (const_int 0)
+ ] 1797))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (const_int 0)
+ ] 1798))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (const_int 0)
+ ] 1799))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (const_int 0)
+ ] 1800))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (const_int 0)
+ ] 1801))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (const_int 0)
+ ] 1802))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (const_int 0)
+ ] 1803))]
+ "CGEN_ENABLE_INSN_P (496)"
+ "cpaccpa0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpacsuma0_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (const_int 0)
+ ] 1804))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (const_int 0)
+ ] 1805))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (const_int 0)
+ ] 1806))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (const_int 0)
+ ] 1807))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (const_int 0)
+ ] 1808))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (const_int 0)
+ ] 1809))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (const_int 0)
+ ] 1810))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (const_int 0)
+ ] 1811))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (const_int 0)
+ ] 1812))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (const_int 0)
+ ] 1813))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (const_int 0)
+ ] 1814))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (const_int 0)
+ ] 1815))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (const_int 0)
+ ] 1816))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (const_int 0)
+ ] 1817))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (const_int 0)
+ ] 1818))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (const_int 0)
+ ] 1819))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (const_int 0)
+ ] 1820))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (const_int 0)
+ ] 1821))]
+ "CGEN_ENABLE_INSN_P (497)"
+ "cpacsuma0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovhla0_w_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1822))]
+ "CGEN_ENABLE_INSN_P (498)"
+ "cpmovhla0.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovhua0_w_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1824))]
+ "CGEN_ENABLE_INSN_P (499)"
+ "cpmovhua0.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppackla0_w_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1826))]
+ "CGEN_ENABLE_INSN_P (500)"
+ "cppackla0.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppackua0_w_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1828))]
+ "CGEN_ENABLE_INSN_P (501)"
+ "cppackua0.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppackla0_h_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1830))]
+ "CGEN_ENABLE_INSN_P (502)"
+ "cppackla0.h\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppackua0_h_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1832))]
+ "CGEN_ENABLE_INSN_P (503)"
+ "cppackua0.h\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppacka0_b_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1834))]
+ "CGEN_ENABLE_INSN_P (504)"
+ "cppacka0.b\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cppacka0u_b_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1836))]
+ "CGEN_ENABLE_INSN_P (505)"
+ "cppacka0u.b\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovlla0_w_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1838))]
+ "CGEN_ENABLE_INSN_P (506)"
+ "cpmovlla0.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovlua0_w_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1840))]
+ "CGEN_ENABLE_INSN_P (507)"
+ "cpmovlua0.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovula0_w_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1842))]
+ "CGEN_ENABLE_INSN_P (508)"
+ "cpmovula0.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovuua0_w_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1844))]
+ "CGEN_ENABLE_INSN_P (509)"
+ "cpmovuua0.w\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovla0_h_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1846))]
+ "CGEN_ENABLE_INSN_P (510)"
+ "cpmovla0.h\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovua0_h_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1848))]
+ "CGEN_ENABLE_INSN_P (511)"
+ "cpmovua0.h\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmova0_b_P0S"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 1850))]
+ "CGEN_ENABLE_INSN_P (512)"
+ "cpmova0.b\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsetla0_w_P0S"
+ [(set (reg:SI 99)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1852))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1853))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1854))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1855))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1856))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1857))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1858))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1859))]
+ "CGEN_ENABLE_INSN_P (513)"
+ "cpsetla0.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsetua0_w_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1860))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1861))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1862))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1863))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1864))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1865))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1866))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1867))]
+ "CGEN_ENABLE_INSN_P (514)"
+ "cpsetua0.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpseta0_h_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1868))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1869))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1870))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1871))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1872))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1873))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1874))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1875))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1876))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1877))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1878))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1879))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1880))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1881))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1882))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1883))]
+ "CGEN_ENABLE_INSN_P (515)"
+ "cpseta0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsadla0_h_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1884))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1885))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1886))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1887))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1888))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1889))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1890))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1891))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1892))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1893))]
+ "CGEN_ENABLE_INSN_P (516)"
+ "cpsadla0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsadua0_h_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1894))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1895))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1896))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1897))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1898))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1899))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1900))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1901))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1902))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1903))]
+ "CGEN_ENABLE_INSN_P (517)"
+ "cpsadua0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsada0_b_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1904))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1905))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1906))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1907))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1908))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1909))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1910))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1911))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1912))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1913))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1914))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1915))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1916))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1917))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1918))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1919))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1920))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1921))]
+ "CGEN_ENABLE_INSN_P (518)"
+ "cpsada0.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsada0u_b_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1922))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1923))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1924))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1925))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1926))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1927))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1928))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1929))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1930))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1931))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1932))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1933))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1934))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1935))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1936))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1937))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1938))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1939))]
+ "CGEN_ENABLE_INSN_P (519)"
+ "cpsada0u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsla0_h_P0S"
+ [(set (reg:SI 99)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1940))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1941))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1942))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1943))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1944))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1945))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1946))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1947))]
+ "CGEN_ENABLE_INSN_P (520)"
+ "cpabsla0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsua0_h_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1948))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1949))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1950))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1951))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1952))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1953))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1954))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1955))]
+ "CGEN_ENABLE_INSN_P (521)"
+ "cpabsua0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsa0_b_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1956))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1957))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1958))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1959))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1960))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1961))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1962))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1963))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1964))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1965))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1966))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1967))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1968))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1969))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1970))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1971))]
+ "CGEN_ENABLE_INSN_P (522)"
+ "cpabsa0.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsa0u_b_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1972))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1973))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1974))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1975))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1976))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1977))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1978))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1979))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1980))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1981))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1982))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1983))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1984))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1985))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1986))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1987))]
+ "CGEN_ENABLE_INSN_P (523)"
+ "cpabsa0u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubacla0_h_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1988))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1989))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1990))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1991))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1992))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1993))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1994))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1995))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1996))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1997))]
+ "CGEN_ENABLE_INSN_P (524)"
+ "cpsubacla0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubacua0_h_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 1998))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 1999))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2000))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2001))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2002))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2003))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2004))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2005))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2006))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2007))]
+ "CGEN_ENABLE_INSN_P (525)"
+ "cpsubacua0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubaca0_b_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2008))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2009))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2010))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2011))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2012))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2013))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2014))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2015))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2016))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2017))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2018))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2019))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2020))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2021))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2022))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2023))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2024))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2025))]
+ "CGEN_ENABLE_INSN_P (526)"
+ "cpsubaca0.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubaca0u_b_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2026))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2027))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2028))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2029))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2030))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2031))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2032))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2033))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2034))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2035))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2036))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2037))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2038))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2039))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2040))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2041))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2042))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2043))]
+ "CGEN_ENABLE_INSN_P (527)"
+ "cpsubaca0u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubla0_h_P0S"
+ [(set (reg:SI 99)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2044))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2045))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2046))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2047))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2048))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2049))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2050))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2051))]
+ "CGEN_ENABLE_INSN_P (528)"
+ "cpsubla0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsubua0_h_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2052))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2053))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2054))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2055))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2056))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2057))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2058))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2059))]
+ "CGEN_ENABLE_INSN_P (529)"
+ "cpsubua0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsuba0_b_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2060))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2061))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2062))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2063))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2064))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2065))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2066))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2067))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2068))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2069))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2070))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2071))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2072))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2073))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2074))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2075))]
+ "CGEN_ENABLE_INSN_P (530)"
+ "cpsuba0.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsuba0u_b_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2076))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2077))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2078))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2079))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2080))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2081))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2082))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2083))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2084))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2085))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2086))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2087))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2088))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2089))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2090))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2091))]
+ "CGEN_ENABLE_INSN_P (531)"
+ "cpsuba0u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddacla0_h_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2092))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2093))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2094))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2095))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2096))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2097))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2098))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2099))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2100))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2101))]
+ "CGEN_ENABLE_INSN_P (532)"
+ "cpaddacla0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddacua0_h_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2102))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2103))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2104))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2105))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2106))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2107))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2108))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2109))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2110))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2111))]
+ "CGEN_ENABLE_INSN_P (533)"
+ "cpaddacua0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddaca0_b_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2112))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2113))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2114))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2115))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2116))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2117))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2118))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2119))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2120))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2121))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2122))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2123))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2124))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2125))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2126))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2127))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2128))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2129))]
+ "CGEN_ENABLE_INSN_P (534)"
+ "cpaddaca0.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddaca0u_b_P0S"
+ [(set (reg:SI 86)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2130))
+ (set (reg:SI 124)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2131))
+ (set (reg:SI 103)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2132))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2133))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2134))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2135))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2136))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2137))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2138))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2139))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2140))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2141))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2142))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2143))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2144))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2145))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2146))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2147))]
+ "CGEN_ENABLE_INSN_P (535)"
+ "cpaddaca0u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddla0_h_P0S"
+ [(set (reg:SI 99)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2148))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2149))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2150))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2151))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2152))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2153))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2154))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2155))]
+ "CGEN_ENABLE_INSN_P (536)"
+ "cpaddla0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpaddua0_h_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2156))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2157))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2158))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2159))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2160))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2161))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2162))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2163))]
+ "CGEN_ENABLE_INSN_P (537)"
+ "cpaddua0.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpadda0_b_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2164))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2165))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2166))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2167))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2168))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2169))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2170))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2171))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2172))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2173))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2174))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2175))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2176))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2177))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2178))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2179))]
+ "CGEN_ENABLE_INSN_P (538)"
+ "cpadda0.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpadda0u_b_P0S"
+ [(set (reg:SI 103)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 2180))
+ (set (reg:SI 129)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2181))
+ (set (reg:SI 102)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2182))
+ (set (reg:SI 130)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2183))
+ (set (reg:SI 101)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2184))
+ (set (reg:SI 131)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2185))
+ (set (reg:SI 100)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2186))
+ (set (reg:SI 132)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2187))
+ (set (reg:SI 99)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2188))
+ (set (reg:SI 125)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2189))
+ (set (reg:SI 98)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2190))
+ (set (reg:SI 126)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2191))
+ (set (reg:SI 97)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2192))
+ (set (reg:SI 127)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2193))
+ (set (reg:SI 96)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2194))
+ (set (reg:SI 128)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 2195))]
+ "CGEN_ENABLE_INSN_P (539)"
+ "cpadda0u.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpge_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3282))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3283))]
+ "CGEN_ENABLE_INSN_P (540)"
+ "cpcmpge.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpge_w_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3282))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3283))]
+ "CGEN_ENABLE_INSN_P (541)"
+ "cpcmpge.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgeu_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3284))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3285))]
+ "CGEN_ENABLE_INSN_P (542)"
+ "cpcmpgeu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgeu_w_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3284))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3285))]
+ "CGEN_ENABLE_INSN_P (543)"
+ "cpcmpgeu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpge_h_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3286))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3287))]
+ "CGEN_ENABLE_INSN_P (544)"
+ "cpcmpge.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpge_h_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3286))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3287))]
+ "CGEN_ENABLE_INSN_P (545)"
+ "cpcmpge.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpge_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3288))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3289))]
+ "CGEN_ENABLE_INSN_P (546)"
+ "cpcmpge.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpge_b_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3288))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3289))]
+ "CGEN_ENABLE_INSN_P (547)"
+ "cpcmpge.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgeu_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3290))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3291))]
+ "CGEN_ENABLE_INSN_P (548)"
+ "cpcmpgeu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgeu_b_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3290))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3291))]
+ "CGEN_ENABLE_INSN_P (549)"
+ "cpcmpgeu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgt_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3292))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3293))]
+ "CGEN_ENABLE_INSN_P (550)"
+ "cpcmpgt.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgt_w_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3292))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3293))]
+ "CGEN_ENABLE_INSN_P (551)"
+ "cpcmpgt.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgtu_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3294))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3295))]
+ "CGEN_ENABLE_INSN_P (552)"
+ "cpcmpgtu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgtu_w_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3294))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3295))]
+ "CGEN_ENABLE_INSN_P (553)"
+ "cpcmpgtu.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgt_h_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3296))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3297))]
+ "CGEN_ENABLE_INSN_P (554)"
+ "cpcmpgt.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgt_h_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3296))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3297))]
+ "CGEN_ENABLE_INSN_P (555)"
+ "cpcmpgt.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgt_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3298))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3299))]
+ "CGEN_ENABLE_INSN_P (556)"
+ "cpcmpgt.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgt_b_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3298))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3299))]
+ "CGEN_ENABLE_INSN_P (557)"
+ "cpcmpgt.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgtu_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3300))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3301))]
+ "CGEN_ENABLE_INSN_P (558)"
+ "cpcmpgtu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpgtu_b_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3300))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3301))]
+ "CGEN_ENABLE_INSN_P (559)"
+ "cpcmpgtu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpne_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3302))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3303))]
+ "CGEN_ENABLE_INSN_P (560)"
+ "cpcmpne.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpne_w_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3302))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3303))]
+ "CGEN_ENABLE_INSN_P (561)"
+ "cpcmpne.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpne_h_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3304))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3305))]
+ "CGEN_ENABLE_INSN_P (562)"
+ "cpcmpne.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpne_h_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3304))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3305))]
+ "CGEN_ENABLE_INSN_P (563)"
+ "cpcmpne.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpne_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3306))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3307))]
+ "CGEN_ENABLE_INSN_P (564)"
+ "cpcmpne.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpne_b_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3306))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3307))]
+ "CGEN_ENABLE_INSN_P (565)"
+ "cpcmpne.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpeq_w_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3308))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3309))]
+ "CGEN_ENABLE_INSN_P (566)"
+ "cpcmpeq.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpeq_w_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3308))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3309))]
+ "CGEN_ENABLE_INSN_P (567)"
+ "cpcmpeq.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpeq_h_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3310))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3311))]
+ "CGEN_ENABLE_INSN_P (568)"
+ "cpcmpeq.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpeq_h_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3310))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3311))]
+ "CGEN_ENABLE_INSN_P (569)"
+ "cpcmpeq.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpeq_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3312))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3313))]
+ "CGEN_ENABLE_INSN_P (570)"
+ "cpcmpeq.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpeq_b_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3312))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3313))]
+ "CGEN_ENABLE_INSN_P (571)"
+ "cpcmpeq.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpeqz_b_C3"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3314))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3315))]
+ "CGEN_ENABLE_INSN_P (572)"
+ "cpcmpeqz.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcmpeqz_b_P0S_P1"
+ [(set (reg:SI 81)
+ (unspec:SI [
+ (match_operand:DI 0 "general_operand" "x")
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3314))
+ (set (reg:SI 123)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3315))]
+ "CGEN_ENABLE_INSN_P (573)"
+ "cpcmpeqz.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovtocc_C3"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 3378)]
+ "CGEN_ENABLE_INSN_P (574)"
+ "cpmovtocc\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovtocc_P0S_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 3378)]
+ "CGEN_ENABLE_INSN_P (575)"
+ "cpmovtocc\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovtocsar1_C3"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 3380)]
+ "CGEN_ENABLE_INSN_P (576)"
+ "cpmovtocsar1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovtocsar1_P0S_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 3380)]
+ "CGEN_ENABLE_INSN_P (577)"
+ "cpmovtocsar1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovtocsar0_C3"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 3382)]
+ "CGEN_ENABLE_INSN_P (578)"
+ "cpmovtocsar0\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovtocsar0_P0S_P1"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "x")
+ ] 3382)]
+ "CGEN_ENABLE_INSN_P (579)"
+ "cpmovtocsar0\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovfrcc_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 3384))]
+ "CGEN_ENABLE_INSN_P (580)"
+ "cpmovfrcc\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovfrcc_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 3384))]
+ "CGEN_ENABLE_INSN_P (581)"
+ "cpmovfrcc\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovfrcsar1_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 3386))]
+ "CGEN_ENABLE_INSN_P (582)"
+ "cpmovfrcsar1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovfrcsar1_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 3386))]
+ "CGEN_ENABLE_INSN_P (583)"
+ "cpmovfrcsar1\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovfrcsar0_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 3388))]
+ "CGEN_ENABLE_INSN_P (584)"
+ "cpmovfrcsar0\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmovfrcsar0_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (const_int 0)
+ ] 3388))]
+ "CGEN_ENABLE_INSN_P (585)"
+ "cpmovfrcsar0\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdcastw_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3316))]
+ "CGEN_ENABLE_INSN_P (586)"
+ "cdcastw\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdcastw_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3316))]
+ "CGEN_ENABLE_INSN_P (587)"
+ "cdcastw\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdcastuw_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3318))]
+ "CGEN_ENABLE_INSN_P (588)"
+ "cdcastuw\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cdcastuw_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3318))]
+ "CGEN_ENABLE_INSN_P (589)"
+ "cdcastuw\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcasth_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3320))]
+ "CGEN_ENABLE_INSN_P (590)"
+ "cpcasth.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcasth_w_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3320))]
+ "CGEN_ENABLE_INSN_P (591)"
+ "cpcasth.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcastuh_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3322))]
+ "CGEN_ENABLE_INSN_P (592)"
+ "cpcastuh.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcastuh_w_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3322))]
+ "CGEN_ENABLE_INSN_P (593)"
+ "cpcastuh.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcastb_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3324))]
+ "CGEN_ENABLE_INSN_P (594)"
+ "cpcastb.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcastb_w_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3324))]
+ "CGEN_ENABLE_INSN_P (595)"
+ "cpcastb.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcastub_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3326))]
+ "CGEN_ENABLE_INSN_P (596)"
+ "cpcastub.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcastub_w_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3326))]
+ "CGEN_ENABLE_INSN_P (597)"
+ "cpcastub.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcastb_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3328))]
+ "CGEN_ENABLE_INSN_P (598)"
+ "cpcastb.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcastb_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3328))]
+ "CGEN_ENABLE_INSN_P (599)"
+ "cpcastb.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcastub_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3330))]
+ "CGEN_ENABLE_INSN_P (600)"
+ "cpcastub.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpcastub_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3330))]
+ "CGEN_ENABLE_INSN_P (601)"
+ "cpcastub.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextl_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3332))]
+ "CGEN_ENABLE_INSN_P (602)"
+ "cpextl.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextl_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3332))]
+ "CGEN_ENABLE_INSN_P (603)"
+ "cpextl.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextlu_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3334))]
+ "CGEN_ENABLE_INSN_P (604)"
+ "cpextlu.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextlu_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3334))]
+ "CGEN_ENABLE_INSN_P (605)"
+ "cpextlu.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextl_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3336))]
+ "CGEN_ENABLE_INSN_P (606)"
+ "cpextl.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextl_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3336))]
+ "CGEN_ENABLE_INSN_P (607)"
+ "cpextl.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextlu_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3338))]
+ "CGEN_ENABLE_INSN_P (608)"
+ "cpextlu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextlu_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3338))]
+ "CGEN_ENABLE_INSN_P (609)"
+ "cpextlu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextu_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3340))]
+ "CGEN_ENABLE_INSN_P (610)"
+ "cpextu.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextu_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3340))]
+ "CGEN_ENABLE_INSN_P (611)"
+ "cpextu.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextuu_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3342))]
+ "CGEN_ENABLE_INSN_P (612)"
+ "cpextuu.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextuu_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3342))]
+ "CGEN_ENABLE_INSN_P (613)"
+ "cpextuu.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextu_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3344))]
+ "CGEN_ENABLE_INSN_P (614)"
+ "cpextu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextu_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3344))]
+ "CGEN_ENABLE_INSN_P (615)"
+ "cpextu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextuu_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3346))]
+ "CGEN_ENABLE_INSN_P (616)"
+ "cpextuu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpextuu_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3346))]
+ "CGEN_ENABLE_INSN_P (617)"
+ "cpextuu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpbcast_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3348))]
+ "CGEN_ENABLE_INSN_P (618)"
+ "cpbcast.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpbcast_w_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3348))]
+ "CGEN_ENABLE_INSN_P (619)"
+ "cpbcast.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpbcast_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3350))]
+ "CGEN_ENABLE_INSN_P (620)"
+ "cpbcast.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpbcast_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3350))]
+ "CGEN_ENABLE_INSN_P (621)"
+ "cpbcast.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpbcast_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3352))]
+ "CGEN_ENABLE_INSN_P (622)"
+ "cpbcast.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpbcast_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3352))]
+ "CGEN_ENABLE_INSN_P (623)"
+ "cpbcast.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpccadd_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "0")
+ ] 3354))]
+ "CGEN_ENABLE_INSN_P (624)"
+ "cpccadd.b\\t%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpccadd_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "0")
+ ] 3354))]
+ "CGEN_ENABLE_INSN_P (625)"
+ "cpccadd.b\\t%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cphadd_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3356))]
+ "CGEN_ENABLE_INSN_P (626)"
+ "cphadd.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cphadd_w_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3356))]
+ "CGEN_ENABLE_INSN_P (627)"
+ "cphadd.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cphadd_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3358))]
+ "CGEN_ENABLE_INSN_P (628)"
+ "cphadd.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cphadd_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3358))]
+ "CGEN_ENABLE_INSN_P (629)"
+ "cphadd.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cphadd_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3360))]
+ "CGEN_ENABLE_INSN_P (630)"
+ "cphadd.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cphadd_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3360))]
+ "CGEN_ENABLE_INSN_P (631)"
+ "cphadd.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cphaddu_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3362))]
+ "CGEN_ENABLE_INSN_P (632)"
+ "cphaddu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cphaddu_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3362))]
+ "CGEN_ENABLE_INSN_P (633)"
+ "cphaddu.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpnorm_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3364))]
+ "CGEN_ENABLE_INSN_P (634)"
+ "cpnorm.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpnorm_w_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3364))]
+ "CGEN_ENABLE_INSN_P (635)"
+ "cpnorm.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpnorm_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3366))]
+ "CGEN_ENABLE_INSN_P (636)"
+ "cpnorm.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpnorm_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3366))]
+ "CGEN_ENABLE_INSN_P (637)"
+ "cpnorm.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpldz_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3368))]
+ "CGEN_ENABLE_INSN_P (638)"
+ "cpldz.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpldz_w_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3368))]
+ "CGEN_ENABLE_INSN_P (639)"
+ "cpldz.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpldz_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3370))]
+ "CGEN_ENABLE_INSN_P (640)"
+ "cpldz.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpldz_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3370))]
+ "CGEN_ENABLE_INSN_P (641)"
+ "cpldz.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsz_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3372))]
+ "CGEN_ENABLE_INSN_P (642)"
+ "cpabsz.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsz_w_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3372))]
+ "CGEN_ENABLE_INSN_P (643)"
+ "cpabsz.w\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsz_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3374))]
+ "CGEN_ENABLE_INSN_P (644)"
+ "cpabsz.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsz_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3374))]
+ "CGEN_ENABLE_INSN_P (645)"
+ "cpabsz.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsz_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3376))]
+ "CGEN_ENABLE_INSN_P (646)"
+ "cpabsz.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpabsz_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3376))]
+ "CGEN_ENABLE_INSN_P (647)"
+ "cpabsz.b\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmov_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 4184))]
+ "CGEN_ENABLE_INSN_P (648)"
+ "cpmov\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmov_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 4184))]
+ "CGEN_ENABLE_INSN_P (649)"
+ "cpmov\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftbs1_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3524))]
+ "CGEN_ENABLE_INSN_P (650)"
+ "cpfsftbs1\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftbs1_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3524))]
+ "CGEN_ENABLE_INSN_P (651)"
+ "cpfsftbs1\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftbs0_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3526))]
+ "CGEN_ENABLE_INSN_P (652)"
+ "cpfsftbs0\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpfsftbs0_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3526))]
+ "CGEN_ENABLE_INSN_P (653)"
+ "cpfsftbs0\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsel_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3530))]
+ "CGEN_ENABLE_INSN_P (654)"
+ "cpsel\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpsel_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3530))]
+ "CGEN_ENABLE_INSN_P (655)"
+ "cpsel\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpunpackl_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3512))]
+ "CGEN_ENABLE_INSN_P (656)"
+ "cpunpackl.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpunpackl_w_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3512))]
+ "CGEN_ENABLE_INSN_P (657)"
+ "cpunpackl.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpunpackl_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3514))]
+ "CGEN_ENABLE_INSN_P (658)"
+ "cpunpackl.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpunpackl_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3514))]
+ "CGEN_ENABLE_INSN_P (659)"
+ "cpunpackl.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpunpackl_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3516))]
+ "CGEN_ENABLE_INSN_P (660)"
+ "cpunpackl.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpunpackl_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3516))]
+ "CGEN_ENABLE_INSN_P (661)"
+ "cpunpackl.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpunpacku_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3518))]
+ "CGEN_ENABLE_INSN_P (662)"
+ "cpunpacku.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpunpacku_w_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3518))]
+ "CGEN_ENABLE_INSN_P (663)"
+ "cpunpacku.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpunpacku_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3520))]
+ "CGEN_ENABLE_INSN_P (664)"
+ "cpunpacku.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpunpacku_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3520))]
+ "CGEN_ENABLE_INSN_P (665)"
+ "cpunpacku.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpunpacku_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3522))]
+ "CGEN_ENABLE_INSN_P (666)"
+ "cpunpacku.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpunpacku_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3522))]
+ "CGEN_ENABLE_INSN_P (667)"
+ "cpunpacku.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpadd3_w_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3550))]
+ "CGEN_ENABLE_INSN_P (668)"
+ "cpadd3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpadd3_w_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3550))]
+ "CGEN_ENABLE_INSN_P (669)"
+ "cpadd3.w\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpadd3_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3552))]
+ "CGEN_ENABLE_INSN_P (670)"
+ "cpadd3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpadd3_h_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3552))]
+ "CGEN_ENABLE_INSN_P (671)"
+ "cpadd3.h\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpadd3_b_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3554))]
+ "CGEN_ENABLE_INSN_P (672)"
+ "cpadd3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpadd3_b_P0S_P1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "x")
+ (match_operand:DI 2 "general_operand" "x")
+ ] 3554))]
+ "CGEN_ENABLE_INSN_P (673)"
+ "cpadd3.b\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0s_p1")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_c0nop_P0_P0S"
+ [(unspec_volatile [
+ (const_int 0)
+ ] 2196)]
+ "CGEN_ENABLE_INSN_P (674)"
+ "c0nop"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0_p0s")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cpmoviu_h_C3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_uint_8a1_immediate" "")
+ ] 3178))]
+ "CGEN_ENABLE_INSN_P (675)"
+ "cpmoviu.h\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cmovh_rn_crm"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 4168))]
+ "CGEN_ENABLE_INSN_P (676)"
+ "cmovh\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cmovh_rn_crm_p0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3556))]
+ "CGEN_ENABLE_INSN_P (677)"
+ "cmovh\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cmovh_crn_rm"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 4170))]
+ "CGEN_ENABLE_INSN_P (678)"
+ "cmovh\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cmovh_crn_rm_p0"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec_volatile:DI [
+ (match_operand:DI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3558))]
+ "CGEN_ENABLE_INSN_P (679)"
+ "cmovh\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cmovc_rn_ccrm"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "y")
+ ] 4172))]
+ "CGEN_ENABLE_INSN_P (680)"
+ "cmovc\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cmovc_rn_ccrm_p0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "y")
+ ] 3560))]
+ "CGEN_ENABLE_INSN_P (681)"
+ "cmovc\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cmovc_ccrn_rm"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=y")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ ] 4174))]
+ "CGEN_ENABLE_INSN_P (682)"
+ "cmovc\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cmovc_ccrn_rm_p0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=y")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3562))]
+ "CGEN_ENABLE_INSN_P (683)"
+ "cmovc\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cmov_rn_crm"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 4176))]
+ "CGEN_ENABLE_INSN_P (684)"
+ "cmov\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cmov_rn_crm_p0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3564))]
+ "CGEN_ENABLE_INSN_P (685)"
+ "cmov\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cmov_crn_rm"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec:DI [
+ (match_operand:DI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 4178))]
+ "CGEN_ENABLE_INSN_P (686)"
+ "cmov\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "c3")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cmov_crn_rm_p0"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
+ (unspec_volatile:DI [
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3566))]
+ "CGEN_ENABLE_INSN_P (687)"
+ "cmov\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "cop")
+ (set_attr "slots" "p0")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bsrv"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3568)
+ (const_int 0))
+ (match_dup 0)
+ (pc)))
+ (set (reg:SI 17)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3570))
+ (set (reg:SI 133)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3571))]
+ "CGEN_ENABLE_INSN_P (688)"
+ "bsrv\\t%l0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_jsrv"
+ [(set (pc)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3572))
+ (set (reg:SI 17)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3574))
+ (set (reg:SI 133)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3575))]
+ "CGEN_ENABLE_INSN_P (689)"
+ "jsrv\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_synccp"
+ [(unspec_volatile [
+ (const_int 0)
+ ] 3576)]
+ "CGEN_ENABLE_INSN_P (690)"
+ "synccp"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bcpaf"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
+ (match_operand:SI 1 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ (reg:SI 81)
+ ] 3578)
+ (const_int 0))
+ (match_dup 1)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (691)"
+ "bcpaf\\t%0,%l1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bcpat"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
+ (match_operand:SI 1 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ (reg:SI 81)
+ ] 3580)
+ (const_int 0))
+ (match_dup 1)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (692)"
+ "bcpat\\t%0,%l1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bcpne"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
+ (match_operand:SI 1 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ (reg:SI 81)
+ ] 3582)
+ (const_int 0))
+ (match_dup 1)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (693)"
+ "bcpne\\t%0,%l1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bcpeq"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
+ (match_operand:SI 1 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ (reg:SI 81)
+ ] 3584)
+ (const_int 0))
+ (match_dup 1)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (694)"
+ "bcpeq\\t%0,%l1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lmcpm1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
+ (unspec:DI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:DI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 31)
+ (reg:SI 30)
+ ] 3586))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 31)
+ (reg:SI 30)
+ ] 3588))]
+ "CGEN_ENABLE_INSN_P (695)"
+ "lmcpm1\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_smcpm1"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:DI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 31)
+ (reg:SI 30)
+ ] 3590))]
+ "CGEN_ENABLE_INSN_P (696)"
+ "smcpm1\\t%1,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lwcpm1"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 31)
+ (reg:SI 30)
+ (mem:SI (scratch:SI))
+ ] 3592))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 31)
+ (reg:SI 30)
+ (mem:SI (scratch:SI))
+ ] 3594))]
+ "CGEN_ENABLE_INSN_P (697)"
+ "lwcpm1\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_swcpm1"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 31)
+ (reg:SI 30)
+ ] 3596))
+ (set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 31)
+ (reg:SI 30)
+ ] 3598))]
+ "CGEN_ENABLE_INSN_P (698)"
+ "swcpm1\\t%1,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lhcpm1"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 31)
+ (reg:SI 30)
+ (mem:SI (scratch:SI))
+ ] 3600))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 31)
+ (reg:SI 30)
+ (mem:SI (scratch:SI))
+ ] 3602))]
+ "CGEN_ENABLE_INSN_P (699)"
+ "lhcpm1\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_shcpm1"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 31)
+ (reg:SI 30)
+ ] 3604))
+ (set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 31)
+ (reg:SI 30)
+ ] 3606))]
+ "CGEN_ENABLE_INSN_P (700)"
+ "shcpm1\\t%1,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lbcpm1"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 31)
+ (reg:SI 30)
+ (mem:SI (scratch:SI))
+ ] 3608))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 31)
+ (reg:SI 30)
+ (mem:SI (scratch:SI))
+ ] 3610))]
+ "CGEN_ENABLE_INSN_P (701)"
+ "lbcpm1\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_sbcpm1"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 31)
+ (reg:SI 30)
+ ] 3612))
+ (set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 31)
+ (reg:SI 30)
+ ] 3614))]
+ "CGEN_ENABLE_INSN_P (702)"
+ "sbcpm1\\t%1,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lmcpm0"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
+ (unspec:DI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:DI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 29)
+ (reg:SI 28)
+ ] 3616))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 29)
+ (reg:SI 28)
+ ] 3618))]
+ "CGEN_ENABLE_INSN_P (703)"
+ "lmcpm0\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_smcpm0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:DI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 29)
+ (reg:SI 28)
+ ] 3620))]
+ "CGEN_ENABLE_INSN_P (704)"
+ "smcpm0\\t%1,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lwcpm0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 29)
+ (reg:SI 28)
+ (mem:SI (scratch:SI))
+ ] 3622))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 29)
+ (reg:SI 28)
+ (mem:SI (scratch:SI))
+ ] 3624))]
+ "CGEN_ENABLE_INSN_P (705)"
+ "lwcpm0\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_swcpm0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 29)
+ (reg:SI 28)
+ ] 3626))
+ (set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 29)
+ (reg:SI 28)
+ ] 3628))]
+ "CGEN_ENABLE_INSN_P (706)"
+ "swcpm0\\t%1,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lhcpm0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 29)
+ (reg:SI 28)
+ (mem:SI (scratch:SI))
+ ] 3630))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 29)
+ (reg:SI 28)
+ (mem:SI (scratch:SI))
+ ] 3632))]
+ "CGEN_ENABLE_INSN_P (707)"
+ "lhcpm0\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_shcpm0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 29)
+ (reg:SI 28)
+ ] 3634))
+ (set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 29)
+ (reg:SI 28)
+ ] 3636))]
+ "CGEN_ENABLE_INSN_P (708)"
+ "shcpm0\\t%1,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lbcpm0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 29)
+ (reg:SI 28)
+ (mem:SI (scratch:SI))
+ ] 3638))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 29)
+ (reg:SI 28)
+ (mem:SI (scratch:SI))
+ ] 3640))]
+ "CGEN_ENABLE_INSN_P (709)"
+ "lbcpm0\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_sbcpm0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 29)
+ (reg:SI 28)
+ ] 3642))
+ (set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 29)
+ (reg:SI 28)
+ ] 3644))]
+ "CGEN_ENABLE_INSN_P (710)"
+ "sbcpm0\\t%1,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lmcpa"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
+ (unspec:DI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:DI 3 "cgen_h_sint_10a1_immediate" "")
+ ] 3646))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ ] 3648))]
+ "CGEN_ENABLE_INSN_P (711)"
+ "lmcpa\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_smcpa"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:DI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ ] 3650))]
+ "CGEN_ENABLE_INSN_P (712)"
+ "smcpa\\t%1,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lwcpa"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (mem:SI (scratch:SI))
+ ] 3652))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (mem:SI (scratch:SI))
+ ] 3654))]
+ "CGEN_ENABLE_INSN_P (713)"
+ "lwcpa\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_swcpa"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ ] 3656))
+ (set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 3658))]
+ "CGEN_ENABLE_INSN_P (714)"
+ "swcpa\\t%1,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lhcpa"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (mem:SI (scratch:SI))
+ ] 3660))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (mem:SI (scratch:SI))
+ ] 3662))]
+ "CGEN_ENABLE_INSN_P (715)"
+ "lhcpa\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_shcpa"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ ] 3664))
+ (set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 3666))]
+ "CGEN_ENABLE_INSN_P (716)"
+ "shcpa\\t%1,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lbcpa"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (mem:SI (scratch:SI))
+ ] 3668))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (mem:SI (scratch:SI))
+ ] 3670))]
+ "CGEN_ENABLE_INSN_P (717)"
+ "lbcpa\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_sbcpa"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ ] 3672))
+ (set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ ] 3674))]
+ "CGEN_ENABLE_INSN_P (718)"
+ "sbcpa\\t%1,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lmcp16"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
+ (unspec:DI [
+ (match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3676))]
+ "CGEN_ENABLE_INSN_P (719)"
+ "lmcp\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_smcp16"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "em")
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3678)]
+ "CGEN_ENABLE_INSN_P (720)"
+ "smcp\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lwcp16"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 3680))]
+ "CGEN_ENABLE_INSN_P (721)"
+ "lwcp\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_swcp16"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "em")
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3682))]
+ "CGEN_ENABLE_INSN_P (722)"
+ "swcp\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lmcpi"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
+ (unspec:DI [
+ (match_operand:SI 2 "general_operand" "1")
+ ] 3684))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ ] 3686))]
+ "CGEN_ENABLE_INSN_P (723)"
+ "lmcpi\\t%0,(%2+)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_smcpi"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:DI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ ] 3688))]
+ "CGEN_ENABLE_INSN_P (724)"
+ "smcpi\\t%1,(%2+)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lwcpi"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (mem:SI (scratch:SI))
+ ] 3690))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (mem:SI (scratch:SI))
+ ] 3692))]
+ "CGEN_ENABLE_INSN_P (725)"
+ "lwcpi\\t%0,(%2+)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_swcpi"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "em")
+ (match_operand:SI 2 "general_operand" "0")
+ ] 3694))
+ (set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3696))]
+ "CGEN_ENABLE_INSN_P (726)"
+ "swcpi\\t%1,(%2+)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lmcp"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
+ (unspec:DI [
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3698))]
+ "CGEN_ENABLE_INSN_P (727)"
+ "lmcp\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_smcp"
+ [(unspec_volatile [
+ (match_operand:DI 0 "general_operand" "em")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3700)]
+ "CGEN_ENABLE_INSN_P (728)"
+ "smcp\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lwcp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 3702))]
+ "CGEN_ENABLE_INSN_P (729)"
+ "lwcp\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_swcp"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "em")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3704))]
+ "CGEN_ENABLE_INSN_P (730)"
+ "swcp\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_ssubu"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3706))]
+ "CGEN_ENABLE_INSN_P (731)"
+ "ssubu\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_saddu"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3708))]
+ "CGEN_ENABLE_INSN_P (732)"
+ "saddu\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_ssub"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3710))]
+ "CGEN_ENABLE_INSN_P (733)"
+ "ssub\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_sadd"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3712))]
+ "CGEN_ENABLE_INSN_P (734)"
+ "sadd\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_clipu"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3714))]
+ "CGEN_ENABLE_INSN_P (735)"
+ "clipu\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_clip"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3716))]
+ "CGEN_ENABLE_INSN_P (736)"
+ "clip\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_maxu"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3718))]
+ "CGEN_ENABLE_INSN_P (737)"
+ "maxu\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_minu"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3720))]
+ "CGEN_ENABLE_INSN_P (738)"
+ "minu\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_max"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3722))]
+ "CGEN_ENABLE_INSN_P (739)"
+ "max\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_min"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3724))]
+ "CGEN_ENABLE_INSN_P (740)"
+ "min\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_ave"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3726))]
+ "CGEN_ENABLE_INSN_P (741)"
+ "ave\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_abs"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3728))]
+ "CGEN_ENABLE_INSN_P (742)"
+ "abs\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_ldz"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3730))]
+ "CGEN_ENABLE_INSN_P (743)"
+ "ldz\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_dbreak"
+ [(set (reg:SI 40)
+ (unspec_volatile:SI [
+ (reg:SI 40)
+ ] 3732))]
+ "CGEN_ENABLE_INSN_P (744)"
+ "dbreak"
+ [(set_attr "may_trap" "yes")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_dret"
+ [(set (pc)
+ (unspec:SI [
+ (reg:SI 41)
+ (reg:SI 40)
+ ] 3734))
+ (set (reg:SI 40)
+ (unspec:SI [
+ (reg:SI 41)
+ (reg:SI 40)
+ ] 3736))
+ (set (reg:SI 134)
+ (unspec:SI [
+ (reg:SI 41)
+ (reg:SI 40)
+ ] 3737))]
+ "CGEN_ENABLE_INSN_P (745)"
+ "dret"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_divu"
+ [(set (pc)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3738))
+ (set (reg:SI 24)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3740))
+ (set (reg:SI 135)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3741))
+ (set (reg:SI 23)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3742))
+ (set (reg:SI 136)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3743))]
+ "CGEN_ENABLE_INSN_P (746)"
+ "divu\\t%0,%1"
+ [(set_attr "may_trap" "yes")
+ (set_attr "latency" "34")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "div")])
+
+
+(define_insn "cgen_intrinsic_div"
+ [(set (pc)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3744))
+ (set (reg:SI 24)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3746))
+ (set (reg:SI 135)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3747))
+ (set (reg:SI 23)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3748))
+ (set (reg:SI 136)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3749))]
+ "CGEN_ENABLE_INSN_P (747)"
+ "div\\t%0,%1"
+ [(set_attr "may_trap" "yes")
+ (set_attr "latency" "34")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "div")])
+
+
+(define_insn "cgen_intrinsic_maddru"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3750))
+ (set (reg:SI 24)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3752))
+ (set (reg:SI 135)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3753))
+ (set (reg:SI 23)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3754))
+ (set (reg:SI 136)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3755))]
+ "CGEN_ENABLE_INSN_P (748)"
+ "maddru\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "3")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "mulr")])
+
+
+(define_insn "cgen_intrinsic_maddr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3756))
+ (set (reg:SI 24)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3758))
+ (set (reg:SI 135)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3759))
+ (set (reg:SI 23)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3760))
+ (set (reg:SI 136)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3761))]
+ "CGEN_ENABLE_INSN_P (749)"
+ "maddr\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "3")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "mulr")])
+
+
+(define_insn "cgen_intrinsic_maddu"
+ [(set (reg:SI 24)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "general_operand" "r")
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3762))
+ (set (reg:SI 135)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3763))
+ (set (reg:SI 23)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3764))
+ (set (reg:SI 136)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3765))]
+ "CGEN_ENABLE_INSN_P (750)"
+ "maddu\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "mul")])
+
+
+(define_insn "cgen_intrinsic_madd"
+ [(set (reg:SI 24)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "general_operand" "r")
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3766))
+ (set (reg:SI 135)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3767))
+ (set (reg:SI 23)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3768))
+ (set (reg:SI 136)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (reg:SI 24)
+ (reg:SI 23)
+ ] 3769))]
+ "CGEN_ENABLE_INSN_P (751)"
+ "madd\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "mul")])
+
+
+(define_insn "cgen_intrinsic_mulru"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3770))
+ (set (reg:SI 24)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3772))
+ (set (reg:SI 135)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3773))
+ (set (reg:SI 23)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3774))
+ (set (reg:SI 136)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3775))]
+ "CGEN_ENABLE_INSN_P (752)"
+ "mulru\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "3")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "mulr")])
+
+
+(define_insn "cgen_intrinsic_mulr"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3776))
+ (set (reg:SI 24)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3778))
+ (set (reg:SI 135)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3779))
+ (set (reg:SI 23)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3780))
+ (set (reg:SI 136)
+ (unspec:SI [
+ (match_dup 1)
+ (match_dup 2)
+ ] 3781))]
+ "CGEN_ENABLE_INSN_P (753)"
+ "mulr\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "3")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "mulr")])
+
+
+(define_insn "cgen_intrinsic_mulu"
+ [(set (reg:SI 24)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3782))
+ (set (reg:SI 135)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3783))
+ (set (reg:SI 23)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3784))
+ (set (reg:SI 136)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3785))]
+ "CGEN_ENABLE_INSN_P (754)"
+ "mulu\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "mul")])
+
+
+(define_insn "cgen_intrinsic_mul"
+ [(set (reg:SI 24)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3786))
+ (set (reg:SI 135)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3787))
+ (set (reg:SI 23)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3788))
+ (set (reg:SI 136)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3789))]
+ "CGEN_ENABLE_INSN_P (755)"
+ "mul\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "mul")])
+
+
+(define_insn "cgen_intrinsic_cache"
+ [(unspec_volatile [
+ (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3790)]
+ "CGEN_ENABLE_INSN_P (756)"
+ "cache\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_tas"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 3792))
+ (set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_dup 1)
+ (mem:SI (scratch:SI))
+ ] 3794))]
+ "CGEN_ENABLE_INSN_P (757)"
+ "tas\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_btstm"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
+ (mem:SI (scratch:SI))
+ ] 3796))]
+ "CGEN_ENABLE_INSN_P (758)"
+ "btstm\\t$0,(%1),%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bnotm"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_uint_3a1_immediate" "")
+ (mem:SI (scratch:SI))
+ ] 3798))]
+ "CGEN_ENABLE_INSN_P (759)"
+ "bnotm\\t(%0),%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bclrm"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_uint_3a1_immediate" "")
+ (mem:SI (scratch:SI))
+ ] 3800))]
+ "CGEN_ENABLE_INSN_P (760)"
+ "bclrm\\t(%0),%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bsetm"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_uint_3a1_immediate" "")
+ (mem:SI (scratch:SI))
+ ] 3802))]
+ "CGEN_ENABLE_INSN_P (761)"
+ "bsetm\\t(%0),%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_ldcb"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
+ ] 3804))]
+ "CGEN_ENABLE_INSN_P (762)"
+ "ldcb\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "3")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "ldcb")])
+
+
+(define_insn "cgen_intrinsic_stcb"
+ [(unspec_volatile [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
+ ] 3806)]
+ "CGEN_ENABLE_INSN_P (763)"
+ "stcb\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "stcb")])
+
+
+(define_insn "cgen_intrinsic_syncm"
+ [(unspec_volatile [
+ (const_int 0)
+ ] 3808)]
+ "CGEN_ENABLE_INSN_P (764)"
+ "syncm"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_break"
+ [(set (pc)
+ (unspec_volatile:SI [
+ (const_int 0)
+ ] 3810))]
+ "CGEN_ENABLE_INSN_P (765)"
+ "break"
+ [(set_attr "may_trap" "yes")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_swi"
+ [(set (reg:SI 36)
+ (unspec_volatile:SI [
+ (match_operand:SI 0 "cgen_h_uint_2a1_immediate" "")
+ (reg:SI 36)
+ ] 3812))]
+ "CGEN_ENABLE_INSN_P (766)"
+ "swi\\t%0"
+ [(set_attr "may_trap" "yes")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_sleep"
+ [(unspec_volatile [
+ (const_int 0)
+ ] 3814)]
+ "CGEN_ENABLE_INSN_P (767)"
+ "sleep"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_halt"
+ [(unspec_volatile [
+ (reg:SI 32)
+ ] 3816)]
+ "CGEN_ENABLE_INSN_P (768)"
+ "halt"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_reti"
+ [(set (pc)
+ (unspec:SI [
+ (reg:SI 32)
+ (reg:SI 42)
+ (reg:SI 39)
+ (reg:SI 35)
+ ] 3818))]
+ "CGEN_ENABLE_INSN_P (769)"
+ "reti"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "ret")])
+
+
+(define_insn "cgen_intrinsic_ei"
+ [(set (reg:SI 32)
+ (unspec_volatile:SI [
+ (reg:SI 32)
+ ] 3820))]
+ "CGEN_ENABLE_INSN_P (770)"
+ "ei"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_di"
+ [(set (reg:SI 32)
+ (unspec_volatile:SI [
+ (reg:SI 32)
+ ] 3822))]
+ "CGEN_ENABLE_INSN_P (771)"
+ "di"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_ldc"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "c")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3824))]
+ "CGEN_ENABLE_INSN_P (772)"
+ "ldc\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "ldc")])
+
+
+(define_insn "cgen_intrinsic_ldc_lo"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (reg:SI 24)
+ ] 3826))]
+ "CGEN_ENABLE_INSN_P (773)"
+ "ldc\\t%0,$lo"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "ldc")])
+
+
+(define_insn "cgen_intrinsic_ldc_hi"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (reg:SI 23)
+ ] 3828))]
+ "CGEN_ENABLE_INSN_P (774)"
+ "ldc\\t%0,$hi"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "ldc")])
+
+
+(define_insn "cgen_intrinsic_ldc_lp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (reg:SI 17)
+ ] 3830))]
+ "CGEN_ENABLE_INSN_P (775)"
+ "ldc\\t%0,$lp"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "ldc")])
+
+
+(define_insn "cgen_intrinsic_stc"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=c")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3832))]
+ "CGEN_ENABLE_INSN_P (776)"
+ "stc\\t%1,%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "stc")])
+
+
+(define_insn "cgen_intrinsic_stc_lo"
+ [(set (reg:SI 24)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ ] 3834))
+ (set (reg:SI 135)
+ (unspec:SI [
+ (match_dup 0)
+ ] 3835))]
+ "CGEN_ENABLE_INSN_P (777)"
+ "stc\\t%0,$lo"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "stc")])
+
+
+(define_insn "cgen_intrinsic_stc_hi"
+ [(set (reg:SI 23)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ ] 3836))
+ (set (reg:SI 136)
+ (unspec:SI [
+ (match_dup 0)
+ ] 3837))]
+ "CGEN_ENABLE_INSN_P (778)"
+ "stc\\t%0,$hi"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "stc")])
+
+
+(define_insn "cgen_intrinsic_stc_lp"
+ [(set (reg:SI 17)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ ] 3838))
+ (set (reg:SI 133)
+ (unspec:SI [
+ (match_dup 0)
+ ] 3839))]
+ "CGEN_ENABLE_INSN_P (779)"
+ "stc\\t%0,$lp"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "stc")])
+
+
+(define_insn "cgen_intrinsic_erepeat"
+ [(set (reg:SI 22)
+ (unspec:SI [
+ (match_operand:SI 0 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3840))
+ (set (reg:SI 137)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3841))
+ (set (reg:SI 21)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3842))
+ (set (reg:SI 138)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3843))
+ (set (reg:SI 20)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3844))
+ (set (reg:SI 139)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3845))]
+ "CGEN_ENABLE_INSN_P (780)"
+ "erepeat\\t%l0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_repeat"
+ [(set (reg:SI 22)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3846))
+ (set (reg:SI 137)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3847))
+ (set (reg:SI 21)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3848))
+ (set (reg:SI 138)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3849))
+ (set (reg:SI 20)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3850))
+ (set (reg:SI 139)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3851))]
+ "CGEN_ENABLE_INSN_P (781)"
+ "repeat\\t%0,%l1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_ret"
+ [(set (pc)
+ (unspec:SI [
+ (reg:SI 32)
+ (reg:SI 42)
+ (reg:SI 17)
+ ] 3852))]
+ "CGEN_ENABLE_INSN_P (782)"
+ "ret"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "ret")])
+
+
+(define_insn "cgen_intrinsic_jsr"
+ [(set (pc)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3854))
+ (set (reg:SI 17)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3856))
+ (set (reg:SI 133)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3857))]
+ "CGEN_ENABLE_INSN_P (783)"
+ "jsr\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_jmp24"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3858)
+ (const_int 0))
+ (match_dup 0)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (784)"
+ "jmp\\t%l0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_jmp"
+ [(set (pc)
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3860))]
+ "CGEN_ENABLE_INSN_P (785)"
+ "jmp\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bsr12"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3866)
+ (const_int 0))
+ (match_dup 0)
+ (pc)))
+ (set (reg:SI 17)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3868))
+ (set (reg:SI 133)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3869))]
+ "CGEN_ENABLE_INSN_P (786)"
+ "bsr\\t%l0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bsr24"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3862)
+ (const_int 0))
+ (match_dup 0)
+ (pc)))
+ (set (reg:SI 17)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3864))
+ (set (reg:SI 133)
+ (unspec:SI [
+ (match_dup 0)
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3865))]
+ "CGEN_ENABLE_INSN_P (787)"
+ "bsr\\t%l0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bne"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3870)
+ (const_int 0))
+ (match_dup 2)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (788)"
+ "bne\\t%0,%1,%l2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_beq"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3872)
+ (const_int 0))
+ (match_dup 2)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (789)"
+ "beq\\t%0,%1,%l2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bgei"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_uint_4a1_immediate" "")
+ (match_operand:SI 2 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3874)
+ (const_int 0))
+ (match_dup 2)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (790)"
+ "bgei\\t%0,%1,%l2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_blti"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_uint_4a1_immediate" "")
+ (match_operand:SI 2 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3876)
+ (const_int 0))
+ (match_dup 2)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (791)"
+ "blti\\t%0,%1,%l2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bnei"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_uint_4a1_immediate" "")
+ (match_operand:SI 2 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3878)
+ (const_int 0))
+ (match_dup 2)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (792)"
+ "bnei\\t%0,%1,%l2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_beqi"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_uint_4a1_immediate" "")
+ (match_operand:SI 2 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3880)
+ (const_int 0))
+ (match_dup 2)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (793)"
+ "beqi\\t%0,%1,%l2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bnez"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3882)
+ (const_int 0))
+ (match_dup 1)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (794)"
+ "bnez\\t%0,%l1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_beqz"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3884)
+ (const_int 0))
+ (match_dup 1)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (795)"
+ "beqz\\t%0,%l1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_bra"
+ [(set (pc)
+ (if_then_else (eq (unspec [
+ (match_operand:SI 0 "immediate_operand" "")
+ (reg:SI 32)
+ (reg:SI 42)
+ ] 3886)
+ (const_int 0))
+ (match_dup 0)
+ (pc)))]
+ "CGEN_ENABLE_INSN_P (796)"
+ "bra\\t%l0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_fsft"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ (reg:SI 18)
+ ] 3888))]
+ "CGEN_ENABLE_INSN_P (797)"
+ "fsft\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "fsft")])
+
+
+(define_insn "cgen_intrinsic_sll3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3890))]
+ "CGEN_ENABLE_INSN_P (798)"
+ "sll3\\t$0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_slli"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3892))]
+ "CGEN_ENABLE_INSN_P (799)"
+ "sll\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "shiftop" "operand2")])
+
+
+(define_insn "cgen_intrinsic_srli"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3894))]
+ "CGEN_ENABLE_INSN_P (800)"
+ "srl\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "shiftop" "operand2")])
+
+
+(define_insn "cgen_intrinsic_srai"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3896))]
+ "CGEN_ENABLE_INSN_P (801)"
+ "sra\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "shiftop" "operand2")])
+
+
+(define_insn "cgen_intrinsic_sll"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3898))]
+ "CGEN_ENABLE_INSN_P (802)"
+ "sll\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_srl"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3900))]
+ "CGEN_ENABLE_INSN_P (803)"
+ "srl\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_sra"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3902))]
+ "CGEN_ENABLE_INSN_P (804)"
+ "sra\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_xor3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
+ ] 3904))]
+ "CGEN_ENABLE_INSN_P (805)"
+ "xor3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_and3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
+ ] 3906))]
+ "CGEN_ENABLE_INSN_P (806)"
+ "and3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_or3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
+ ] 3908))]
+ "CGEN_ENABLE_INSN_P (807)"
+ "or3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_nor"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3910))]
+ "CGEN_ENABLE_INSN_P (808)"
+ "nor\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_xor"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3912))]
+ "CGEN_ENABLE_INSN_P (809)"
+ "xor\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_and"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3914))]
+ "CGEN_ENABLE_INSN_P (810)"
+ "and\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_or"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3916))]
+ "CGEN_ENABLE_INSN_P (811)"
+ "or\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_sltu3x"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
+ ] 3918))]
+ "CGEN_ENABLE_INSN_P (812)"
+ "sltu3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_slt3x"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "cgen_h_sint_16a1_immediate" "")
+ ] 3920))]
+ "CGEN_ENABLE_INSN_P (813)"
+ "slt3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_add3x"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "cgen_h_sint_16a1_immediate" "")
+ ] 3922))]
+ "CGEN_ENABLE_INSN_P (814)"
+ "add3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_sl2ad3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3924))]
+ "CGEN_ENABLE_INSN_P (815)"
+ "sl2ad3\\t$0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_sl1ad3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3926))]
+ "CGEN_ENABLE_INSN_P (816)"
+ "sl1ad3\\t$0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "int2")])
+
+
+(define_insn "cgen_intrinsic_sltu3i"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3928))]
+ "CGEN_ENABLE_INSN_P (817)"
+ "sltu3\\t$0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_slt3i"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
+ ] 3930))]
+ "CGEN_ENABLE_INSN_P (818)"
+ "slt3\\t$0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_sltu3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3932))]
+ "CGEN_ENABLE_INSN_P (819)"
+ "sltu3\\t$0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_slt3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3934))]
+ "CGEN_ENABLE_INSN_P (820)"
+ "slt3\\t$0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_neg"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3936))]
+ "CGEN_ENABLE_INSN_P (821)"
+ "neg\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_sbvck3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3938))]
+ "CGEN_ENABLE_INSN_P (822)"
+ "sbvck3\\t$0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "advck")])
+
+
+(define_insn "cgen_intrinsic_sub"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3940))]
+ "CGEN_ENABLE_INSN_P (823)"
+ "sub\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_advck3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3942))]
+ "CGEN_ENABLE_INSN_P (824)"
+ "advck3\\t$0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "advck")])
+
+
+(define_insn "cgen_intrinsic_add3i"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
+ (reg:SI 15)
+ ] 3944))]
+ "CGEN_ENABLE_INSN_P (825)"
+ "add3\\t%0,$sp,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_add"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "cgen_h_sint_6a1_immediate" "")
+ ] 3946))]
+ "CGEN_ENABLE_INSN_P (826)"
+ "add\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_add3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3948))]
+ "CGEN_ENABLE_INSN_P (827)"
+ "add3\\t%0,%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_movh"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
+ ] 3950))]
+ "CGEN_ENABLE_INSN_P (828)"
+ "movh\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_movu16"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
+ ] 3952))]
+ "CGEN_ENABLE_INSN_P (829)"
+ "movu\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_movu24"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_uint_24a1_immediate" "")
+ ] 3954))]
+ "CGEN_ENABLE_INSN_P (830)"
+ "movu\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_movi8"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_sint_8a1_immediate" "")
+ ] 3958))]
+ "CGEN_ENABLE_INSN_P (831)"
+ "mov\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_movi16"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ ] 3956))]
+ "CGEN_ENABLE_INSN_P (832)"
+ "mov\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_mov"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3960))]
+ "CGEN_ENABLE_INSN_P (833)"
+ "mov\\t%0,%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_ssarb"
+ [(set (reg:SI 18)
+ (unspec:SI [
+ (match_operand:SI 0 "cgen_h_sint_2a1_immediate" "")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 3962))
+ (set (reg:SI 140)
+ (unspec:SI [
+ (match_dup 0)
+ (match_dup 1)
+ ] 3963))]
+ "CGEN_ENABLE_INSN_P (834)"
+ "ssarb\\t%0(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "ssarb")])
+
+
+(define_insn "cgen_intrinsic_extuh"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ ] 3964))]
+ "CGEN_ENABLE_INSN_P (835)"
+ "extuh\\t%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_extub"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ ] 3966))]
+ "CGEN_ENABLE_INSN_P (836)"
+ "extub\\t%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_exth"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ ] 3968))]
+ "CGEN_ENABLE_INSN_P (837)"
+ "exth\\t%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_extb"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ ] 3970))]
+ "CGEN_ENABLE_INSN_P (838)"
+ "extb\\t%1"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lw24"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_uint_22a4_immediate" "")
+ (mem:SI (scratch:SI))
+ ] 3972))]
+ "CGEN_ENABLE_INSN_P (839)"
+ "lw\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_sw24"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_uint_22a4_immediate" "")
+ ] 3974))]
+ "CGEN_ENABLE_INSN_P (840)"
+ "sw\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lhu16"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 3976))]
+ "CGEN_ENABLE_INSN_P (841)"
+ "lhu\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lbu16"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 3978))]
+ "CGEN_ENABLE_INSN_P (842)"
+ "lbu\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lw16"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 3980))]
+ "CGEN_ENABLE_INSN_P (843)"
+ "lw\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lh16"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 3982))]
+ "CGEN_ENABLE_INSN_P (844)"
+ "lh\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lb16"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 3984))]
+ "CGEN_ENABLE_INSN_P (845)"
+ "lb\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_sw16"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3986))]
+ "CGEN_ENABLE_INSN_P (846)"
+ "sw\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_sh16"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3988))]
+ "CGEN_ENABLE_INSN_P (847)"
+ "sh\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_sb16"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 3990))]
+ "CGEN_ENABLE_INSN_P (848)"
+ "sb\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lhu_tp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_uint_6a2_immediate" "")
+ (reg:SI 13)
+ (mem:SI (scratch:SI))
+ ] 3992))]
+ "CGEN_ENABLE_INSN_P (849)"
+ "lhu\\t%0,%1($tp)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lbu_tp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_uint_7a1_immediate" "")
+ (reg:SI 13)
+ (mem:SI (scratch:SI))
+ ] 3994))]
+ "CGEN_ENABLE_INSN_P (850)"
+ "lbu\\t%0,%1($tp)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lw_tp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
+ (reg:SI 13)
+ (mem:SI (scratch:SI))
+ ] 3996))]
+ "CGEN_ENABLE_INSN_P (851)"
+ "lw\\t%0,%1($tp)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lh_tp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_uint_6a2_immediate" "")
+ (reg:SI 13)
+ (mem:SI (scratch:SI))
+ ] 3998))]
+ "CGEN_ENABLE_INSN_P (852)"
+ "lh\\t%0,%1($tp)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lb_tp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_uint_7a1_immediate" "")
+ (reg:SI 13)
+ (mem:SI (scratch:SI))
+ ] 4000))]
+ "CGEN_ENABLE_INSN_P (853)"
+ "lb\\t%0,%1($tp)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_sw_tp"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "t")
+ (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
+ (reg:SI 13)
+ ] 4002))]
+ "CGEN_ENABLE_INSN_P (854)"
+ "sw\\t%0,%1($tp)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_sh_tp"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "t")
+ (match_operand:SI 1 "cgen_h_uint_6a2_immediate" "")
+ (reg:SI 13)
+ ] 4004))]
+ "CGEN_ENABLE_INSN_P (855)"
+ "sh\\t%0,%1($tp)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_sb_tp"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "t")
+ (match_operand:SI 1 "cgen_h_uint_7a1_immediate" "")
+ (reg:SI 13)
+ ] 4006))]
+ "CGEN_ENABLE_INSN_P (856)"
+ "sb\\t%0,%1($tp)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lw_sp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
+ (reg:SI 15)
+ (mem:SI (scratch:SI))
+ ] 4008))]
+ "CGEN_ENABLE_INSN_P (857)"
+ "lw\\t%0,%1($sp)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_sw_sp"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
+ (reg:SI 15)
+ ] 4010))]
+ "CGEN_ENABLE_INSN_P (858)"
+ "sw\\t%0,%1($sp)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lhu"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 4012))]
+ "CGEN_ENABLE_INSN_P (859)"
+ "lhu\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lbu"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 4014))]
+ "CGEN_ENABLE_INSN_P (860)"
+ "lbu\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lw"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 4016))]
+ "CGEN_ENABLE_INSN_P (861)"
+ "lw\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lh"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 4018))]
+ "CGEN_ENABLE_INSN_P (862)"
+ "lh\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lb"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 4020))]
+ "CGEN_ENABLE_INSN_P (863)"
+ "lb\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "2")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_sw"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 4022))]
+ "CGEN_ENABLE_INSN_P (864)"
+ "sw\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_sh"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 4024))]
+ "CGEN_ENABLE_INSN_P (865)"
+ "sh\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_sb"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 4026))]
+ "CGEN_ENABLE_INSN_P (866)"
+ "sb\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_dsp1"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "cgen_h_uint_20a1_immediate" "")
+ ] 4028))]
+ "CGEN_ENABLE_INSN_P (867)"
+ "dsp1\\t%1,%2"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_dsp0"
+ [(unspec_volatile [
+ (match_operand:SI 0 "cgen_h_uint_24a1_immediate" "")
+ ] 4030)]
+ "CGEN_ENABLE_INSN_P (868)"
+ "dsp0\\t%0"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_dsp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ (match_operand:SI 3 "cgen_h_uint_16a1_immediate" "")
+ ] 4032))]
+ "CGEN_ENABLE_INSN_P (869)"
+ "dsp\\t%1,%2,%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_uci"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ (match_operand:SI 3 "cgen_h_uint_16a1_immediate" "")
+ ] 4034))]
+ "CGEN_ENABLE_INSN_P (870)"
+ "uci\\t%1,%2,%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lhucpm1"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 31)
+ (reg:SI 30)
+ (mem:SI (scratch:SI))
+ ] 4036))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 31)
+ (reg:SI 30)
+ (mem:SI (scratch:SI))
+ ] 4038))]
+ "CGEN_ENABLE_INSN_P (871)"
+ "lhucpm1\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lbucpm1"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 31)
+ (reg:SI 30)
+ (mem:SI (scratch:SI))
+ ] 4040))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 31)
+ (reg:SI 30)
+ (mem:SI (scratch:SI))
+ ] 4042))]
+ "CGEN_ENABLE_INSN_P (872)"
+ "lbucpm1\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lhucpm0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 29)
+ (reg:SI 28)
+ (mem:SI (scratch:SI))
+ ] 4044))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 29)
+ (reg:SI 28)
+ (mem:SI (scratch:SI))
+ ] 4046))]
+ "CGEN_ENABLE_INSN_P (873)"
+ "lhucpm0\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lbucpm0"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (reg:SI 29)
+ (reg:SI 28)
+ (mem:SI (scratch:SI))
+ ] 4048))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (reg:SI 29)
+ (reg:SI 28)
+ (mem:SI (scratch:SI))
+ ] 4050))]
+ "CGEN_ENABLE_INSN_P (874)"
+ "lbucpm0\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_lhucpa"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (mem:SI (scratch:SI))
+ ] 4052))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (mem:SI (scratch:SI))
+ ] 4054))]
+ "CGEN_ENABLE_INSN_P (875)"
+ "lhucpa\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lbucpa"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 2 "general_operand" "1")
+ (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
+ (mem:SI (scratch:SI))
+ ] 4056))
+ (set (match_operand:SI 1 "nonimmediate_operand" "=r")
+ (unspec:SI [
+ (match_dup 2)
+ (match_dup 3)
+ (mem:SI (scratch:SI))
+ ] 4058))]
+ "CGEN_ENABLE_INSN_P (876)"
+ "lbucpa\\t%0,(%2+),%3"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "load")])
+
+
+(define_insn "cgen_intrinsic_lhucp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 4060))]
+ "CGEN_ENABLE_INSN_P (877)"
+ "lhucp\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lhcp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 4062))]
+ "CGEN_ENABLE_INSN_P (878)"
+ "lhcp\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_shcp"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "em")
+ (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 4064))]
+ "CGEN_ENABLE_INSN_P (879)"
+ "shcp\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lbucp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 4066))]
+ "CGEN_ENABLE_INSN_P (880)"
+ "lbucp\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_lbcp"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
+ (unspec:SI [
+ (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ (mem:SI (scratch:SI))
+ ] 4068))]
+ "CGEN_ENABLE_INSN_P (881)"
+ "lbcp\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_sbcp"
+ [(set (mem:SI (scratch:SI))
+ (unspec:SI [
+ (match_operand:SI 0 "general_operand" "em")
+ (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 4070))]
+ "CGEN_ENABLE_INSN_P (882)"
+ "sbcp\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "store")])
+
+
+(define_insn "cgen_intrinsic_casw3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ (match_operand:SI 3 "general_operand" "r")
+ ] 4072))]
+ "CGEN_ENABLE_INSN_P (883)"
+ "casw3\\t%1,%2,(%3)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_cash3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ (match_operand:SI 3 "general_operand" "r")
+ ] 4074))]
+ "CGEN_ENABLE_INSN_P (884)"
+ "cash3\\t%1,%2,(%3)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_casb3"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_operand" "r")
+ (match_operand:SI 3 "general_operand" "r")
+ ] 4076))]
+ "CGEN_ENABLE_INSN_P (885)"
+ "casb3\\t%1,%2,(%3)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_prefd"
+ [(unspec_volatile [
+ (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
+ (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
+ (match_operand:SI 2 "general_operand" "r")
+ ] 4078)]
+ "CGEN_ENABLE_INSN_P (886)"
+ "pref\\t%0,%1(%2)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "4")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_pref"
+ [(unspec_volatile [
+ (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 4080)]
+ "CGEN_ENABLE_INSN_P (887)"
+ "pref\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_ldcb_r"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ (unspec_volatile:SI [
+ (match_operand:SI 1 "general_operand" "r")
+ ] 4082))]
+ "CGEN_ENABLE_INSN_P (888)"
+ "ldcb\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "3")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
+
+(define_insn "cgen_intrinsic_stcb_r"
+ [(unspec_volatile [
+ (match_operand:SI 0 "general_operand" "r")
+ (match_operand:SI 1 "general_operand" "r")
+ ] 4084)]
+ "CGEN_ENABLE_INSN_P (889)"
+ "stcb\\t%0,(%1)"
+ [(set_attr "may_trap" "no")
+ (set_attr "latency" "0")
+ (set_attr "length" "2")
+ (set_attr "slot" "core")
+ (set_attr "slots" "core")
+ (set_attr "stall" "none")])
+
--- /dev/null
+#undef __section
+#define __section(_secname) __attribute__((section(#_secname)))
+#undef mep_nop
+#define mep_nop() __asm__ volatile ("nop")
+
+#pragma GCC coprocessor available $c0...$c31
+#pragma GCC coprocessor call_saved $c6...$c7
+
+#include <intrinsics.h>
--- /dev/null
+; Insns introduced for the MeP-c5 core
+;
+
+(dnf f-c5n4 "extended field" (all-mep-core-isas) 16 4)
+(dnf f-c5n5 "extended field" (all-mep-core-isas) 20 4)
+(dnf f-c5n6 "extended field" (all-mep-core-isas) 24 4)
+(dnf f-c5n7 "extended field" (all-mep-core-isas) 28 4)
+(dnf f-rl5 "register l c5" (all-mep-core-isas) 20 4)
+(df f-12s20 "extended field" (all-mep-core-isas) 20 12 INT #f #f)
+
+(dnop rl5 "register Rl c5" (all-mep-core-isas) h-gpr f-rl5)
+(dnop cdisp12 "copro addend (12 bits)" (all-mep-core-isas) h-sint f-12s20)
+
+(dnci stcb_r "store in control bus space" (VOLATILE (MACH c5))
+ "stcb $rn,($rma)"
+ (+ MAJ_7 rn rma (f-sub4 12))
+ (c-call VOID "do_stcb" rn (and rma #xffff))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-stcb))))
+
+(dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3))
+ "ldcb $rn,($rma)"
+ (+ MAJ_7 rn rma (f-sub4 13))
+ (set rn (c-call SI "do_ldcb" (and rma #xffff)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-ldcb)
+ (unit u-exec)
+ (unit u-ldcb-gpr (out loadreg rn)))))
+
+(dnci pref "cache prefetch" ((MACH c5) VOLATILE)
+ "pref $cimm4,($rma)"
+ (+ MAJ_7 cimm4 rma (f-sub4 5))
+ (sequence ()
+ (c-call VOID "check_option_dcache" pc)
+ (c-call VOID "do_cache_prefetch" cimm4 rma pc))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci prefd "cache prefetch" ((MACH c5) VOLATILE)
+ "pref $cimm4,$sdisp16($rma)"
+ (+ MAJ_15 cimm4 rma (f-sub4 3) sdisp16)
+ (sequence ()
+ (c-call VOID "check_option_dcache" pc)
+ (c-call VOID "do_cache_prefetch" cimm4 (add INT rma (ext SI sdisp16)) pc))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+ "casb3 $rl5,$rn,($rm)"
+ (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x0))
+ (sequence ()
+ (c-call VOID "do_casb3" (index-of rl5) rn rm pc)
+ (set rl5 rl5)
+ )
+ ((mep (unit u-use-gpr (in usereg rl5))
+ (unit u-load-gpr (out loadreg rl5))
+ (unit u-exec))))
+
+(dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+ "cash3 $rl5,$rn,($rm)"
+ (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x1))
+ (sequence ()
+ (c-call VOID "do_cash3" (index-of rl5) rn rm pc)
+ (set rl5 rl5)
+ )
+ ((mep (unit u-use-gpr (in usereg rl5))
+ (unit u-load-gpr (out loadreg rl5))
+ (unit u-exec))))
+
+(dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+ "casw3 $rl5,$rn,($rm)"
+ (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x2))
+ (sequence ()
+ (c-call VOID "do_casw3" (index-of rl5) rn rm pc)
+ (set rl5 rl5)
+ )
+ ((mep (unit u-use-gpr (in usereg rl5))
+ (unit u-load-gpr (out loadreg rl5))
+ (unit u-exec))))
+
+
+
+(dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "sbcp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 0) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
+ (set (mem QI (add rma (ext SI cdisp12))) (and crn #xff)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "lbcp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 4) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem QI (add rma (ext SI cdisp12))))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "lbucp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 12) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem QI (add rma (ext SI cdisp12))))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+
+(dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "shcp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 1) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
+ (set (mem HI (add rma (ext SI cdisp12))) (and crn #xffff)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "lhcp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 5) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem HI (add rma (ext SI cdisp12))))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "lhucp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 13) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem HI (add rma (ext SI cdisp12))))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+
+(dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
+ "lbucpa $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xC) (f-ext62 #x0) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem QI rma)))
+ (set rma (add rma cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
+ "lhucpa $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xD) (f-ext62 #x0) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+ (set rma (add rma (ext SI cdisp10a2))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbucpm0 "lbucpm0" (OPTIONAL_CP_INSN (MACH c5))
+ "lbucpm0 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x2) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem QI rma)))
+ (set rma (mod0 cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhucpm0 "lhucpm0" (OPTIONAL_CP_INSN (MACH c5))
+ "lhucpm0 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x2) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+ (set rma (mod0 cdisp10a2)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbucpm1 "lbucpm1" (OPTIONAL_CP_INSN (MACH c5))
+ "lbucpm1 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x3) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem QI rma)))
+ (set rma (mod1 cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhucpm1 "lhucpm1" (OPTIONAL_CP_INSN (MACH c5))
+ "lhucpm1 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x3) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+ (set rma (mod1 cdisp10a2)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci uci "uci" ((MACH c5) VOLATILE)
+ "uci $rn,$rm,$uimm16"
+ (+ MAJ_15 rn rm (f-sub4 2) simm16)
+ (set rn (c-call SI "do_UCI" rn rm (zext SI uimm16) pc))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnf f-c5-rnm "register n/m" (all-mep-isas) 4 8)
+(dnf f-c5-rm "register m" (all-mep-isas) 8 4)
+(df f-c5-16u16 "general 16-bit u-val" (all-mep-isas) 16 16 UINT #f #f)
+
+(dnmf f-c5-rmuimm20 "20-bit immediate in Rm/Imm16" (all-mep-isas) UINT
+ (f-c5-rm f-c5-16u16)
+ (sequence () ; insert
+ (set (ifield f-c5-rm) (srl (ifield f-c5-rmuimm20) 16))
+ (set (ifield f-c5-16u16) (and (ifield f-c5-rmuimm20) #xffff))
+ )
+ (sequence () ; extract
+ (set (ifield f-c5-rmuimm20) (or (ifield f-c5-16u16)
+ (sll (ifield f-c5-rm) 16)))
+ )
+ )
+(dnop c5rmuimm20 "20-bit immediate in rm and imm16" (all-mep-core-isas) h-uint f-c5-rmuimm20)
+
+(dnmf f-c5-rnmuimm24 "24-bit immediate in Rm/Imm16" (all-mep-isas) UINT
+ (f-c5-rnm f-c5-16u16)
+ (sequence () ; insert
+ (set (ifield f-c5-rnm) (srl (ifield f-c5-rnmuimm24) 16))
+ (set (ifield f-c5-16u16) (and (ifield f-c5-rnmuimm24) #xffff))
+ )
+ (sequence () ; extract
+ (set (ifield f-c5-rnmuimm24) (or (ifield f-c5-16u16)
+ (sll (ifield f-c5-rnm) 16)))
+ )
+ )
+(dnop c5rnmuimm24 "24-bit immediate in rn, rm, and imm16" (all-mep-core-isas) h-uint f-c5-rnmuimm24)
+
+(dnci dsp "dsp" ((MACH c5) VOLATILE)
+ "dsp $rn,$rm,$uimm16"
+ (+ MAJ_15 rn rm (f-sub4 0) uimm16)
+ (set rn (c-call SI "do_DSP" rn rm (zext SI uimm16) pc))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci dsp0 "dsp0" ((MACH c5) VOLATILE NO-DIS ALIAS)
+ "dsp0 $c5rnmuimm24"
+ (+ MAJ_15 c5rnmuimm24 (f-sub4 0))
+ (c-call VOID "do_DSP" (zext SI c5rnmuimm24) pc)
+ ((mep (unit u-exec))))
+
+(dnci dsp1 "dsp1" ((MACH c5) VOLATILE NO-DIS ALIAS)
+ "dsp1 $rn,$c5rmuimm20"
+ (+ MAJ_15 rn (f-sub4 0) c5rmuimm20)
+ (set rn (c-call SI "do_DSP" rn (zext SI c5rmuimm20) pc))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
--- /dev/null
+; Toshiba MeP Media Engine architecture description. -*- Scheme -*-
+; Copyright (C) 2001, 2002, 2003, 2004, 2005 Red Hat, Inc.
+; This file is part of CGEN.
+; See file COPYING.CGEN for details.
+
+(include "simplify.inc")
+
+(define-pmacro isa-enum ()
+ (isas mep
+; begin-isa-enum
+ ext_core1 ext_cop1_16 ext_cop1_32 ext_cop1_48 ext_cop1_64
+; end-isa-enum
+ )
+)
+
+(define-arch
+ (name mep)
+ (comment "Toshiba MeP Media Engine")
+ (insn-lsb0? #f) ;; work around cgen limitation
+ (machs mep h1 c5)
+ isa-enum
+)
+
+(define-isa
+ (name mep)
+ (comment "MeP core instruction set")
+ (default-insn-word-bitsize 32)
+ (default-insn-bitsize 32)
+ (base-insn-bitsize 32)
+)
+
+; begin-isas
+(define-isa
+ (name ext_core1)
+ (comment "MeP core extension instruction set")
+ (default-insn-word-bitsize 32)
+ (default-insn-bitsize 32)
+ (base-insn-bitsize 32)
+)
+
+(define-isa
+ (name ext_cop1_16)
+ (comment "MeP coprocessor instruction set")
+ (default-insn-word-bitsize 32)
+ (default-insn-bitsize 32)
+ (base-insn-bitsize 32)
+)
+
+(define-isa
+ (name ext_cop1_32)
+ (comment "MeP coprocessor instruction set")
+ (default-insn-word-bitsize 32)
+ (default-insn-bitsize 32)
+ (base-insn-bitsize 32)
+)
+
+(define-isa
+ (name ext_cop1_48)
+ (comment "MeP coprocessor instruction set")
+ (default-insn-word-bitsize 32)
+ (default-insn-bitsize 32)
+ (base-insn-bitsize 32)
+)
+
+(define-isa
+ (name ext_cop1_64)
+ (comment "MeP coprocessor instruction set")
+ (default-insn-word-bitsize 32)
+ (default-insn-bitsize 32)
+ (base-insn-bitsize 32)
+)
+
+(define-pmacro all-mep-isas () (ISA mep,ext_core1,ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64))
+
+(define-pmacro all-mep-core-isas () (ISA mep,ext_core1,ext_cop1_32))
+
+(define-pmacro all-core-isa-list () mep,ext_core1)
+; end-isas
+
+(define-cpu
+ (name mepf)
+ (comment "MeP family")
+ (endian either)
+ (insn-chunk-bitsize 16)
+ (word-bitsize 32)
+)
+
+(define-mach
+ (name mep)
+ (comment "MeP media engine")
+ (cpu mepf)
+ isa-enum
+)
+
+(define-mach
+ (name h1)
+ (comment "H1 media engine")
+ (cpu mepf)
+ isa-enum
+)
+
+(define-mach
+ (name c5)
+ (comment "C5 media engine")
+ (cpu mepf)
+ isa-enum
+)
+
+(define-model
+ (name mep)
+ (comment "MeP media engine processor")
+ (mach c5) ; mach gets changed by MeP-Integrator
+
+ (unit u-exec "execution unit" ()
+ 1 1 ; issue done
+ () () () ())
+
+ ; Branch unit
+ (unit u-branch "Branch Unit" ()
+ 0 0 ; issue done
+ () ; state
+ () ; inputs
+ ((pc)) ; outputs
+ () ; profile action (default)
+ )
+
+ ; Multiply unit
+ (unit u-multiply "Multiply Unit" ()
+ 0 0 ; issue done
+ () ; state
+ () ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+
+ ; Divide unit
+ (unit u-divide "Divide Unit" ()
+ 0 0 ; issue done
+ () ; state
+ () ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+
+ ; Stcb unit
+ (unit u-stcb "stcb Unit" ()
+ 0 0 ; issue done
+ () ; state
+ () ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+
+ ; Ldcb unit
+ (unit u-ldcb "ldcb Unit" ()
+ 0 0 ; issue done
+ () ; state
+ () ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+
+ ; Load gpr unit
+ (unit u-load-gpr "Load into GPR Unit" ()
+ 0 0 ; issue done
+ () ; state
+ () ; inputs
+ ((loadreg INT -1)) ; outputs
+ () ; profile action (default)
+ )
+
+ (unit u-ldcb-gpr "Ldcb into GPR Unit" ()
+ 0 0 ; issue done
+ () ; state
+ () ; inputs
+ ((loadreg INT -1)) ; outputs
+ () ; profile action (default)
+ )
+
+ ; Multiply into GPR unit
+ (unit u-mul-gpr "Multiply into GPR Unit" ()
+ 0 0 ; issue done
+ () ; state
+ () ; inputs
+ ((resultreg INT -1)) ; outputs
+ () ; profile action (default)
+ )
+
+ ; Use gpr unit -- stalls if GPR not ready
+ (unit u-use-gpr "Use GPR Unit" ()
+ 0 0 ; issue done
+ () ; state
+ ((usereg INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+
+ ; Use ctrl-reg unit -- stalls if CTRL-REG not ready
+ (unit u-use-ctrl-reg "Use CTRL-REG Unit" ()
+ 0 0 ; issue done
+ () ; state
+ ((usereg INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+
+ ; Store ctrl-reg unit -- stalls if CTRL-REG not ready
+ (unit u-store-ctrl-reg "Store CTRL-REG Unit" ()
+ 0 0 ; issue done
+ () ; state
+ () ; inputs
+ ((storereg INT -1)) ; outputs
+ () ; profile action (default)
+ )
+)
+\f
+; Hardware elements.
+
+(dnh h-pc "program counter" (PC PROFILE all-mep-isas) (pc) () () ())
+
+(define-hardware
+ (name h-gpr)
+ (comment "General purpose registers")
+ (attrs all-mep-isas CACHE-ADDR PROFILE)
+ (type register SI (16))
+ (indices keyword "$"
+ (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5)
+ ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11)
+ ; "$8" is the preferred name for register 8, but "$tp", "$gp"
+ ; and "$sp" are preferred for their respective registers.
+ (fp 8) (tp 13) (gp 14) (sp 15)
+ ("12" 12) ("13" 13) ("14" 14) ("15" 15)))
+)
+
+(define-hardware
+ (name h-csr)
+ (comment "Control/special registers")
+ (attrs all-mep-isas PROFILE)
+ (type register SI (32))
+ (indices keyword "$"
+ ((pc 0) (lp 1) (sar 2) (rpb 4) (rpe 5) (rpc 6)
+ (hi 7) (lo 8) (mb0 12) (me0 13) (mb1 14) (me1 15)
+ (psw 16) (id 17) (tmp 18) (epc 19) (exc 20) (cfg 21)
+ (npc 23) (dbg 24) (depc 25) (opt 26) (rcfg 27) (ccfg 28)
+; begin-extra-csr-registers
+ (vid 22)
+; end-extra-csr-registers
+ ))
+ (get (index) (c-call SI "cgen_get_csr_value" index))
+ (set (index newval) (c-call VOID "cgen_set_csr_value" index newval))
+)
+
+(define-pmacro (-reg-pair n) ((.sym n) n))
+(define-hardware
+ (name h-cr64)
+ (comment "64-bit coprocessor registers")
+ (attrs all-mep-isas)
+ ; This assumes that the data path of the co-pro is 64 bits.
+ (type register DI (32))
+ (indices keyword "$c" (.map -reg-pair (.iota 32)))
+ (set (index newval) (c-call VOID "h_cr64_queue_set" index newval))
+)
+(define-hardware
+ (name h-cr64-w)
+ (comment "64-bit coprocessor registers, pending writes")
+ (attrs all-mep-isas)
+ ; This assumes that the data path of the co-pro is 64 bits.
+ (type register DI (32))
+)
+
+(define-hardware
+ (name h-cr)
+ (comment "32-bit coprocessor registers")
+ (attrs all-mep-isas VIRTUAL)
+ (type register SI (32))
+ (indices keyword "$c" (.map -reg-pair (.iota 32)))
+ (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval)))
+ (get (index) (trunc SI (c-call DI "h_cr64_get" index)))
+)
+
+;; Given a coprocessor control register number N, expand to a
+;; name/index pair: ($ccrN N)
+(define-pmacro (-ccr-reg-pair n) ((.sym "$ccr" n) n))
+
+(define-hardware
+ (name h-ccr)
+ (comment "Coprocessor control registers")
+ (attrs all-mep-isas)
+ (type register SI (64))
+ (indices keyword "" (.map -ccr-reg-pair (.iota 64)))
+ (set (index newval) (c-call VOID "h_ccr_queue_set" index newval))
+)
+(define-hardware
+ (name h-ccr-w)
+ (comment "Coprocessor control registers, pending writes")
+ (attrs all-mep-isas)
+ (type register SI (64))
+)
+
+\f
+; Instruction fields. Bit numbering reversed.
+
+; Conventions:
+;
+; N = number of bits in value
+; A = alignment (2 or 4, omit for 1)
+; B = leftmost (i.e. closest to zero) bit position
+;
+; -- Generic Fields (f-*) --
+; N number of bits in *value* (1-24)
+; [us] signed vs unsigned
+; B position of left-most bit (4-16)
+; aA opt. alignment (2=drop 1 lsb, 4=drop 2 lsbs, etc)
+; n opt. for noncontiguous fields
+; f-foo-{hi,lo} msb/lsb parts of field f-foo
+;
+; -- Operands --
+; pcrelNaA PC-relative branch target (signed)
+; pcabsNaA Absolute branch target (unsigned)
+;
+; [us]dispNaA [un]signed displacement
+; [us]immN [un]signed immediate value
+; addrNaA absolute address (unsigned)
+;
+; Additional prefixes may be used for special cases.
+
+(dnf f-major "major opcode" (all-mep-core-isas) 0 4)
+
+(dnf f-rn "register n" (all-mep-core-isas) 4 4)
+(dnf f-rn3 "register 0-7" (all-mep-core-isas) 5 3)
+(dnf f-rm "register m" (all-mep-core-isas) 8 4)
+(dnf f-rl "register l" (all-mep-core-isas) 12 4)
+(dnf f-sub2 "sub opcode (2 bits)" (all-mep-core-isas) 14 2)
+(dnf f-sub3 "sub opcode (3 bits)" (all-mep-core-isas) 13 3)
+(dnf f-sub4 "sub opcode (4 bits)" (all-mep-core-isas) 12 4)
+(dnf f-ext "extended field" (all-mep-core-isas) 16 8)
+(dnf f-ext4 "extended field 16:4" (all-mep-core-isas) 16 4)
+(dnf f-ext62 "extended field 20:2" (all-mep-core-isas) 20 2)
+(dnf f-crn "copro register n" (all-mep-core-isas) 4 4)
+
+(df f-csrn-hi "cr hi 1u15" (all-mep-core-isas) 15 1 UINT #f #f)
+(df f-csrn-lo "cr lo 4u8" (all-mep-core-isas) 8 4 UINT #f #f)
+(define-multi-ifield
+ (name f-csrn)
+ (comment "control reg")
+ (attrs all-mep-core-isas)
+ (mode UINT)
+ (subfields f-csrn-hi f-csrn-lo)
+ (insert (sequence ()
+ (set (ifield f-csrn-lo) (and (ifield f-csrn) #xf))
+ (set (ifield f-csrn-hi) (srl (ifield f-csrn) 4))))
+ (extract (set (ifield f-csrn)
+ (or (sll (ifield f-csrn-hi) 4) (ifield f-csrn-lo))))
+ )
+
+(df f-crnx-hi "crx hi 1u28" (all-mep-core-isas) 28 1 UINT #f #f)
+(df f-crnx-lo "crx lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f)
+(define-multi-ifield
+ (name f-crnx)
+ (comment "copro register n (0-31)")
+ (attrs all-mep-core-isas)
+ (mode UINT)
+ (subfields f-crnx-hi f-crnx-lo)
+ (insert (sequence ()
+ (set (ifield f-crnx-lo) (and (ifield f-crnx) #xf))
+ (set (ifield f-crnx-hi) (srl (ifield f-crnx) 4))))
+ (extract (set (ifield f-crnx)
+ (or (sll (ifield f-crnx-hi) 4) (ifield f-crnx-lo))))
+ )
+
+; Miscellaneous fields.
+
+(define-pmacro (dnfb n)
+ (dnf (.sym f- n) (.str "bit " n) (all-mep-isas) n 1))
+
+; Define small fields used throughout the instruction set description.
+; Each field (eg. `f-N') is at single bit field at position N.
+
+(dnfb 0)
+(dnfb 1)
+(dnfb 2)
+(dnfb 3)
+(dnfb 4)
+(dnfb 5)
+(dnfb 6)
+(dnfb 7)
+(dnfb 8)
+(dnfb 9)
+(dnfb 10)
+(dnfb 11)
+(dnfb 12)
+(dnfb 13)
+(dnfb 14)
+(dnfb 15)
+(dnfb 16)
+(dnfb 17)
+(dnfb 18)
+(dnfb 19)
+(dnfb 20)
+(dnfb 21)
+(dnfb 22)
+(dnfb 23)
+(dnfb 24)
+(dnfb 25)
+(dnfb 26)
+(dnfb 27)
+(dnfb 28)
+(dnfb 29)
+(dnfb 30)
+(dnfb 31)
+
+; Branch/Jump target addresses
+
+(df f-8s8a2 "pc-rel addr (8 bits)" (all-mep-core-isas PCREL-ADDR) 8 7 INT
+ ((value pc) (sra SI (sub SI value pc) 1))
+ ((value pc) (add SI (sll SI value 1) pc)))
+
+(df f-12s4a2 "pc-rel addr (12 bits)" (all-mep-core-isas PCREL-ADDR) 4 11 INT
+ ((value pc) (sra SI (sub SI value pc) 1))
+ ((value pc) (add SI (sll SI value 1) pc)))
+
+(df f-17s16a2 "pc-rel addr (17 bits)" (all-mep-core-isas PCREL-ADDR) 16 16 INT
+ ((value pc) (sra SI (sub SI value pc) 1))
+ ((value pc) (add SI (sll SI value 1) pc)))
+
+(df f-24s5a2n-hi "24s5a2n hi 16s16" (all-mep-core-isas PCREL-ADDR) 16 16 INT #f #f)
+(df f-24s5a2n-lo "24s5a2n lo 7s5a2" (all-mep-core-isas PCREL-ADDR) 5 7 UINT #f #f)
+(define-multi-ifield
+ (name f-24s5a2n)
+ (comment "pc-rel addr (24 bits align 2)")
+ (attrs all-mep-core-isas PCREL-ADDR)
+ (mode INT)
+ (subfields f-24s5a2n-hi f-24s5a2n-lo)
+ (insert (sequence ()
+ (set (ifield f-24s5a2n)
+ (sub (ifield f-24s5a2n) pc))
+ (set (ifield f-24s5a2n-lo)
+ (srl (and (ifield f-24s5a2n) #xfe) 1))
+ (set (ifield f-24s5a2n-hi)
+ (sra INT (ifield f-24s5a2n) 8))))
+ (extract (set (ifield f-24s5a2n)
+ (add SI (or (sll (ifield f-24s5a2n-hi) 8)
+ (sll (ifield f-24s5a2n-lo) 1))
+ pc)))
+ )
+
+(df f-24u5a2n-hi "24u5a2n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
+(df f-24u5a2n-lo "24u5a2n lo 7u5a2" (all-mep-core-isas) 5 7 UINT #f #f)
+(define-multi-ifield
+ (name f-24u5a2n)
+ (comment "abs jump target (24 bits, alignment 2)")
+ (attrs all-mep-core-isas ABS-ADDR)
+ (mode UINT)
+ (subfields f-24u5a2n-hi f-24u5a2n-lo)
+ (insert (sequence ()
+ (set (ifield f-24u5a2n-lo)
+ (srl (and (ifield f-24u5a2n) #xff) 1))
+ (set (ifield f-24u5a2n-hi)
+ (srl (ifield f-24u5a2n) 8))
+ ))
+ (extract (set (ifield f-24u5a2n)
+ (or (sll (ifield f-24u5a2n-hi) 8)
+ (sll (ifield f-24u5a2n-lo) 1))))
+ )
+
+; Displacement fields.
+
+(df f-2u6 "SAR offset (2 bits)" (all-mep-core-isas) 6 2 UINT #f #f)
+(df f-7u9 "tp-rel b (7 bits)" (all-mep-core-isas) 9 7 UINT #f #f)
+(df f-7u9a2 "tp-rel h (7 bits)" (all-mep-core-isas) 9 6 UINT
+ ((value pc) (srl SI value 1))
+ ((value pc) (sll SI value 1)))
+(df f-7u9a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas) 9 5 UINT
+ ((value pc) (srl SI value 2))
+ ((value pc) (sll SI value 2)))
+(df f-16s16 "general 16-bit s-val" (all-mep-core-isas) 16 16 INT #f #f)
+
+; Immediate fields.
+
+(df f-2u10 "swi level (2 bits)" (all-mep-core-isas) 10 2 UINT #f #f)
+(df f-3u5 "bit offset (3 bits)" (all-mep-core-isas) 5 3 UINT #f #f)
+(df f-4u8 "bCC const (4 bits)" (all-mep-core-isas) 8 4 UINT #f #f)
+(df f-5u8 "slt & shifts (5 bits)" (all-mep-core-isas) 8 5 UINT #f #f)
+(df f-5u24 "clip immediate (5 bits)" (all-mep-core-isas) 24 5 UINT #f #f)
+(df f-6s8 "add immediate (6 bits)" (all-mep-core-isas) 8 6 INT #f #f)
+(df f-8s8 "add imm (8 bits)" (all-mep-core-isas) 8 8 INT #f #f)
+(df f-16u16 "general 16-bit u-val" (all-mep-core-isas) 16 16 UINT #f #f)
+(df f-12u16 "cmov fixed 1" (all-mep-core-isas) 16 12 UINT #f #f)
+(df f-3u29 "cmov fixed 2" (all-mep-core-isas) 29 3 UINT #f #f)
+
+
+; These are all for the coprocessor opcodes
+
+; The field is like IJKiiiiiii where I and J are toggled if K is set,
+; for compatibility with older cores.
+(define-pmacro (compute-cdisp10 val)
+ (cond SI
+ ((and SI (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x200)
+ (sub (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x400))
+ (else
+ (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)))
+ )
+ )
+(define-pmacro (extend-cdisp10 val)
+ (cond SI
+ ((and SI (compute-cdisp10 val) #x200)
+ (sub (and SI (compute-cdisp10 val) #x3ff) #x400))
+ (else
+ (and SI (compute-cdisp10 val) #x3ff))
+ )
+ )
+
+(df f-cdisp10 "cop imm10" (all-mep-core-isas) 22 10 INT
+ ((value pc) (extend-cdisp10 value))
+ ((value pc) (extend-cdisp10 value))
+ )
+
+; Non-contiguous fields.
+
+(df f-24u8a4n-hi "24u8a4n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
+(df f-24u8a4n-lo "24u8a4n lo 8u8a4" (all-mep-core-isas) 8 6 UINT #f #f)
+(define-multi-ifield
+ (name f-24u8a4n)
+ (comment "absolute 24-bit address")
+ (attrs all-mep-core-isas)
+ (mode UINT)
+ (subfields f-24u8a4n-hi f-24u8a4n-lo)
+ (insert (sequence ()
+ (set (ifield f-24u8a4n-hi) (srl (ifield f-24u8a4n) 8))
+ (set (ifield f-24u8a4n-lo) (srl (and (ifield f-24u8a4n) #xfc) 2))))
+ (extract (set (ifield f-24u8a4n)
+ (or (sll (ifield f-24u8a4n-hi) 8)
+ (sll (ifield f-24u8a4n-lo) 2))))
+ )
+
+(df f-24u8n-hi "24u8n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
+(df f-24u8n-lo "24u8n lo 8u8" (all-mep-core-isas) 8 8 UINT #f #f)
+(define-multi-ifield
+ (name f-24u8n)
+ (comment "24-bit constant")
+ (attrs all-mep-core-isas)
+ (mode UINT)
+ (subfields f-24u8n-hi f-24u8n-lo)
+ (insert (sequence ()
+ (set (ifield f-24u8n-hi) (srl (ifield f-24u8n) 8))
+ (set (ifield f-24u8n-lo) (and (ifield f-24u8n) #xff))))
+ (extract (set (ifield f-24u8n)
+ (or (sll (ifield f-24u8n-hi) 8)
+ (ifield f-24u8n-lo))))
+ )
+
+(df f-24u4n-hi "24u4n hi 8u4" (all-mep-core-isas) 4 8 UINT #f #f)
+(df f-24u4n-lo "24u4n lo 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
+(define-multi-ifield
+ (name f-24u4n)
+ (comment "coprocessor code")
+ (attrs all-mep-core-isas)
+ (mode UINT)
+ (subfields f-24u4n-hi f-24u4n-lo)
+ (insert (sequence ()
+ (set (ifield f-24u4n-hi) (srl (ifield f-24u4n) 16))
+ (set (ifield f-24u4n-lo) (and (ifield f-24u4n) #xffff))))
+ (extract (set (ifield f-24u4n)
+ (or (sll (ifield f-24u4n-hi) 16)
+ (ifield f-24u4n-lo))))
+ )
+
+(define-multi-ifield
+ (name f-callnum)
+ (comment "system call number field")
+ (attrs all-mep-core-isas)
+ (mode UINT)
+ (subfields f-5 f-6 f-7 f-11)
+ (insert (sequence ()
+ (set (ifield f-5) (and (srl (ifield f-callnum) 3) 1))
+ (set (ifield f-6) (and (srl (ifield f-callnum) 2) 1))
+ (set (ifield f-7) (and (srl (ifield f-callnum) 1) 1))
+ (set (ifield f-11) (and (ifield f-callnum) 1))))
+ (extract (set (ifield f-callnum)
+ (or (sll (ifield f-5) 3)
+ (or (sll (ifield f-6) 2)
+ (or (sll (ifield f-7) 1)
+ (ifield f-11))))))
+ )
+
+(df f-ccrn-hi "ccrn hi 2u28" (all-mep-core-isas) 28 2 UINT #f #f)
+(df f-ccrn-lo "ccrn lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f)
+(define-multi-ifield
+ (name f-ccrn)
+ (comment "Coprocessor register number field")
+ (attrs all-mep-core-isas)
+ (mode UINT)
+ (subfields f-ccrn-hi f-ccrn-lo)
+ (insert (sequence ()
+ (set (ifield f-ccrn-hi) (and (srl (ifield f-ccrn) 4) #x3))
+ (set (ifield f-ccrn-lo) (and (ifield f-ccrn) #xf))))
+ (extract (set (ifield f-ccrn)
+ (or (sll (ifield f-ccrn-hi) 4)
+ (ifield f-ccrn-lo))))
+ )
+\f
+; Operands.
+
+;; Only LABEL, REGNUM, FMAX_FLOAT and FMAX_INT are now relevant for correct
+;; operation. The others are mostly kept for backwards compatibility,
+;; although they do affect the dummy prototypes in
+;; gcc/config/mep/intrinsics.h.
+(define-attr
+ (type enum)
+ (for operand)
+ (name CDATA)
+ (comment "datatype to use for C intrinsics mapping")
+ (values LABEL REGNUM FMAX_FLOAT FMAX_INT
+ POINTER LONG ULONG SHORT USHORT CHAR UCHAR CP_DATA_BUS_INT)
+ (default LONG))
+
+(define-attr
+ (type enum)
+ (for insn)
+ (name CPTYPE)
+ (comment "datatype to use for coprocessor values")
+ (values CP_DATA_BUS_INT VECT V2SI V4HI V8QI V2USI V4UHI V8UQI)
+ (default CP_DATA_BUS_INT))
+
+(define-attr
+ (type enum)
+ (for insn)
+ (name CRET)
+ ;; VOID - all arguments are passed as parameters; if any are written, pointers to them are passed.
+ ;; FIRST - the first argument is the return value.
+ ;; FIRSTCOPY - the first argument is the return value, but a copy is also the first parameter.
+ (values VOID FIRST FIRSTCOPY)
+ (default VOID)
+ (comment "Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it."))
+
+(define-attr
+ (type integer)
+ (for operand)
+ (name ALIGN)
+ (comment "alignment of immediate operands")
+ (default 1))
+
+(define-attr
+ (for operand)
+ (type boolean)
+ (name RELOC_IMPLIES_OVERFLOW)
+ (comment "Operand should not be considered as a candidate for relocs"))
+
+(define-attr
+ (for hardware)
+ (type boolean)
+ (name IS_FLOAT)
+ (comment "Register contains a floating point value"))
+
+(define-pmacro (dpop name commment attrib hwr field func)
+ (define-full-operand name comment attrib
+ hwr DFLT field ((parse func)) () ()))
+(define-pmacro (dprp name commment attrib hwr field pafunc prfunc)
+ (define-full-operand name comment attrib
+ hwr DFLT field ((parse pafunc) (print prfunc)) () ()))
+
+(dnop r0 "register 0" (all-mep-core-isas) h-gpr 0)
+(dnop rn "register Rn" (all-mep-core-isas) h-gpr f-rn)
+(dnop rm "register Rm" (all-mep-core-isas) h-gpr f-rm)
+(dnop rl "register Rl" (all-mep-core-isas) h-gpr f-rl)
+(dnop rn3 "register 0-7" (all-mep-core-isas) h-gpr f-rn3)
+
+;; Variants of RM/RN with different CDATA attributes. See comment above
+;; CDATA for more details.
+
+(dnop rma "register Rm holding pointer" (all-mep-core-isas (CDATA POINTER)) h-gpr f-rm)
+
+(dnop rnc "register Rn holding char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
+(dnop rnuc "register Rn holding unsigned char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
+(dnop rns "register Rn holding short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
+(dnop rnus "register Rn holding unsigned short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
+(dnop rnl "register Rn holding long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
+(dnop rnul "register Rn holding unsigned long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn)
+
+(dnop rn3c "register 0-7 holding unsigned char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3)
+(dnop rn3uc "register 0-7 holding byte" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3)
+(dnop rn3s "register 0-7 holding unsigned short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3)
+(dnop rn3us "register 0-7 holding short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3)
+(dnop rn3l "register 0-7 holding unsigned long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3)
+(dnop rn3ul "register 0-7 holding long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn3)
+
+
+(dnop lp "link pointer" (all-mep-core-isas) h-csr 1)
+(dnop sar "shift amount register" (all-mep-core-isas) h-csr 2)
+(dnop hi "high result" (all-mep-core-isas) h-csr 7)
+(dnop lo "low result" (all-mep-core-isas) h-csr 8)
+(dnop mb0 "modulo begin register 0" (all-mep-core-isas) h-csr 12)
+(dnop me0 "modulo end register 0" (all-mep-core-isas) h-csr 13)
+(dnop mb1 "modulo begin register 1" (all-mep-core-isas) h-csr 14)
+(dnop me1 "modulo end register 1" (all-mep-core-isas) h-csr 15)
+(dnop psw "program status word" (all-mep-core-isas) h-csr 16)
+(dnop epc "exception prog counter" (all-mep-core-isas) h-csr 19)
+(dnop exc "exception cause" (all-mep-core-isas) h-csr 20)
+(dnop npc "nmi program counter" (all-mep-core-isas) h-csr 23)
+(dnop dbg "debug register" (all-mep-core-isas) h-csr 24)
+(dnop depc "debug exception pc" (all-mep-core-isas) h-csr 25)
+(dnop opt "option register" (all-mep-core-isas) h-csr 26)
+(dnop r1 "register 1" (all-mep-core-isas) h-gpr 1)
+(dnop tp "tiny data area pointer" (all-mep-core-isas) h-gpr 13)
+(dnop sp "stack pointer" (all-mep-core-isas) h-gpr 15)
+(dprp tpr "TP register" (all-mep-core-isas) h-gpr 13 "tpreg" "tpreg")
+(dprp spr "SP register" (all-mep-core-isas) h-gpr 15 "spreg" "spreg")
+
+(define-full-operand
+ csrn "control/special register" (all-mep-core-isas (CDATA REGNUM)) h-csr
+ DFLT f-csrn ((parse "csrn")) () ()
+)
+
+(dnop csrn-idx "control/special reg idx" (all-mep-core-isas) h-uint f-csrn)
+(dnop crn64 "copro Rn (64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-crn)
+(dnop crn "copro Rn (32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr f-crn)
+(dnop crnx64 "copro Rn (0-31, 64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-crnx)
+(dnop crnx "copro Rn (0-31, 32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr f-crnx)
+(dnop ccrn "copro control reg CCRn" (all-mep-core-isas (CDATA REGNUM)) h-ccr f-ccrn)
+(dnop cccc "copro flags" (all-mep-core-isas) h-uint f-rm)
+
+(dprp pcrel8a2 "pc-rel addr (8 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-8s8a2 "mep_align" "address")
+(dprp pcrel12a2 "pc-rel addr (12 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-12s4a2 "mep_align" "address")
+(dprp pcrel17a2 "pc-rel addr (17 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-17s16a2 "mep_align" "address")
+(dprp pcrel24a2 "pc-rel addr (24 bits)" (all-mep-core-isas (CDATA LABEL)) h-sint f-24s5a2n "mep_align" "address")
+(dprp pcabs24a2 "pc-abs addr (24 bits)" (all-mep-core-isas (CDATA LABEL)) h-uint f-24u5a2n "mep_alignu" "address")
+
+(dpop sdisp16 "displacement (16 bits)" (all-mep-core-isas) h-sint f-16s16 "signed16")
+(dpop simm16 "signed imm (16 bits)" (all-mep-core-isas) h-sint f-16s16 "signed16")
+(dpop uimm16 "unsigned imm (16 bits)" (all-mep-core-isas) h-uint f-16u16 "unsigned16")
+(dnop code16 "uci/dsp code (16 bits)" (all-mep-core-isas) h-uint f-16u16)
+
+(dnop udisp2 "SSARB addend (2 bits)" (all-mep-core-isas) h-sint f-2u6)
+(dnop uimm2 "interrupt (2 bits)" (all-mep-core-isas) h-uint f-2u10)
+
+(dnop simm6 "add const (6 bits)" (all-mep-core-isas) h-sint f-6s8)
+(dnop simm8 "mov const (8 bits)" (all-mep-core-isas RELOC_IMPLIES_OVERFLOW)
+ h-sint f-8s8)
+
+(dpop addr24a4 "sw/lw addr (24 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-24u8a4n "mep_alignu")
+(dnop code24 "coprocessor code" (all-mep-core-isas) h-uint f-24u4n)
+
+(dnop callnum "system call number" (all-mep-core-isas) h-uint f-callnum)
+(dnop uimm3 "bit immediate (3 bits)" (all-mep-core-isas) h-uint f-3u5)
+(dnop uimm4 "bCC const (4 bits)" (all-mep-core-isas) h-uint f-4u8)
+(dnop uimm5 "bit/shift val (5 bits)" (all-mep-core-isas) h-uint f-5u8)
+
+(dpop udisp7 "tp-rel b (7 bits)" (all-mep-core-isas) h-uint f-7u9 "unsigned7")
+(dpop udisp7a2 "tp-rel h (7 bits)" (all-mep-core-isas (ALIGN 2)) h-uint f-7u9a2 "unsigned7")
+(dpop udisp7a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-7u9a4 "unsigned7")
+(dpop uimm7a4 "sp w-addend (7 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-7u9a4 "mep_alignu")
+
+(dnop uimm24 "immediate (24 bits)" (all-mep-core-isas) h-uint f-24u8n)
+
+(dnop cimm4 "cache immed'te (4 bits)" (all-mep-core-isas) h-uint f-rn)
+(dnop cimm5 "clip immediate (5 bits)" (all-mep-core-isas) h-uint f-5u24)
+
+(dpop cdisp10 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
+(dpop cdisp10a2 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
+(dpop cdisp10a4 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
+(dpop cdisp10a8 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
+
+; Special operand representing the various ways that the literal zero can be
+; specified.
+(define-full-operand
+ zero "Zero operand" (all-mep-core-isas) h-sint DFLT f-nil
+ ((parse "zero")) () ()
+)
+\f
+; Attributes.
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_BIT_INSN)
+ (comment "optional bit manipulation instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_MUL_INSN)
+ (comment "optional 32-bit multiply instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_DIV_INSN)
+ (comment "optional 32-bit divide instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_DEBUG_INSN)
+ (comment "optional debug instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_LDZ_INSN)
+ (comment "optional leading zeroes instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_ABS_INSN)
+ (comment "optional absolute difference instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_AVE_INSN)
+ (comment "optional average instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_MINMAX_INSN)
+ (comment "optional min/max instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_CLIP_INSN)
+ (comment "optional clipping instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_SAT_INSN)
+ (comment "optional saturation instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_UCI_INSN)
+ (comment "optional UCI instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_DSP_INSN)
+ (comment "optional DSP instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_CP_INSN)
+ (comment "optional coprocessor-related instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_CP64_INSN)
+ (comment "optional coprocessor-related 64 data bit instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name OPTIONAL_VLIW64)
+ (comment "optional vliw64 mode (vliw32 is default)"))
+
+(define-attr
+ (for insn)
+ (type enum)
+ (name STALL)
+ (attrs META)
+ (values NONE SHIFTI INT2 LOAD STORE LDC STC LDCB STCB SSARB FSFT RET
+ ADVCK MUL MULR DIV)
+ (default NONE)
+ (comment "gcc stall attribute"))
+
+(define-attr
+ (for insn)
+ (type string)
+ (name INTRINSIC)
+ (attrs META)
+ (comment "gcc intrinsic name"))
+
+(define-attr
+ (for insn)
+ (type enum)
+ (name SLOT)
+ (attrs META)
+ (values NONE C3 V1 V3 P0S P0 P1)
+ (default NONE)
+ (comment "coprocessor slot type"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name MAY_TRAP)
+ (comment "instruction may generate an exception"))
+
+; Attributes for scheduling restrictions in vliw mode
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name VLIW_ALONE)
+ (comment "instruction can be scheduled alone in vliw mode"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name VLIW_NO_CORE_NOP)
+ (comment "there is no corresponding nop core instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name VLIW_NO_COP_NOP)
+ (comment "there is no corresponding nop coprocessor instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name VLIW64_NO_MATCHING_NOP)
+ (comment "there is no corresponding nop coprocessor instruction"))
+(define-attr
+ (for insn)
+ (type boolean)
+ (name VLIW32_NO_MATCHING_NOP)
+ (comment "there is no corresponding nop coprocessor instruction"))
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name VOLATILE)
+ (comment "Insn is volatile."))
+
+(define-attr
+ (for insn)
+ (type integer)
+ (name LATENCY)
+ (comment "The latency of this insn, used for scheduling as an intrinsic in gcc")
+ (default 0))
+
+; The MeP config tool will edit this.
+(define-attr
+ (type enum)
+ (for insn)
+ (name CONFIG)
+ (values NONE ; config-attr-start
+ default
+ ) ; config-attr-end
+)
+
+\f
+; Enumerations.
+
+(define-normal-insn-enum major "major opcodes" (all-mep-core-isas) MAJ_
+ f-major
+ (.map .str (.iota 16))
+)
+
+
+(define-pmacro (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming isa)
+ (define-insn
+ (name xname)
+ (comment xcomment)
+ (.splice attrs (.unsplice xattrs) (ISA isa))
+ (syntax xsyntax)
+ (format xformat)
+ (semantics xsemantics)
+ (.splice timing (.unsplice xtiming))
+ )
+)
+
+(define-pmacro (dnmi-isa xname xcomment xattrs xsyntax xemit isa)
+ (dnmi xname xcomment (.splice (.unsplice xattrs) (ISA isa)) xsyntax xemit)
+)
+
+; For making profiling calls and dynamic configuration
+(define-pmacro (cg-profile caller callee)
+ (c-call "cg_profile" caller callee)
+)
+; For dynamic configuration only
+(define-pmacro (cg-profile-jump caller callee)
+ (c-call "cg_profile_jump" caller callee)
+)
+
+; For defining Core Instructions
+(define-pmacro (dnci xname xcomment xattrs xsyntax xformat xsemantics xtiming)
+ (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming all-core-isa-list)
+)
+(define-pmacro (dncmi xname xcomment xattrs xsyntax xemit)
+ (dnmi-isa xname xcomment xattrs xsyntax xemit all-core-isa-list)
+)
+
+; For defining Coprocessor Instructions
+;(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming cop)
+;)
+
+;; flag setting macro
+(define-pmacro (set-bit xop xbitnum xval)
+ (set xop (or
+ (and xop (inv (sll 1 xbitnum)))
+ (and (sll 1 xbitnum) (sll xval xbitnum)))))
+
+;; some flags we commonly use in vliw reasoning / mode-switching etc.
+(define-pmacro (get-opt.vliw64) (and (srl opt 6) 1))
+(define-pmacro (get-opt.vliw32) (and (srl opt 5) 1))
+(define-pmacro (get-rm.lsb) (and rm 1))
+(define-pmacro (get-psw.om) (and (srl psw 12) 1))
+(define-pmacro (get-psw.nmi) (and (srl psw 9) 1))
+(define-pmacro (get-psw.iep) (and (srl psw 1) 1))
+(define-pmacro (get-psw.ump) (and (srl psw 3) 1))
+(define-pmacro (get-epc.etom) (and epc 1))
+(define-pmacro (get-npc.ntom) (and npc 1))
+(define-pmacro (get-lp.ltom) (and lp 1))
+
+(define-pmacro (set-psw.om zval) (set-bit (raw-reg h-csr 16) 12 zval))
+(define-pmacro (set-psw.nmi zval) (set-bit (raw-reg h-csr 16) 9 zval))
+(define-pmacro (set-psw.umc zval) (set-bit (raw-reg h-csr 16) 2 zval))
+(define-pmacro (set-psw.iec zval) (set-bit (raw-reg h-csr 16) 0 zval))
+(define-pmacro (set-rpe.elr zval) (set-bit (raw-reg h-csr 5) 0 zval))
+
+
+;; the "3 way switch" depending on our current operating mode and vliw status flags
+(define-pmacro (core-vliw-switch core-rtl vliw32-rtl vliw64-rtl)
+ (cond
+ ((andif (get-psw.om) (get-opt.vliw64)) vliw64-rtl)
+ ((andif (get-psw.om) (get-opt.vliw32)) vliw32-rtl)
+ (else core-rtl)))
+
+;; the varying-pcrel idiom
+(define-pmacro (set-vliw-modified-pcrel-offset xtarg xa xb xc)
+ (core-vliw-switch (set xtarg (add pc xa))
+ (set xtarg (add pc xb))
+ (set xtarg (add pc xc))))
+
+;; the increasing-alignment idiom in branch displacements
+(define-pmacro (set-vliw-alignment-modified xtarg zaddr)
+ (core-vliw-switch (set xtarg (and zaddr (inv 1)))
+ (set xtarg (and zaddr (inv 3)))
+ (set xtarg (and zaddr (inv 7)))))
+
+;; the increasing-alignment idiom in option-only form
+(define-pmacro (set-vliw-aliignment-modified-by-option xtarg zaddr)
+ (if (get-opt.vliw32)
+ (set xtarg (and zaddr (inv 3)))
+ (set xtarg (and zaddr (inv 7)))))
+
+
+\f
+; pmacros needed for coprocessor modulo addressing.
+
+; Taken from supplement ``The operation of the modulo addressing'' in
+; Toshiba documentation rev 2.2, p. 34.
+
+(define-pmacro (compute-mask0)
+ (sequence SI ((SI temp))
+ (set temp (or mb0 me0))
+ (srl (const SI -1) (c-call SI "do_ldz" temp))))
+
+(define-pmacro (mod0 immed)
+ (sequence SI ((SI modulo-mask))
+ (set modulo-mask (compute-mask0))
+ (if SI (eq (and rma modulo-mask) me0)
+ (or (and rma (inv modulo-mask)) mb0)
+ (add rma (ext SI immed)))))
+
+(define-pmacro (compute-mask1)
+ (sequence SI ((SI temp))
+ (set temp (or mb1 me1))
+ (srl (const SI -1) (c-call SI "do_ldz" temp))))
+
+(define-pmacro (mod1 immed)
+ (sequence SI ((SI modulo-mask))
+ (set modulo-mask (compute-mask1))
+ (if SI (eq (and rma modulo-mask) me1)
+ (or (and rma (inv modulo-mask)) mb1)
+ (add rma (ext SI immed)))))
+
+\f
+; Instructions.
+
+; A pmacro for use in semantic bodies of unimplemented insns.
+(define-pmacro (unimp mnemonic) (nop))
+
+; Core specific instructions
+; (include "mep-h1.cpu") ; -- exposed by MeP-Integrator
+(include "mep-c5.cpu") ; -- exposed by MeP-Integrator
+
+; Load/store instructions.
+
+(dnci sb "store byte (register indirect)" ((STALL STORE))
+ "sb $rnc,($rma)"
+ (+ MAJ_0 rnc rma (f-sub4 8))
+ (sequence ()
+ (c-call VOID "check_write_to_text" rma)
+ (set (mem UQI rma) (and rnc #xff)))
+ ((mep (unit u-use-gpr (in usereg rnc))
+ (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci sh "store half-word (register indirect)" ((STALL STORE))
+ "sh $rns,($rma)"
+ (+ MAJ_0 rns rma (f-sub4 9))
+ (sequence ()
+ (c-call VOID "check_write_to_text" (and rma (inv 1)))
+ (set (mem UHI (and rma (inv 1))) (and rns #xffff)))
+ ((mep (unit u-use-gpr (in usereg rns))
+ (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci sw "store word (register indirect)" ((STALL STORE))
+ "sw $rnl,($rma)"
+ (+ MAJ_0 rnl rma (f-sub4 10))
+ (sequence ()
+ (c-call VOID "check_write_to_text" (and rma (inv 3)))
+ (set (mem USI (and rma (inv 3))) rnl))
+ ((mep (unit u-use-gpr (in usereg rnl))
+ (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lb "load byte (register indirect)" ((STALL LOAD) (LATENCY 2))
+ "lb $rnc,($rma)"
+ (+ MAJ_0 rnc rma (f-sub4 12))
+ (set rnc (ext SI (mem QI rma)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rnc)))))
+
+(dnci lh "load half-word (register indirect)" ((STALL LOAD) (LATENCY 2))
+ "lh $rns,($rma)"
+ (+ MAJ_0 rns rma (f-sub4 13))
+ (set rns (ext SI (mem HI (and rma (inv 1)))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rns)))))
+
+(dnci lw "load word (register indirect)" ((STALL LOAD) (LATENCY 2))
+ "lw $rnl,($rma)"
+ (+ MAJ_0 rnl rma (f-sub4 14))
+ (set rnl (mem SI (and rma (inv 3))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rnl)))))
+
+(dnci lbu "load unsigned byte (register indirect)" ((STALL LOAD) (LATENCY 2))
+ "lbu $rnuc,($rma)"
+ (+ MAJ_0 rnuc rma (f-sub4 11))
+ (set rnuc (zext SI (mem UQI rma)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rnuc)))))
+
+(dnci lhu "load unsigned half-word (register indirect)" ((STALL LOAD) (LATENCY 2))
+ "lhu $rnus,($rma)"
+ (+ MAJ_0 rnus rma (f-sub4 15))
+ (set rnus (zext SI (mem UHI (and rma (inv 1)))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rnus)))))
+
+(dnci sw-sp "store word (sp relative)" ((STALL STORE))
+ "sw $rnl,$udisp7a4($spr)"
+ (+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 2))
+ (sequence ()
+ (c-call VOID "check_write_to_text" (and (add udisp7a4 sp) (inv 3)))
+ (set (mem SI (and (add udisp7a4 sp) (inv 3))) rnl))
+ ((mep (unit u-use-gpr (in usereg rnl))
+ (unit u-use-gpr (in usereg sp))
+ (unit u-exec))))
+
+
+(dnci lw-sp "load word (sp relative)" ((STALL LOAD) (LATENCY 2))
+ "lw $rnl,$udisp7a4($spr)"
+ (+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 3))
+ (set rnl (mem SI (and (add udisp7a4 sp) (inv 3))))
+ ((mep (unit u-use-gpr (in usereg sp))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rnl)))))
+
+(dnci sb-tp "store byte (tp relative)" ((STALL STORE))
+ "sb $rn3c,$udisp7($tpr)"
+ (+ MAJ_8 (f-4 0) rn3c (f-8 0) udisp7)
+ (sequence ()
+ (c-call VOID "check_write_to_text" (add (zext SI udisp7) tp))
+ (set (mem QI (add (zext SI udisp7) tp)) (and rn3c #xff)))
+ ((mep (unit u-use-gpr (in usereg rn3c))
+ (unit u-use-gpr (in usereg tp))
+ (unit u-exec))))
+
+(dnci sh-tp "store half-word (tp relative)" ((STALL STORE))
+ "sh $rn3s,$udisp7a2($tpr)"
+ (+ MAJ_8 (f-4 0) rn3s (f-8 1) udisp7a2 (f-15 0))
+ (sequence ()
+ (c-call VOID "check_write_to_text" (and (add (zext SI udisp7a2) tp) (inv 1)))
+ (set (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))) (and rn3s #xffff)))
+ ((mep (unit u-use-gpr (in usereg rn3s))
+ (unit u-use-gpr (in usereg tp))
+ (unit u-exec))))
+
+(dnci sw-tp "store word (tp relative)" ((STALL STORE))
+ "sw $rn3l,$udisp7a4($tpr)"
+ (+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 2))
+ (sequence ()
+ (c-call VOID "check_write_to_text" (and (add (zext SI udisp7a4) tp) (inv 3)))
+ (set (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))) rn3l))
+ ((mep (unit u-use-gpr (in usereg rn3l))
+ (unit u-use-gpr (in usereg tp))
+ (unit u-exec))))
+
+(dnci lb-tp "load byte (tp relative)" ((STALL LOAD) (LATENCY 2))
+ "lb $rn3c,$udisp7($tpr)"
+ (+ MAJ_8 (f-4 1) rn3c (f-8 0) udisp7)
+ (set rn3c (ext SI (mem QI (add (zext SI udisp7) tp))))
+ ((mep (unit u-use-gpr (in usereg tp))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rn3c)))))
+
+(dnci lh-tp "load half-word (tp relative)" ((STALL LOAD) (LATENCY 2))
+ "lh $rn3s,$udisp7a2($tpr)"
+ (+ MAJ_8 (f-4 1) rn3s (f-8 1) udisp7a2 (f-15 0))
+ (set rn3s (ext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1)))))
+ ((mep (unit u-use-gpr (in usereg tp))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rn3s)))))
+
+(dnci lw-tp "load word (tp relative)" ((STALL LOAD) (LATENCY 2))
+ "lw $rn3l,$udisp7a4($tpr)"
+ (+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 3))
+ (set rn3l (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))))
+ ((mep (unit u-use-gpr (in usereg tp))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rn3l)))))
+
+(dnci lbu-tp "load unsigned byte (tp relative)" ((STALL LOAD) (LATENCY 2))
+ "lbu $rn3uc,$udisp7($tpr)"
+ (+ MAJ_4 (f-4 1) rn3uc (f-8 1) udisp7)
+ (set rn3uc (zext SI (mem QI (add (zext SI udisp7) tp))))
+ ((mep (unit u-use-gpr (in usereg tp))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rn3uc)))))
+
+(dnci lhu-tp "load unsigned half-word (tp relative)" ((STALL LOAD) (LATENCY 2))
+ "lhu $rn3us,$udisp7a2($tpr)"
+ (+ MAJ_8 (f-4 1) rn3us (f-8 1) udisp7a2 (f-15 1))
+ (set rn3us (zext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1)))))
+ ((mep (unit u-use-gpr (in usereg tp))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rn3us)))))
+
+(dnci sb16 "store byte (16 bit displacement)" ((STALL STORE))
+ "sb $rnc,$sdisp16($rma)"
+ (+ MAJ_12 rnc rma (f-sub4 8) sdisp16)
+ (sequence ()
+ (c-call VOID "check_write_to_text" (add rma (ext SI sdisp16)))
+ (set (mem QI (add rma (ext SI sdisp16))) (and rnc #xff)))
+ ((mep (unit u-use-gpr (in usereg rnc))
+ (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci sh16 "store half-word (16 bit displacement)" ((STALL STORE))
+ "sh $rns,$sdisp16($rma)"
+ (+ MAJ_12 rns rma (f-sub4 9) sdisp16)
+ (sequence ()
+ (c-call VOID "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 1)))
+ (set (mem HI (and (add rma (ext SI sdisp16)) (inv 1))) (and rns #xffff)))
+ ((mep (unit u-use-gpr (in usereg rns))
+ (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci sw16 "store word (16 bit displacement)" ((STALL STORE))
+ "sw $rnl,$sdisp16($rma)"
+ (+ MAJ_12 rnl rma (f-sub4 10) sdisp16)
+ (sequence ()
+ (c-call "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 3)))
+ (set (mem SI (and (add rma (ext SI sdisp16)) (inv 3))) rnl))
+ ((mep (unit u-use-gpr (in usereg rnl))
+ (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lb16 "load byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
+ "lb $rnc,$sdisp16($rma)"
+ (+ MAJ_12 rnc rma (f-sub4 12) sdisp16)
+ (set rnc (ext SI (mem QI (add rma (ext SI sdisp16)))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rnc)))))
+
+(dnci lh16 "load half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
+ "lh $rns,$sdisp16($rma)"
+ (+ MAJ_12 rns rma (f-sub4 13) sdisp16)
+ (set rns (ext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1)))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rns)))))
+
+(dnci lw16 "load word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
+ "lw $rnl,$sdisp16($rma)"
+ (+ MAJ_12 rnl rma (f-sub4 14) sdisp16)
+ (set rnl (mem SI (and (add rma (ext SI sdisp16)) (inv 3))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rnl)))))
+
+(dnci lbu16 "load unsigned byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
+ "lbu $rnuc,$sdisp16($rma)"
+ (+ MAJ_12 rnuc rma (f-sub4 11) sdisp16)
+ (set rnuc (zext SI (mem QI (add rma (ext SI sdisp16)))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rnuc)))))
+
+(dnci lhu16 "load unsigned half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
+ "lhu $rnus,$sdisp16($rma)"
+ (+ MAJ_12 rnus rma (f-sub4 15) sdisp16)
+ (set rnus (zext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1)))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rnus)))))
+
+(dnci sw24 "store word (24 bit absolute addressing)" ((STALL STORE))
+ "sw $rnl,($addr24a4)"
+ (+ MAJ_14 rnl addr24a4 (f-sub2 2))
+ (sequence ()
+ (c-call VOID "check_write_to_text" (zext SI addr24a4))
+ (set (mem SI (zext SI addr24a4)) rnl))
+ ((mep (unit u-use-gpr (in usereg rnl))
+ (unit u-exec))))
+
+(dnci lw24 "load word (24 bit absolute addressing)" ((STALL LOAD) (LATENCY 2))
+ "lw $rnl,($addr24a4)"
+ (+ MAJ_14 rnl addr24a4 (f-sub2 3))
+ (set rnl (mem SI (zext SI addr24a4)))
+ ((mep (unit u-exec)
+ (unit u-load-gpr (out loadreg rnl)))))
+
+\f
+; Extension instructions.
+
+(dnci extb "sign extend byte" ()
+ "extb $rn"
+ (+ MAJ_1 rn (f-rm 0) (f-sub4 13))
+ (set rn (ext SI (and QI rn #xff)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci exth "sign extend half-word" ()
+ "exth $rn"
+ (+ MAJ_1 rn (f-rm 2) (f-sub4 13))
+ (set rn (ext SI (and HI rn #xffff)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci extub "zero extend byte" ()
+ "extub $rn"
+ (+ MAJ_1 rn (f-rm 8) (f-sub4 13))
+ (set rn (zext SI (and rn #xff)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci extuh "zero extend half-word" ()
+ "extuh $rn"
+ (+ MAJ_1 rn (f-rm 10) (f-sub4 13))
+ (set rn (zext SI (and rn #xffff)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+\f
+; Shift amount manipulation instructions.
+
+(dnci ssarb "set sar to bytes" ((STALL SSARB))
+ "ssarb $udisp2($rm)"
+ (+ MAJ_1 (f-4 0) (f-5 0) udisp2 rm (f-sub4 12))
+ (if (c-call BI "big_endian_p")
+ (set sar (zext SI (mul (and (add udisp2 rm) 3) 8)))
+ (set sar (sub 32 (zext SI (mul (and (add udisp2 rm) 3) 8)))))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+\f
+; Move instructions.
+
+(dnci mov "move" ()
+ "mov $rn,$rm"
+ (+ MAJ_0 rn rm (f-sub4 0))
+ (set rn rm)
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci movi8 "move 8-bit immediate" ()
+ "mov $rn,$simm8"
+ (+ MAJ_5 rn simm8)
+ (set rn (ext SI simm8))
+ ())
+
+(dnci movi16 "move 16-bit immediate" ()
+ "mov $rn,$simm16"
+ (+ MAJ_12 rn (f-rm 0) (f-sub4 1) simm16)
+ (set rn (ext SI simm16))
+ ())
+
+(dnci movu24 "move 24-bit unsigned immediate" ()
+ "movu $rn3,$uimm24"
+ (+ MAJ_13 (f-4 0) rn3 uimm24)
+ (set rn3 (zext SI uimm24))
+ ())
+
+(dnci movu16 "move 16-bit unsigned immediate" ()
+ "movu $rn,$uimm16"
+ (+ MAJ_12 rn (f-rm 1) (f-sub4 1) uimm16)
+ (set rn (zext SI uimm16))
+ ())
+
+(dnci movh "move high 16-bit immediate" ()
+ "movh $rn,$uimm16"
+ (+ MAJ_12 rn (f-rm 2) (f-sub4 1) uimm16)
+ (set rn (sll uimm16 16))
+ ())
+
+\f
+; Arithmetic instructions.
+
+(dnci add3 "add three registers" ()
+ "add3 $rl,$rn,$rm"
+ (+ MAJ_9 rn rm rl)
+ (set rl (add rn rm))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci add "add" ()
+ "add $rn,$simm6"
+ (+ MAJ_6 rn simm6 (f-sub2 0))
+ (set rn (add rn (ext SI simm6)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci add3i "add two registers and immediate" ()
+ "add3 $rn,$spr,$uimm7a4"
+ (+ MAJ_4 rn (f-8 0) uimm7a4 (f-sub2 0))
+ (set rn (add sp (zext SI uimm7a4)))
+ ((mep (unit u-use-gpr (in usereg sp))
+ (unit u-exec))))
+
+(dnci advck3 "add overflow check" ((STALL ADVCK))
+ "advck3 \\$0,$rn,$rm"
+ (+ MAJ_0 rn rm (f-sub4 7))
+ (if (add-oflag rn rm 0)
+ (set r0 1)
+ (set r0 0))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci sub "subtract" ()
+ "sub $rn,$rm"
+ (+ MAJ_0 rn rm (f-sub4 4))
+ (set rn (sub rn rm))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm)))))
+
+(dnci sbvck3 "subtraction overflow check" ((STALL ADVCK))
+ "sbvck3 \\$0,$rn,$rm"
+ (+ MAJ_0 rn rm (f-sub4 5))
+ (if (sub-oflag rn rm 0)
+ (set r0 1)
+ (set r0 0))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci neg "negate" ()
+ "neg $rn,$rm"
+ (+ MAJ_0 rn rm (f-sub4 1))
+ (set rn (neg rm))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci slt3 "set if less than" ()
+ "slt3 \\$0,$rn,$rm"
+ (+ MAJ_0 rn rm (f-sub4 2))
+ (if (lt rn rm)
+ (set r0 1)
+ (set r0 0))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci sltu3 "set less than unsigned" ()
+ "sltu3 \\$0,$rn,$rm"
+ (+ MAJ_0 rn rm (f-sub4 3))
+ (if (ltu rn rm)
+ (set r0 1)
+ (set r0 0))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci slt3i "set if less than immediate" ()
+ "slt3 \\$0,$rn,$uimm5"
+ (+ MAJ_6 rn uimm5 (f-sub3 1))
+ (if (lt rn (zext SI uimm5))
+ (set r0 1)
+ (set r0 0))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci sltu3i "set if less than unsigned immediate" ()
+ "sltu3 \\$0,$rn,$uimm5"
+ (+ MAJ_6 rn uimm5 (f-sub3 5))
+ (if (ltu rn (zext SI uimm5))
+ (set r0 1)
+ (set r0 0))
+ ())
+
+(dnci sl1ad3 "shift left one and add" ((STALL INT2))
+ "sl1ad3 \\$0,$rn,$rm"
+ (+ MAJ_2 rn rm (f-sub4 6))
+ (set r0 (add (sll rn 1) rm))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci sl2ad3 "shift left two and add" ((STALL INT2))
+ "sl2ad3 \\$0,$rn,$rm"
+ (+ MAJ_2 rn rm (f-sub4 7))
+ (set r0 (add (sll rn 2) rm))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci add3x "three operand add (extended)" ()
+ "add3 $rn,$rm,$simm16"
+ (+ MAJ_12 rn rm (f-sub4 0) simm16)
+ (set rn (add rm (ext SI simm16)))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci slt3x "set if less than (extended)" ()
+ "slt3 $rn,$rm,$simm16"
+ (+ MAJ_12 rn rm (f-sub4 2) simm16)
+ (if (lt rm (ext SI simm16))
+ (set rn 1)
+ (set rn 0))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci sltu3x "set if less than unsigned (extended)" ()
+ "sltu3 $rn,$rm,$uimm16"
+ (+ MAJ_12 rn rm (f-sub4 3) uimm16)
+ (if (ltu rm (zext SI uimm16))
+ (set rn 1)
+ (set rn 0))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+\f
+; Logical instructions.
+
+(dnci or "bitwise or" ()
+ "or $rn,$rm"
+ (+ MAJ_1 rn rm (f-sub4 0))
+ (set rn (or rn rm))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci and "bitwise and" ()
+ "and $rn,$rm"
+ (+ MAJ_1 rn rm (f-sub4 1))
+ (set rn (and rn rm))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci xor "bitwise exclusive or" ()
+ "xor $rn,$rm"
+ (+ MAJ_1 rn rm (f-sub4 2))
+ (set rn (xor rn rm))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci nor "bitwise negated or" ()
+ "nor $rn,$rm"
+ (+ MAJ_1 rn rm (f-sub4 3))
+ (set rn (inv (or rn rm)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci or3 "or three operand" ()
+ "or3 $rn,$rm,$uimm16"
+ (+ MAJ_12 rn rm (f-sub4 4) uimm16)
+ (set rn (or rm (zext SI uimm16)))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci and3 "and three operand" ()
+ "and3 $rn,$rm,$uimm16"
+ (+ MAJ_12 rn rm (f-sub4 5) uimm16)
+ (set rn (and rm (zext SI uimm16)))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci xor3 "exclusive or three operand" ()
+ "xor3 $rn,$rm,$uimm16"
+ (+ MAJ_12 rn rm (f-sub4 6) uimm16)
+ (set rn (xor rm (zext SI uimm16)))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+\f
+; Shift instructions.
+
+(dnci sra "shift right arithmetic" ((STALL INT2))
+ "sra $rn,$rm"
+ (+ MAJ_2 rn rm (f-sub4 13))
+ (set rn (sra rn (and rm #x1f)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci srl "shift right logical" ((STALL INT2))
+ "srl $rn,$rm"
+ (+ MAJ_2 rn rm (f-sub4 12))
+ (set rn (srl rn (and rm #x1f)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci sll "shift left logical" ((STALL INT2))
+ "sll $rn,$rm"
+ (+ MAJ_2 rn rm (f-sub4 14))
+ (set rn (sll rn (and rm #x1f)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+(dnci srai "shift right arithmetic (immediate)" ((STALL SHIFTI))
+ "sra $rn,$uimm5"
+ (+ MAJ_6 rn uimm5 (f-sub3 3))
+ (set rn (sra rn uimm5))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci srli "shift right logical (immediate)" ((STALL SHIFTI))
+ "srl $rn,$uimm5"
+ (+ MAJ_6 rn uimm5 (f-sub3 2))
+ (set rn (srl rn uimm5))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci slli "shift left logical (immediate)" ((STALL SHIFTI))
+ "sll $rn,$uimm5"
+ (+ MAJ_6 rn uimm5 (f-sub3 6))
+ (set rn (sll rn uimm5))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci sll3 "three-register shift left logical" ((STALL INT2))
+ "sll3 \\$0,$rn,$uimm5"
+ (+ MAJ_6 rn uimm5 (f-sub3 7))
+ (set r0 (sll rn uimm5))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci fsft "field shift" ((STALL FSFT))
+ "fsft $rn,$rm"
+ (+ MAJ_2 rn rm (f-sub4 15))
+ (sequence ((DI temp) (QI shamt))
+ (set shamt (and sar #x3f))
+ (set temp (sll (or (sll (zext DI rn) 32) (zext DI rm)) shamt))
+ (set rn (subword SI (srl temp 32) 1)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+\f
+; Branch/jump instructions.
+
+(dnci bra "branch" (RELAXABLE)
+ "bra $pcrel12a2"
+ (+ MAJ_11 pcrel12a2 (f-15 0))
+ (set-vliw-alignment-modified pc pcrel12a2)
+ ((mep (unit u-branch)
+ (unit u-exec))))
+
+(dnci beqz "branch if equal zero" (RELAXABLE)
+ "beqz $rn,$pcrel8a2"
+ (+ MAJ_10 rn pcrel8a2 (f-15 0))
+ (if (eq rn 0)
+ (set-vliw-alignment-modified pc pcrel8a2))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec)
+ (unit u-branch))))
+
+(dnci bnez "branch if not equal zero" (RELAXABLE)
+ "bnez $rn,$pcrel8a2"
+ (+ MAJ_10 rn pcrel8a2 (f-15 1))
+ (if (ne rn 0)
+ (set-vliw-alignment-modified pc pcrel8a2))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec)
+ (unit u-branch))))
+
+(dnci beqi "branch equal immediate" (RELAXABLE)
+ "beqi $rn,$uimm4,$pcrel17a2"
+ (+ MAJ_14 rn uimm4 (f-sub4 0) pcrel17a2)
+ (if (eq rn (zext SI uimm4))
+ (set-vliw-alignment-modified pc pcrel17a2))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec)
+ (unit u-branch))))
+
+(dnci bnei "branch not equal immediate" (RELAXABLE)
+ "bnei $rn,$uimm4,$pcrel17a2"
+ (+ MAJ_14 rn uimm4 (f-sub4 4) pcrel17a2)
+ (if (ne rn (zext SI uimm4))
+ (set-vliw-alignment-modified pc pcrel17a2))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec)
+ (unit u-branch))))
+
+(dnci blti "branch less than immediate" (RELAXABLE)
+ "blti $rn,$uimm4,$pcrel17a2"
+ (+ MAJ_14 rn uimm4 (f-sub4 12) pcrel17a2)
+ (if (lt rn (zext SI uimm4))
+ (set-vliw-alignment-modified pc pcrel17a2))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec)
+ (unit u-branch))))
+
+(dnci bgei "branch greater than immediate" (RELAXABLE)
+ "bgei $rn,$uimm4,$pcrel17a2"
+ (+ MAJ_14 rn uimm4 (f-sub4 8) pcrel17a2)
+ (if (ge rn (zext SI uimm4))
+ (set-vliw-alignment-modified pc pcrel17a2))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec)
+ (unit u-branch))))
+
+(dnci beq "branch equal" ()
+ "beq $rn,$rm,$pcrel17a2"
+ (+ MAJ_14 rn rm (f-sub4 1) pcrel17a2)
+ (if (eq rn rm)
+ (set-vliw-alignment-modified pc pcrel17a2))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-branch))))
+
+(dnci bne "branch not equal" ()
+ "bne $rn,$rm,$pcrel17a2"
+ (+ MAJ_14 rn rm (f-sub4 5) pcrel17a2)
+ (if (ne rn rm)
+ (set-vliw-alignment-modified pc pcrel17a2))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-branch))))
+
+(dnci bsr12 "branch to subroutine (12 bit displacement)" (RELAXABLE)
+ "bsr $pcrel12a2"
+ (+ MAJ_11 pcrel12a2 (f-15 1))
+ (sequence ()
+ (cg-profile pc pcrel12a2)
+ (set-vliw-modified-pcrel-offset lp 2 4 8)
+ (set-vliw-alignment-modified pc pcrel12a2))
+ ((mep (unit u-exec)
+ (unit u-branch))))
+
+(dnci bsr24 "branch to subroutine (24 bit displacement)" ()
+ "bsr $pcrel24a2"
+ (+ MAJ_13 (f-4 1) (f-sub4 9) pcrel24a2)
+ (sequence ()
+ (cg-profile pc pcrel24a2)
+ (set-vliw-modified-pcrel-offset lp 4 4 8)
+ (set-vliw-alignment-modified pc pcrel24a2))
+ ((mep (unit u-exec)
+ (unit u-branch))))
+
+(dnci jmp "jump" ()
+ "jmp $rm"
+ (+ MAJ_1 (f-rn 0) rm (f-sub4 14))
+ (sequence ()
+ (if (eq (get-psw.om) 0)
+ ;; core mode
+ (if (get-rm.lsb)
+ (sequence ()
+ (set-psw.om 1) ;; enter VLIW mode
+ (set-vliw-aliignment-modified-by-option pc rm))
+ (set pc (and rm (inv 1))))
+ ;; VLIW mode
+ (if (get-rm.lsb)
+ (sequence ()
+ (set-psw.om 0) ;; enter core mode
+ (set pc (and rm (inv 1))))
+ (set-vliw-aliignment-modified-by-option pc rm)))
+ (cg-profile-jump pc rm))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-branch))))
+
+(dnci jmp24 "jump (24 bit target)" ()
+ "jmp $pcabs24a2"
+ (+ MAJ_13 (f-4 1) (f-sub4 8) pcabs24a2)
+ (sequence ()
+ (set-vliw-alignment-modified pc (or (and pc #xf0000000) pcabs24a2))
+ (cg-profile-jump pc pcabs24a2))
+ ((mep (unit u-exec)
+ (unit u-branch))))
+
+(dnci jsr "jump to subroutine" ()
+ "jsr $rm"
+ (+ MAJ_1 (f-rn 0) rm (f-sub4 15))
+ (sequence ()
+ (cg-profile pc rm)
+ (set-vliw-modified-pcrel-offset lp 2 4 8)
+ (set-vliw-alignment-modified pc rm))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-branch))))
+
+(dnci ret "return from subroutine" ((STALL RET))
+ "ret"
+ (+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 2))
+ (sequence ()
+ (if (eq (get-psw.om) 0)
+ ;; core mode
+ (if (get-lp.ltom) ;; link-pointer "toggle mode" bit
+ (sequence ()
+ (set-psw.om 1) ;; enter VLIW mode
+ (set-vliw-aliignment-modified-by-option pc lp))
+ (set pc (and lp (inv 1))))
+ ;; VLIW mode
+ (if (get-lp.ltom) ;; link-pointer "toggle mode" bit
+ (sequence ()
+ (set-psw.om 0) ;; enter VLIW mode
+ (set pc (and lp (inv 1))))
+ (set-vliw-aliignment-modified-by-option pc lp)))
+ (c-call VOID "notify_ret" pc))
+ ((mep (unit u-exec)
+ (unit u-branch))))
+
+\f
+; Repeat instructions.
+
+(dnci repeat "repeat specified repeat block" ()
+ "repeat $rn,$pcrel17a2"
+ (+ MAJ_14 rn (f-rm 0) (f-sub4 9) pcrel17a2)
+ (sequence ()
+ (set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8)
+ (set-vliw-alignment-modified (reg h-csr 5) pcrel17a2)
+ (set (reg h-csr 6) rn))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci erepeat "endless repeat" ()
+ "erepeat $pcrel17a2"
+ (+ MAJ_14 (f-rn 0) (f-rm 1) (f-sub4 9) pcrel17a2)
+ (sequence ()
+ (set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8)
+ (set-vliw-alignment-modified (reg h-csr 5) pcrel17a2)
+ (set-rpe.elr 1)
+ ; rpc may be undefined for erepeat
+ ; use 1 to trigger repeat logic in the sim's main loop
+ (set (reg h-csr 6) 1))
+ ())
+
+\f
+; Control instructions.
+
+;; special store variants
+
+(dnci stc_lp "store to control register lp" ((STALL STC))
+ "stc $rn,\\$lp"
+ (+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
+ (set lp rn)
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-store-ctrl-reg (out storereg lp))
+ (unit u-exec))))
+
+(dnci stc_hi "store to control register hi" ((STALL STC))
+ "stc $rn,\\$hi"
+ (+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
+ (set hi rn)
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-store-ctrl-reg (out storereg hi))
+ (unit u-exec))))
+
+(dnci stc_lo "store to control register lo" ((STALL STC))
+ "stc $rn,\\$lo"
+ (+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
+ (set lo rn)
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-store-ctrl-reg (out storereg lo))
+ (unit u-exec))))
+
+;; general store
+
+(dnci stc "store to control register" (VOLATILE (STALL STC))
+ "stc $rn,$csrn"
+ (+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 0))
+ (set csrn rn)
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-store-ctrl-reg (out storereg csrn))
+ (unit u-exec))))
+
+;; special load variants
+
+(dnci ldc_lp "load from control register lp" ((STALL LDC))
+ "ldc $rn,\\$lp"
+ (+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
+ (set rn lp)
+ ((mep (unit u-use-ctrl-reg (in usereg lp))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rn)))))
+
+
+(dnci ldc_hi "load from control register hi" ((STALL LDC))
+ "ldc $rn,\\$hi"
+ (+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
+ (set rn hi)
+ ((mep (unit u-use-ctrl-reg (in usereg hi))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rn)))))
+
+(dnci ldc_lo "load from control register lo" ((STALL LDC))
+ "ldc $rn,\\$lo"
+ (+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
+ (set rn lo)
+ ((mep (unit u-use-ctrl-reg (in usereg lo))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rn)))))
+
+;; general load
+
+(dnci ldc "load from control register" (VOLATILE (STALL LDC) (LATENCY 2))
+ "ldc $rn,$csrn"
+ (+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 1))
+ (if (eq (ifield f-csrn) 0)
+ ;; loading from the pc
+ (set-vliw-modified-pcrel-offset rn 2 4 8)
+ ;; loading from something else
+ (set rn csrn))
+ ((mep (unit u-use-ctrl-reg (in usereg csrn))
+ (unit u-exec)
+ (unit u-load-gpr (out loadreg rn)))))
+
+(dnci di "disable interrupt" (VOLATILE)
+ "di"
+ (+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 0))
+ ; clear psw.iec
+ (set psw (sll (srl psw 1) 1))
+ ())
+
+(dnci ei "enable interrupt" (VOLATILE)
+ "ei"
+ (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 0))
+ ; set psw.iec
+ (set psw (or psw 1))
+ ())
+
+(dnci reti "return from interrupt" ((STALL RET))
+ "reti"
+ (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 2))
+ (if (eq (get-psw.om) 0)
+ ;; core operation mode
+ (if (get-psw.nmi)
+ ;; return from NMI
+ (if (get-npc.ntom)
+ ;; return in VLIW operation mode
+ (sequence ()
+ (set-psw.om 1)
+ (set-vliw-aliignment-modified-by-option pc npc)
+ (set-psw.nmi 0))
+ ;; return in core mode
+ (sequence ()
+ (set pc (and npc (inv 1)))
+ (set-psw.nmi 0)))
+ ;; return from non-NMI
+ (if (get-epc.etom)
+ ;; return in VLIW mode
+ (sequence ()
+ (set-psw.om 1)
+ (set-vliw-aliignment-modified-by-option pc epc)
+ (set-psw.umc (get-psw.ump))
+ (set-psw.iec (get-psw.iep)))
+ ;; return in core mode
+ (sequence ()
+ (set pc (and epc (inv 1)))
+ (set-psw.umc (get-psw.ump))
+ (set-psw.iec (get-psw.iep)))))
+ ;; VLIW operation mode
+ ;; xxx undefined
+ (nop))
+ ((mep (unit u-exec)
+ (unit u-branch))))
+
+(dnci halt "halt pipeline" (VOLATILE)
+ "halt"
+ (+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 2))
+ ; set psw.halt
+ (set (raw-reg h-csr 16) (or psw (sll 1 11)))
+ ())
+
+(dnci sleep "sleep pipeline" (VOLATILE)
+ "sleep"
+ (+ MAJ_7 (f-rn 0) (f-rm 6) (f-sub4 2))
+ (c-call VOID "do_sleep")
+ ())
+
+(dnci swi "software interrupt" (MAY_TRAP VOLATILE)
+ "swi $uimm2"
+ (+ MAJ_7 (f-rn 0) (f-8 0) (f-9 0) uimm2 (f-sub4 6))
+ (cond
+ ((eq uimm2 0) (set exc (or exc (sll 1 4))))
+ ((eq uimm2 1) (set exc (or exc (sll 1 5))))
+ ((eq uimm2 2) (set exc (or exc (sll 1 6))))
+ ((eq uimm2 3) (set exc (or exc (sll 1 7)))))
+ ())
+
+(dnci break "break exception" (MAY_TRAP VOLATILE)
+ "break"
+ (+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 2))
+ (set pc (c-call USI "break_exception" pc))
+ ((mep (unit u-exec)
+ (unit u-branch))))
+
+(dnci syncm "synchronise with memory" (VOLATILE)
+ "syncm"
+ (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 1))
+ (unimp "syncm")
+ ())
+
+(dnci stcb "store in control bus space" (VOLATILE (STALL STCB))
+ "stcb $rn,$uimm16"
+ (+ MAJ_15 rn (f-rm 0) (f-sub4 4) uimm16)
+ (c-call VOID "do_stcb" rn uimm16)
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec)
+ (unit u-stcb))))
+
+(dnci ldcb "load from control bus space" (VOLATILE (STALL LDCB) (LATENCY 3))
+ "ldcb $rn,$uimm16"
+ (+ MAJ_15 rn (f-rm 1) (f-sub4 4) uimm16)
+ (set rn (c-call SI "do_ldcb" uimm16))
+ ((mep (unit u-ldcb)
+ (unit u-exec)
+ (unit u-ldcb-gpr (out loadreg rn)))))
+
+\f
+; Bit manipulation instructions.
+; The following instructions become the reserved instruction when the
+; bit manipulation option is off.
+
+(dnci bsetm "set bit in memory" (OPTIONAL_BIT_INSN)
+ "bsetm ($rma),$uimm3"
+ (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 0))
+ (sequence ()
+ (c-call "check_option_bit" pc)
+ (set (mem UQI rma) (or (mem UQI rma) (sll 1 uimm3))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci bclrm "clear bit in memory" (OPTIONAL_BIT_INSN)
+ "bclrm ($rma),$uimm3"
+ (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 1))
+ (sequence ()
+ (c-call "check_option_bit" pc)
+ (set (mem UQI rma) (and (mem UQI rma) (inv (sll 1 uimm3)))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci bnotm "toggle bit in memory" (OPTIONAL_BIT_INSN)
+ "bnotm ($rma),$uimm3"
+ (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 2))
+ (sequence ()
+ (c-call "check_option_bit" pc)
+ (set (mem UQI rma) (xor (mem UQI rma) (sll 1 uimm3))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci btstm "test bit in memory" (OPTIONAL_BIT_INSN)
+ "btstm \\$0,($rma),$uimm3"
+ (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 3))
+ (sequence ()
+ (c-call "check_option_bit" pc)
+ (set r0 (zext SI (and UQI (mem UQI rma) (sll 1 uimm3)))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci tas "test and set" (OPTIONAL_BIT_INSN)
+ "tas $rn,($rma)"
+ (+ MAJ_2 rn rma (f-sub4 4))
+ (sequence ((SI result))
+ (c-call "check_option_bit" pc)
+ (set result (zext SI (mem UQI rma)))
+ (set (mem UQI rma) 1)
+ (set rn result))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+\f
+; Data cache instruction.
+
+(dnci cache "cache operations" (VOLATILE)
+ "cache $cimm4,($rma)"
+ (+ MAJ_7 cimm4 rma (f-sub4 4))
+ (c-call VOID "do_cache" cimm4 rma pc)
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+\f
+; Multiply instructions.
+; These instructions become the RI when the 32-bit multiply
+; instruction option is off.
+
+(dnci mul "multiply" (OPTIONAL_MUL_INSN (STALL MUL))
+ "mul $rn,$rm"
+ (+ MAJ_1 rn rm (f-sub4 4))
+ (sequence ((DI result))
+ (c-call "check_option_mul" pc)
+ (set result (mul (ext DI rn) (ext DI rm)))
+ (set hi (subword SI result 0))
+ (set lo (subword SI result 1)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-multiply))))
+
+(dnci mulu "multiply unsigned" (OPTIONAL_MUL_INSN (STALL MUL))
+ "mulu $rn,$rm"
+ (+ MAJ_1 rn rm (f-sub4 5))
+ (sequence ((DI result))
+ (c-call "check_option_mul" pc)
+ (set result (mul (zext UDI rn) (zext UDI rm)))
+ (set hi (subword SI result 0))
+ (set lo (subword SI result 1)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-multiply))))
+
+(dnci mulr "multiply, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
+ "mulr $rn,$rm"
+ (+ MAJ_1 rn rm (f-sub4 6))
+ (sequence ((DI result))
+ (c-call "check_option_mul" pc)
+ (set result (mul (ext DI rn) (ext DI rm)))
+ (set hi (subword SI result 0))
+ (set lo (subword SI result 1))
+ (set rn (subword SI result 1)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-multiply)
+ (unit u-mul-gpr (out resultreg rn)))))
+
+(dnci mulru "multiply unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
+ "mulru $rn,$rm"
+ (+ MAJ_1 rn rm (f-sub4 7))
+ (sequence ((DI result))
+ (c-call "check_option_mul" pc)
+ (set result (mul (zext UDI rn) (zext UDI rm)))
+ (set hi (subword SI result 0))
+ (set lo (subword SI result 1))
+ (set rn (subword SI result 1)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-multiply)
+ (unit u-mul-gpr (out resultreg rn)))))
+
+(dnci madd "multiply accumulate" (OPTIONAL_MUL_INSN (STALL MUL))
+ "madd $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3004))
+ (sequence ((DI result))
+ (c-call "check_option_mul" pc)
+ (set result (or (sll (zext DI hi) 32) (zext DI lo)))
+ (set result (add result (mul (ext DI rn) (ext DI rm))))
+ (set hi (subword SI result 0))
+ (set lo (subword SI result 1)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-multiply))))
+
+(dnci maddu "multiply accumulate unsigned" (OPTIONAL_MUL_INSN (STALL MUL))
+ "maddu $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3005))
+ (sequence ((DI result))
+ (c-call "check_option_mul" pc)
+ (set result (or (sll (zext DI hi) 32) (zext DI lo)))
+ (set result (add result (mul (zext UDI rn) (zext UDI rm))))
+ (set hi (subword SI result 0))
+ (set lo (subword SI result 1)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-multiply))))
+
+
+(dnci maddr "multiply accumulate, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
+ "maddr $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3006))
+ (sequence ((DI result))
+ (c-call "check_option_mul" pc)
+ (set result (or (sll (zext DI hi) 32) (zext DI lo)))
+ (set result (add result (mul (ext DI rn) (ext DI rm))))
+ (set hi (subword SI result 0))
+ (set lo (subword SI result 1))
+ (set rn (subword SI result 1)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-multiply)
+ (unit u-mul-gpr (out resultreg rn)))))
+
+(dnci maddru "multiple accumulate unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
+ "maddru $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3007))
+ (sequence ((DI result))
+ (c-call "check_option_mul" pc)
+ (set result (or (sll (zext DI hi) 32) (zext DI lo)))
+ (set result (add result (mul (zext UDI rn) (zext UDI rm))))
+ (set hi (subword SI result 0))
+ (set lo (subword SI result 1))
+ (set rn (subword SI result 1)))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-multiply)
+ (unit u-mul-gpr (out resultreg rn)))))
+
+\f
+; Divide instructions.
+; These instructions become the RI when the 32-bit divide instruction
+; option is off.
+
+(dnci div "divide" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP)
+ "div $rn,$rm"
+ (+ MAJ_1 rn rm (f-sub4 8))
+ (sequence ()
+ (c-call "check_option_div" pc)
+ (if (eq rm 0)
+ (set pc (c-call USI "zdiv_exception" pc))
+ ; Special case described on p. 76.
+ (if (and (eq rn #x80000000)
+ (eq rm #xffffffff))
+ (sequence ()
+ (set lo #x80000000)
+ (set hi 0))
+ (sequence ()
+ (set lo (div rn rm))
+ (set hi (mod rn rm))))))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-divide)
+ (unit u-branch))))
+
+(dnci divu "divide unsigned" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP)
+ "divu $rn,$rm"
+ (+ MAJ_1 rn rm (f-sub4 9))
+ (sequence ()
+ (c-call "check_option_div" pc)
+ (if (eq rm 0)
+ (set pc (c-call USI "zdiv_exception" pc))
+ (sequence ()
+ (set lo (udiv rn rm))
+ (set hi (umod rn rm)))))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-divide)
+ (unit u-branch))))
+
+\f
+; Debug functions.
+; These instructions become the RI when the debug function option is
+; off.
+
+(dnci dret "return from debug exception" (OPTIONAL_DEBUG_INSN)
+ "dret"
+ (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 3))
+ (sequence ()
+ (c-call "check_option_debug" pc)
+ ; set DBG.DM.
+ (set dbg (and dbg (inv (sll SI 1 15))))
+ (set pc depc))
+ ((mep (unit u-exec)
+ (unit u-branch))))
+
+(dnci dbreak "generate debug exception" (OPTIONAL_DEBUG_INSN MAY_TRAP VOLATILE)
+ "dbreak"
+ (+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 3))
+ (sequence ()
+ (c-call "check_option_debug" pc)
+ ; set DBG.DPB.
+ (set dbg (or dbg 1)))
+ ())
+
+\f
+; Leading zero instruction.
+
+(dnci ldz "leading zeroes" (OPTIONAL_LDZ_INSN (STALL INT2))
+ "ldz $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 0))
+ (sequence ()
+ (c-call "check_option_ldz" pc)
+ (set rn (c-call SI "do_ldz" rm)))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec))))
+
+\f
+; Absolute difference instruction.
+
+(dnci abs "absolute difference" (OPTIONAL_ABS_INSN (STALL INT2))
+ "abs $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 3))
+ (sequence ()
+ (c-call "check_option_abs" pc)
+ (set rn (abs (sub rn rm))))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+\f
+; Average instruction.
+
+(dnci ave "average" (OPTIONAL_AVE_INSN (STALL INT2))
+ "ave $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 2))
+ (sequence ()
+ (c-call "check_option_ave" pc)
+ (set rn (sra (add (add rn rm) 1) 1)))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+\f
+; MIN/MAX instructions.
+
+(dnci min "minimum" (OPTIONAL_MINMAX_INSN (STALL INT2))
+ "min $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 4))
+ (sequence ()
+ (c-call "check_option_minmax" pc)
+ (if (gt rn rm)
+ (set rn rm)))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci max "maximum" (OPTIONAL_MINMAX_INSN (STALL INT2))
+ "max $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 5))
+ (sequence ()
+ (c-call "check_option_minmax" pc)
+ (if (lt rn rm)
+ (set rn rm)))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci minu "minimum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2))
+ "minu $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 6))
+ (sequence ()
+ (c-call "check_option_minmax" pc)
+ (if (gtu rn rm)
+ (set rn rm)))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci maxu "maximum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2))
+ "maxu $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 7))
+ (sequence ()
+ (c-call "check_option_minmax" pc)
+ (if (ltu rn rm)
+ (set rn rm)))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+\f
+; Clipping instruction.
+
+(dnci clip "clip" (OPTIONAL_CLIP_INSN (STALL INT2))
+ "clip $rn,$cimm5"
+ (+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 0))
+ (sequence ((SI min) (SI max))
+ (c-call "check_option_clip" pc)
+ (set max (sub (sll 1 (sub cimm5 1)) 1))
+ (set min (neg (sll 1 (sub cimm5 1))))
+ (cond
+ ((eq cimm5 0) (set rn 0))
+ ((gt rn max) (set rn max))
+ ((lt rn min) (set rn min))))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci clipu "clip unsigned" (OPTIONAL_CLIP_INSN (STALL INT2))
+ "clipu $rn,$cimm5"
+ (+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 1))
+ (sequence ((SI max))
+ (c-call "check_option_clip" pc)
+ (set max (sub (sll 1 cimm5) 1))
+ (cond
+ ((eq cimm5 0) (set rn 0))
+ ((gt rn max) (set rn max))
+ ((lt rn 0) (set rn 0))))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+\f
+; Saturation instructions.
+
+(dnci sadd "saturating addition" (OPTIONAL_SAT_INSN (STALL INT2))
+ "sadd $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 8))
+ (sequence ()
+ (c-call "check_option_sat" pc)
+ (if (add-oflag rn rm 0)
+ (if (nflag rn)
+ ; underflow
+ (set rn (neg (sll 1 31)))
+ ; overflow
+ (set rn (sub (sll 1 31) 1)))
+ (set rn (add rn rm))))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci ssub "saturating subtraction" (OPTIONAL_SAT_INSN (STALL INT2))
+ "ssub $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 10))
+ (sequence ()
+ (c-call "check_option_sat" pc)
+ (if (sub-oflag rn rm 0)
+ (if (nflag rn)
+ ; underflow
+ (set rn (neg (sll 1 31)))
+ ; overflow
+ (set rn (sub (sll 1 31) 1)))
+ (set rn (sub rn rm))))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci saddu "saturating unsigned addition" (OPTIONAL_SAT_INSN (STALL INT2))
+ "saddu $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 9))
+ (sequence ()
+ (c-call "check_option_sat" pc)
+ (if (add-cflag rn rm 0)
+ (set rn (inv 0))
+ (set rn (add rn rm))))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnci ssubu "saturating unsigned subtraction" (OPTIONAL_SAT_INSN (STALL INT2))
+ "ssubu $rn,$rm"
+ (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 11))
+ (sequence ()
+ (c-call "check_option_sat" pc)
+ (if (sub-cflag rn rm 0)
+ (set rn 0)
+ (set rn (sub rn rm))))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+\f
+; UCI and DSP options are defined in an external file.
+; See `mep-sample-ucidsp.cpu' for a sample.
+
+\f
+; Coprocessor instructions.
+
+(dnci swcp "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
+ "swcp $crn,($rma)"
+ (+ MAJ_3 crn rma (f-sub4 8))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
+ (set (mem SI (and rma (inv SI 3))) crn))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lwcp "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
+ "lwcp $crn,($rma)"
+ (+ MAJ_3 crn rma (f-sub4 9))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (mem SI (and rma (inv SI 3)))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci smcp "smcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
+ "smcp $crn64,($rma)"
+ (+ MAJ_3 crn64 rma (f-sub4 10))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "check_option_cp64" pc)
+ (c-call VOID "check_write_to_text" rma)
+ (c-call "do_smcp" rma crn64 pc))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lmcp "lmcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
+ "lmcp $crn64,($rma)"
+ (+ MAJ_3 crn64 rma (f-sub4 11))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "check_option_cp64" pc)
+ (set crn64 (c-call DI "do_lmcp" rma pc)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci swcpi "swcp (post-increment)" (OPTIONAL_CP_INSN (STALL STORE))
+ "swcpi $crn,($rma+)"
+ (+ MAJ_3 crn rma (f-sub4 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
+ (set (mem SI (and rma (inv SI 3))) crn)
+ (set rma (add rma 4)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lwcpi "lwcp (post-increment)" (OPTIONAL_CP_INSN (STALL LOAD))
+ "lwcpi $crn,($rma+)"
+ (+ MAJ_3 crn rma (f-sub4 1))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (mem SI (and rma (inv SI 3))))
+ (set rma (add rma 4)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci smcpi "smcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
+ "smcpi $crn64,($rma+)"
+ (+ MAJ_3 crn64 rma (f-sub4 2))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "check_option_cp64" pc)
+ (c-call VOID "check_write_to_text" rma)
+ (c-call "do_smcpi" (index-of rma) crn64 pc)
+ (set rma rma)) ; reference as output for intrinsic generation
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lmcpi "lmcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
+ "lmcpi $crn64,($rma+)"
+ (+ MAJ_3 crn64 rma (f-sub4 3))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "check_option_cp64" pc)
+ (set crn64 (c-call DI "do_lmcpi" (index-of rma) pc))
+ (set rma rma)) ; reference as output for intrinsic generation
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci swcp16 "swcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL STORE))
+ "swcp $crn,$sdisp16($rma)"
+ (+ MAJ_15 crn rma (f-sub4 12) sdisp16)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set (mem SI (and (add rma sdisp16) (inv SI 3))) crn))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lwcp16 "lwcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL LOAD))
+ "lwcp $crn,$sdisp16($rma)"
+ (+ MAJ_15 crn rma (f-sub4 13) sdisp16)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (mem SI (and (add rma sdisp16) (inv SI 3)))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci smcp16 "smcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
+ "smcp $crn64,$sdisp16($rma)"
+ (+ MAJ_15 crn64 rma (f-sub4 14) sdisp16)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "check_option_cp64" pc)
+ (c-call "do_smcp16" rma sdisp16 crn64 pc))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lmcp16 "lmcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
+ "lmcp $crn64,$sdisp16($rma)"
+ (+ MAJ_15 crn64 rma (f-sub4 15) sdisp16)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "check_option_cp64" pc)
+ (set crn64 (c-call DI "do_lmcp16" rma sdisp16 pc)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci sbcpa "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
+ "sbcpa $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 0) (f-ext62 0) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" rma)
+ (set (mem QI rma) (and crn #xff))
+ (set rma (add rma (ext SI cdisp10))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbcpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
+ "lbcpa $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x0) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem QI rma)))
+ (set rma (add rma (ext SI cdisp10))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci shcpa "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
+ "shcpa $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x0) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (and rma (inv SI 1)))
+ (set (mem HI (and rma (inv SI 1))) (and crn #xffff))
+ (set rma (add rma (ext SI cdisp10a2))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhcpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
+ "lhcpa $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x0) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem HI (and rma (inv SI 1)))))
+ (set rma (add rma (ext SI cdisp10a2))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci swcpa "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
+ "swcpa $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x0) cdisp10a4)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
+ (set (mem SI (and rma (inv SI 3))) crn)
+ (set rma (add rma (ext SI cdisp10a4))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lwcpa "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
+ "lwcpa $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x0) cdisp10a4)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (mem SI (and rma (inv SI 3))))
+ (set rma (add rma (ext SI cdisp10a4))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci smcpa "smcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
+ "smcpa $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x0) cdisp10a8)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "check_option_cp64" pc)
+ (c-call VOID "check_write_to_text" rma)
+ (c-call "do_smcpa" (index-of rma) cdisp10a8 crn64 pc)
+ (set rma rma)) ; reference as output for intrinsic generation
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lmcpa "lmcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
+ "lmcpa $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x0) cdisp10a8)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "check_option_cp64" pc)
+ (set crn64 (c-call DI "do_lmcpa" (index-of rma) cdisp10a8 pc))
+ (set rma rma)) ; reference as output for intrinsic generation
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+\f
+(dnci sbcpm0 "sbcpm0" (OPTIONAL_CP_INSN)
+ "sbcpm0 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x2) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" rma)
+ (set (mem QI rma) (and crn #xff))
+ (set rma (mod0 cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbcpm0 "lbcpm0" (OPTIONAL_CP_INSN)
+ "lbcpm0 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x2) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem QI rma)))
+ (set rma (mod0 cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci shcpm0 "shcpm0" (OPTIONAL_CP_INSN)
+ "shcpm0 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x2) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (and rma (inv SI 1)))
+ (set (mem HI (and rma (inv SI 1))) (and crn #xffff))
+ (set rma (mod0 cdisp10a2)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhcpm0 "lhcpm0" (OPTIONAL_CP_INSN)
+ "lhcpm0 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x2) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem HI (and rma (inv SI 1)))))
+ (set rma (mod0 cdisp10a2)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci swcpm0 "swcpm0" (OPTIONAL_CP_INSN)
+ "swcpm0 $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x2) cdisp10a4)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
+ (set (mem SI (and rma (inv SI 3))) crn)
+ (set rma (mod0 cdisp10a4)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lwcpm0 "lwcpm0" (OPTIONAL_CP_INSN)
+ "lwcpm0 $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x2) cdisp10a4)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (mem SI (and rma (inv SI 3))))
+ (set rma (mod0 cdisp10a4)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci smcpm0 "smcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
+ "smcpm0 $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x2) cdisp10a8)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "check_option_cp64" pc)
+ (c-call VOID "check_write_to_text" rma)
+ (c-call "do_smcp" rma crn64 pc)
+ (set rma (mod0 cdisp10a8)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lmcpm0 "lmcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
+ "lmcpm0 $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x2) cdisp10a8)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "check_option_cp64" pc)
+ (set crn64 (c-call DI "do_lmcp" rma pc))
+ (set rma (mod0 cdisp10a8)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci sbcpm1 "sbcpm1" (OPTIONAL_CP_INSN)
+ "sbcpm1 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x3) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" rma)
+ (set (mem QI rma) (and crn #xff))
+ (set rma (mod1 cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbcpm1 "lbcpm1" (OPTIONAL_CP_INSN)
+ "lbcpm1 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x3) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem QI rma)))
+ (set rma (mod1 cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci shcpm1 "shcpm1" (OPTIONAL_CP_INSN)
+ "shcpm1 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x3) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (and rma (inv SI 1)))
+ (set (mem HI (and rma (inv SI 1))) (and crn #xffff))
+ (set rma (mod1 cdisp10a2)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhcpm1 "lhcpm1" (OPTIONAL_CP_INSN)
+ "lhcpm1 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x3) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem HI (and rma (inv SI 1)))))
+ (set rma (mod1 cdisp10a2)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci swcpm1 "swcpm1" (OPTIONAL_CP_INSN)
+ "swcpm1 $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x3) cdisp10a4)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
+ (set (mem SI (and rma (inv SI 3))) crn)
+ (set rma (mod1 cdisp10a4)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lwcpm1 "lwcpm1" (OPTIONAL_CP_INSN)
+ "lwcpm1 $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x3) cdisp10a4)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem SI (and rma (inv SI 3)))))
+ (set rma (mod1 cdisp10a4)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci smcpm1 "smcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
+ "smcpm1 $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x3) cdisp10a8)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "check_option_cp64" pc)
+ (c-call "do_smcp" rma crn64 pc)
+ (c-call VOID "check_write_to_text" rma)
+ (set rma (mod1 cdisp10a8)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lmcpm1 "lmcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
+ "lmcpm1 $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x3) cdisp10a8)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "check_option_cp64" pc)
+ (set crn64 (c-call DI "do_lmcp" rma pc))
+ (set rma (mod1 cdisp10a8)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnop cp_flag "branch condition register" (all-mep-isas) h-ccr 1)
+
+(dnci bcpeq "branch coprocessor equal" (OPTIONAL_CP_INSN RELAXABLE)
+ "bcpeq $cccc,$pcrel17a2"
+ (+ MAJ_13 (f-rn 8) cccc (f-sub4 4) pcrel17a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (if (eq (xor cccc cp_flag) 0)
+ (set-vliw-alignment-modified pc pcrel17a2)))
+ ())
+
+(dnci bcpne "branch coprocessor not equal" (OPTIONAL_CP_INSN RELAXABLE)
+ "bcpne $cccc,$pcrel17a2"
+ (+ MAJ_13 (f-rn 8) cccc (f-sub4 5) pcrel17a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (if (ne (xor cccc cp_flag) 0)
+ (set-vliw-alignment-modified pc pcrel17a2)))
+ ())
+
+(dnci bcpat "branch coprocessor and true" (OPTIONAL_CP_INSN RELAXABLE)
+ "bcpat $cccc,$pcrel17a2"
+ (+ MAJ_13 (f-rn 8) cccc (f-sub4 6) pcrel17a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (if (ne (and cccc cp_flag) 0)
+ (set-vliw-alignment-modified pc pcrel17a2)))
+ ())
+
+(dnci bcpaf "branch coprocessor and false" (OPTIONAL_CP_INSN RELAXABLE)
+ "bcpaf $cccc,$pcrel17a2"
+ (+ MAJ_13 (f-rn 8) cccc (f-sub4 7) pcrel17a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (if (eq (and cccc cp_flag) 0)
+ (set-vliw-alignment-modified pc pcrel17a2)))
+ ())
+
+(dnci synccp "synchronise with coprocessor" (OPTIONAL_CP_INSN)
+ "synccp"
+ (+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 1))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (unimp "synccp"))
+ ())
+
+(dnci jsrv "jump to vliw subroutine " (OPTIONAL_CP_INSN)
+ "jsrv $rm"
+ (+ MAJ_1 (f-rn 8) rm (f-sub4 15))
+ (sequence ()
+ (cg-profile pc rm)
+ (c-call "check_option_cp" pc)
+ (core-vliw-switch
+
+ ;; in core operating mode
+ (sequence ()
+ (set lp (or (add pc 2) 1))
+ (set-vliw-aliignment-modified-by-option pc rm)
+ (set-psw.om 1)) ;; to VLIW operation mode
+
+ ;; in VLIW32 operating mode
+ (sequence ()
+ (set lp (or (add pc 4) 1))
+ (set pc (and rm (inv 1)))
+ (set-psw.om 0)) ;; to core operation mode
+
+ ;; in VLIW64 operating mode
+ (sequence ()
+ (set lp (or (add pc 8) 1))
+ (set pc (and rm (inv 1)))
+ (set-psw.om 0)))) ;; to core operation mode
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-exec)
+ (unit u-branch))))
+
+(dnci bsrv "branch to vliw subroutine" (OPTIONAL_CP_INSN)
+ "bsrv $pcrel24a2"
+ (+ MAJ_13 (f-4 1) (f-sub4 11) pcrel24a2)
+ (sequence ()
+ (cg-profile pc pcrel24a2)
+ (c-call "check_option_cp" pc)
+ (core-vliw-switch
+
+ ;; in core operating mode
+ (sequence ()
+ (set lp (or (add pc 4) 1))
+ (set-vliw-aliignment-modified-by-option pc pcrel24a2)
+ (set-psw.om 1)) ;; to VLIW operation mode
+
+ ;; in VLIW32 operating mode
+ (sequence ()
+ (set lp (or (add pc 4) 1))
+ (set pc (and pcrel24a2 (inv 1)))
+ (set-psw.om 0)) ;; to core operation mode
+
+ ;; in VLIW64 operating mode
+ (sequence ()
+ (set lp (or (add pc 8) 1))
+ (set pc (and pcrel24a2 (inv 1)))
+ (set-psw.om 0)))) ;; to core operation mode
+ ((mep (unit u-exec)
+ (unit u-branch))))
+
+\f
+; An instruction for test instrumentation.
+; Using a reserved opcode.
+
+(dnci sim-syscall "simulator system call" ()
+ "--syscall--"
+ (+ MAJ_7 (f-4 1) callnum (f-8 0) (f-9 0) (f-10 0) (f-sub4 0))
+ (c-call "do_syscall" pc callnum)
+ ())
+
+(define-pmacro (dnri n major minor)
+ (dnci (.sym ri- n) "reserved instruction" ()
+ "--reserved--"
+ (+ major rn rm (f-sub4 minor))
+ (set pc (c-call USI "ri_exception" pc))
+ ((mep (unit u-exec)
+ (unit u-branch)))))
+
+(dnri 0 MAJ_0 6)
+(dnri 1 MAJ_1 10)
+(dnri 2 MAJ_1 11)
+(dnri 3 MAJ_2 5)
+(dnri 4 MAJ_2 8)
+(dnri 5 MAJ_2 9)
+(dnri 6 MAJ_2 10)
+(dnri 7 MAJ_2 11)
+(dnri 8 MAJ_3 4)
+(dnri 9 MAJ_3 5)
+(dnri 10 MAJ_3 6)
+(dnri 11 MAJ_3 7)
+(dnri 12 MAJ_3 12)
+(dnri 13 MAJ_3 13)
+(dnri 14 MAJ_3 14)
+(dnri 15 MAJ_3 15)
+(dnri 17 MAJ_7 7)
+(dnri 20 MAJ_7 14)
+(dnri 21 MAJ_7 15)
+(dnri 22 MAJ_12 7)
+(dnri 23 MAJ_14 13)
+;(dnri 24 MAJ_15 3)
+(dnri 26 MAJ_15 8)
+; begin core-specific reserved insns
+; end core-specific reserved insns
+
+\f
+; Macro instructions.
+
+(dnmi nop "nop"
+ ()
+ "nop"
+ (emit mov (rn 0) (rm 0)))
+
+; Emit the 16 bit form of these 32 bit insns when the displacement is zero.
+;
+(dncmi sb16-0 "store byte (explicit 16 bit displacement of zero)" (NO-DIS)
+ "sb $rnc,$zero($rma)"
+ (emit sb rnc rma))
+
+(dncmi sh16-0 "store half (explicit 16 bit displacement of zero)" (NO-DIS)
+ "sh $rns,$zero($rma)"
+ (emit sh rns rma))
+
+(dncmi sw16-0 "store word (explicit 16 bit displacement of zero)" (NO-DIS)
+ "sw $rnl,$zero($rma)"
+ (emit sw rnl rma))
+
+(dncmi lb16-0 "load byte (explicit 16 bit displacement of zero)" (NO-DIS)
+ "lb $rnc,$zero($rma)"
+ (emit lb rnc rma))
+
+(dncmi lh16-0 "load half (explicit 16 bit displacement of zero)" (NO-DIS)
+ "lh $rns,$zero($rma)"
+ (emit lh rns rma))
+
+(dncmi lw16-0 "load word (explicit 16 bit displacement of zero)" (NO-DIS)
+ "lw $rnl,$zero($rma)"
+ (emit lw rnl rma))
+
+(dncmi lbu16-0 "load unsigned byte (explicit 16 bit displacement of zero)" (NO-DIS)
+ "lbu $rnuc,$zero($rma)"
+ (emit lbu rnuc rma))
+
+(dncmi lhu16-0 "load unsigned half (explicit 16 bit displacement of zero)" (NO-DIS)
+ "lhu $rnus,$zero($rma)"
+ (emit lhu rnus rma))
+
+(dncmi swcp16-0 "swcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS)
+ "swcp $crn,$zero($rma)"
+ (emit swcp crn rma))
+
+(dncmi lwcp16-0 "lwcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS)
+ "lwcp $crn,$zero($rma)"
+ (emit lwcp crn rma))
+
+(dncmi smcp16-0 "smcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS)
+ "smcp $crn64,$zero($rma)"
+ (emit smcp crn64 rma))
+
+(dncmi lmcp16-0 "lmcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS)
+ "lmcp $crn64,$zero($rma)"
+ (emit lmcp crn64 rma))
--- /dev/null
+; Toshiba MeP Media Engine architecture description. -*- Scheme -*-
+; Copyright (C) 2001 Red Hat, Inc.
+; This file is part of CGEN.
+; See file COPYING.CGEN for details.
+
+; This file serves as a wrapper to bring in the core description plus
+; sample implementations of the UCI and DSP instructions.
+
+(include "mep-core.cpu")
+(include "mep-ext-cop.cpu")
--- /dev/null
+; Toshiba MeP Media Engine architecture description. -*- Scheme -*-
+; Copyright (C) 2003 Red Hat, Inc.
+; This file is part of CGEN.
+; See file COPYING.CGEN for details.
+
+;; begin-user-isa-includes
+(include "mep-ivc2.cpu")
+;; end-user-isa-includes
--- /dev/null
+
+
+/* DO NOT EDIT: This file is automatically generated by CGEN.
+ Any changes you make will be discarded when it is next regenerated. */
+
+#ifdef WANT_GCC_DECLARATIONS
+#define FIRST_SHADOW_REGISTER 113
+#define LAST_SHADOW_REGISTER 140
+#define FIXED_SHADOW_REGISTERS \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
+#define CALL_USED_SHADOW_REGISTERS FIXED_SHADOW_REGISTERS
+#define SHADOW_REG_ALLOC_ORDER \
+ 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140
+#define SHADOW_REGISTER_NAMES \
+ "$shadow87", "$shadow107", "$shadow106", "$shadow105", "$shadow104", "$shadow111", "$shadow110", "$shadow109", "$shadow108", "$shadow84", "$shadow81", "$shadow86", "$shadow99", "$shadow98", "$shadow97", "$shadow96", "$shadow103", "$shadow102", "$shadow101", "$shadow100", "$shadow17", "$shadow40", "$shadow24", "$shadow23", "$shadow22", "$shadow21", "$shadow20", "$shadow18"
+
+
+
+#ifndef __MEP__
+enum {
+ mep_fcmpleis = 597,
+ mep_fcmplis = 599,
+ mep_fcmpes = 601,
+ mep_fcmpules = 603,
+ mep_fcmpuls = 605,
+ mep_fcmpues = 607,
+ mep_fcmpus = 609,
+ mep_fcvtsw = 611,
+ mep_ftruncws = 613,
+ mep_fnegs = 615,
+ mep_fabss = 617,
+ mep_fsqrts = 619,
+ mep_fdivs = 621,
+ mep_fmuls = 623,
+ mep_fsubs = 625,
+ mep_fadds = 627,
+ mep_fmovs = 629,
+ mep_cextb = 630,
+ mep_cexth = 631,
+ mep_cextub = 632,
+ mep_cextuh = 633,
+ mep_xmula0 = 634,
+ mep_cmula0 = 635,
+ mep_cneg = 636,
+ mep_cmovh2 = 638,
+ mep_cmovh1 = 639,
+ mep_cmovc2 = 640,
+ mep_cmovc1 = 641,
+ mep_cmov2 = 642,
+ mep_cmov1 = 643,
+ mep_cmovi = 644,
+ mep_cpmov = 646,
+ mep_cmov = 647,
+ mep_csrai3 = 648,
+ mep_csrai = 650,
+ mep_csra3 = 652,
+ mep_csra = 654,
+ mep_csrli3 = 656,
+ mep_csrli = 658,
+ mep_csrl3 = 660,
+ mep_csrl = 662,
+ mep_cslli3 = 664,
+ mep_cslli = 666,
+ mep_csll3 = 668,
+ mep_csll = 670,
+ mep_cxori3 = 672,
+ mep_cxori = 674,
+ mep_cxor3 = 676,
+ mep_cxor = 678,
+ mep_cnori3 = 680,
+ mep_cnori = 682,
+ mep_cnor3 = 684,
+ mep_cnor = 686,
+ mep_cori3 = 688,
+ mep_cori = 690,
+ mep_cor3 = 692,
+ mep_cor = 694,
+ mep_candi3 = 696,
+ mep_candi = 698,
+ mep_cand3 = 700,
+ mep_cand = 702,
+ mep_csubi3 = 704,
+ mep_csubi = 706,
+ mep_csub3 = 708,
+ mep_csub = 710,
+ mep_caddi3 = 712,
+ mep_caddi = 714,
+ mep_cadd3 = 716,
+ mep_cadd = 718
+};
+#endif /* ! defined (__MEP__) */
+
+
+enum cgen_regnum_operand_type {
+ cgen_regnum_operand_type_POINTER, /* long * */
+ cgen_regnum_operand_type_LABEL, /* void * */
+ cgen_regnum_operand_type_LONG, /* long */
+ cgen_regnum_operand_type_ULONG, /* unsigned long */
+ cgen_regnum_operand_type_SHORT, /* short */
+ cgen_regnum_operand_type_USHORT, /* unsigned short */
+ cgen_regnum_operand_type_CHAR, /* char */
+ cgen_regnum_operand_type_UCHAR, /* unsigned char */
+ cgen_regnum_operand_type_SI, /* __cop long */
+ cgen_regnum_operand_type_DI, /* __cop long long */
+ cgen_regnum_operand_type_CP_DATA_BUS_INT, /* cp_data_bus_int */
+ cgen_regnum_operand_type_VECTOR, /* opaque vector type */
+ cgen_regnum_operand_type_V8QI, /* V8QI vector type */
+ cgen_regnum_operand_type_V4HI, /* V4HI vector type */
+ cgen_regnum_operand_type_V2SI, /* V2SI vector type */
+ cgen_regnum_operand_type_V8UQI, /* V8UQI vector type */
+ cgen_regnum_operand_type_V4UHI, /* V4UHI vector type */
+ cgen_regnum_operand_type_V2USI, /* V2USI vector type */
+ cgen_regnum_operand_type_DEFAULT = cgen_regnum_operand_type_LONG
+};
+
+struct cgen_regnum_operand {
+ /* The number of addressable registers, 0 for non-regnum operands. */
+ unsigned char count;
+
+ /* The first register. */
+ unsigned char base;
+
+ /* The type of the operand. */
+ enum cgen_regnum_operand_type type;
+
+ /* Is it passed by reference? */
+ int reference_p;
+};
+
+struct cgen_insn {
+ /* An index into cgen_intrinsics[]. */
+ unsigned int intrinsic;
+
+ /* A bitmask of the ISAs which include this instruction. */
+ unsigned int isas;
+
+ /* A bitmask of the target-specific groups to which this instruction
+ belongs. */
+ unsigned int groups;
+
+ /* The insn_code for this instruction. */
+ int icode;
+
+ /* The number of arguments to the intrinsic function. */
+ unsigned int num_args;
+
+ /* If true, the first argument is the return value. */
+ unsigned int cret_p;
+
+ /* Maps operand numbers to argument numbers. */
+ unsigned int op_mapping[10];
+
+ /* Array of regnum properties, indexed by argument number. */
+ struct cgen_regnum_operand regnums[10];
+
+ /* The length of the instruction, in bytes. */
+ int length;
+};
+
+extern const struct cgen_insn cgen_insns[];
+extern const char *const cgen_intrinsics[];
+
+/* Is the instruction described by cgen_insns[INDEX] enabled? */
+#define CGEN_ENABLE_INSN_P(INDEX) \
+ ((CGEN_CURRENT_ISAS & cgen_insns[INDEX].isas) != 0 \
+ && (CGEN_CURRENT_GROUP & cgen_insns[INDEX].groups) != 0)
+
+#define ISA_EXT1 1
+#define ISA_MEP 2
+
+#define GROUP_KNOWN_CODE 1
+#define GROUP_NORMAL 2
+#define GROUP_VLIW 4
+
+#endif
+#ifdef WANT_GCC_DEFINITIONS
+struct cgen_immediate_predicate {
+ insn_operand_predicate_fn predicate;
+ int lower, upper, align;
+};
+
+const struct cgen_immediate_predicate cgen_immediate_predicates[] = {
+ { cgen_h_sint_12a1_immediate, -2048, 2048, 1 },
+ { cgen_h_uint_20a1_immediate, 0, 1048576, 1 },
+ { cgen_h_uint_7a1_immediate, 0, 128, 1 },
+ { cgen_h_uint_6a2_immediate, 0, 128, 2 },
+ { cgen_h_uint_22a4_immediate, 0, 33554432, 4 },
+ { cgen_h_sint_2a1_immediate, -2, 2, 1 },
+ { cgen_h_uint_24a1_immediate, 0, 16777216, 1 },
+ { cgen_h_sint_6a1_immediate, -32, 32, 1 },
+ { cgen_h_uint_5a4_immediate, 0, 256, 4 },
+ { cgen_h_uint_2a1_immediate, 0, 4, 1 },
+ { cgen_h_sint_10a1_immediate, -512, 512, 1 },
+ { cgen_h_uint_4a1_immediate, 0, 16, 1 },
+ { cgen_h_uint_6a1_immediate, 0, 64, 1 },
+ { cgen_h_uint_16a1_immediate, 0, 65536, 1 },
+ { cgen_h_uint_8a1_immediate, 0, 256, 1 },
+ { cgen_h_sint_16a1_immediate, -32768, 32768, 1 },
+ { cgen_h_uint_5a1_immediate, 0, 32, 1 },
+ { cgen_h_sint_8a1_immediate, -128, 128, 1 },
+ { cgen_h_uint_3a1_immediate, 0, 8, 1 }
+};
+
+const char *const cgen_intrinsics[] = {
+ "mep_cpfmadila1_h",
+ "mep_cpfmadiua1_h",
+ "mep_cpfmadia1_b",
+ "mep_cpfmadia1u_b",
+ "mep_cpfmulila1_h",
+ "mep_cpfmuliua1_h",
+ "mep_cpfmulia1_b",
+ "mep_cpfmulia1u_b",
+ "mep_cpamadila1_h",
+ "mep_cpamadiua1_h",
+ "mep_cpamadia1_b",
+ "mep_cpamadia1u_b",
+ "mep_cpamulila1_h",
+ "mep_cpamuliua1_h",
+ "mep_cpamulia1_b",
+ "mep_cpamulia1u_b",
+ "mep_cpfmadila1s1_h",
+ "mep_cpfmadiua1s1_h",
+ "mep_cpfmadia1s1_b",
+ "mep_cpfmadia1s1u_b",
+ "mep_cpfmulila1s1_h",
+ "mep_cpfmuliua1s1_h",
+ "mep_cpfmulia1s1_b",
+ "mep_cpfmulia1s1u_b",
+ "mep_cpfmadila1s0_h",
+ "mep_cpfmadiua1s0_h",
+ "mep_cpfmadia1s0_b",
+ "mep_cpfmadia1s0u_b",
+ "mep_cpfmulila1s0_h",
+ "mep_cpfmuliua1s0_h",
+ "mep_cpfmulia1s0_b",
+ "mep_cpfmulia1s0u_b",
+ "mep_cpacswp",
+ "mep_cpaccpa1",
+ "mep_cpacsuma1",
+ "mep_c1nop",
+ "mep_cpfacla0s1_h",
+ "mep_cpfacua0s1_h",
+ "mep_cpfaca0s1_b",
+ "mep_cpfaca0s1u_b",
+ "mep_cpfsftbla0s1_h",
+ "mep_cpfsftbua0s1_h",
+ "mep_cpfsftba0s1_b",
+ "mep_cpfsftba0s1u_b",
+ "mep_cpfacla0s0_h",
+ "mep_cpfacua0s0_h",
+ "mep_cpfaca0s0_b",
+ "mep_cpfaca0s0u_b",
+ "mep_cpfsftbla0s0_h",
+ "mep_cpfsftbua0s0_h",
+ "mep_cpfsftba0s0_b",
+ "mep_cpfsftba0s0u_b",
+ "mep_cpsllia0",
+ "mep_cpsraia0",
+ "mep_cpsrlia0",
+ "mep_cpslla0",
+ "mep_cpsraa0",
+ "mep_cpsrla0",
+ "mep_cpaccpa0",
+ "mep_cpacsuma0",
+ "mep_cpmovhla0_w",
+ "mep_cpmovhua0_w",
+ "mep_cppackla0_w",
+ "mep_cppackua0_w",
+ "mep_cppackla0_h",
+ "mep_cppackua0_h",
+ "mep_cppacka0_b",
+ "mep_cppacka0u_b",
+ "mep_cpmovlla0_w",
+ "mep_cpmovlua0_w",
+ "mep_cpmovula0_w",
+ "mep_cpmovuua0_w",
+ "mep_cpmovla0_h",
+ "mep_cpmovua0_h",
+ "mep_cpmova0_b",
+ "mep_cpsetla0_w",
+ "mep_cpsetua0_w",
+ "mep_cpseta0_h",
+ "mep_cpsadla0_h",
+ "mep_cpsadua0_h",
+ "mep_cpsada0_b",
+ "mep_cpsada0u_b",
+ "mep_cpabsla0_h",
+ "mep_cpabsua0_h",
+ "mep_cpabsa0_b",
+ "mep_cpabsa0u_b",
+ "mep_cpsubacla0_h",
+ "mep_cpsubacua0_h",
+ "mep_cpsubaca0_b",
+ "mep_cpsubaca0u_b",
+ "mep_cpsubla0_h",
+ "mep_cpsubua0_h",
+ "mep_cpsuba0_b",
+ "mep_cpsuba0u_b",
+ "mep_cpaddacla0_h",
+ "mep_cpaddacua0_h",
+ "mep_cpaddaca0_b",
+ "mep_cpaddaca0u_b",
+ "mep_cpaddla0_h",
+ "mep_cpaddua0_h",
+ "mep_cpadda0_b",
+ "mep_cpadda0u_b",
+ "mep_c0nop",
+ "mep_cpsmsbslla1_w",
+ "mep_cpsmsbslua1_w",
+ "mep_cpsmsbslla1_h",
+ "mep_cpsmsbslua1_h",
+ "mep_cpsmadslla1_w",
+ "mep_cpsmadslua1_w",
+ "mep_cpsmadslla1_h",
+ "mep_cpsmadslua1_h",
+ "mep_cpmulslla1_w",
+ "mep_cpmulslua1_w",
+ "mep_cpmulslla1_h",
+ "mep_cpmulslua1_h",
+ "mep_cpsmsbla1_w",
+ "mep_cpsmsbua1_w",
+ "mep_cpsmsbla1_h",
+ "mep_cpsmsbua1_h",
+ "mep_cpsmadla1_w",
+ "mep_cpsmadua1_w",
+ "mep_cpsmadla1_h",
+ "mep_cpsmadua1_h",
+ "mep_cpmsbla1_w",
+ "mep_cpmsbua1_w",
+ "mep_cpmsbla1u_w",
+ "mep_cpmsbua1u_w",
+ "mep_cpmsbla1_h",
+ "mep_cpmsbua1_h",
+ "mep_cpmadla1_w",
+ "mep_cpmadua1_w",
+ "mep_cpmadla1u_w",
+ "mep_cpmadua1u_w",
+ "mep_cpmadla1_h",
+ "mep_cpmadua1_h",
+ "mep_cpmada1_b",
+ "mep_cpmada1u_b",
+ "mep_cpmulla1_w",
+ "mep_cpmulua1_w",
+ "mep_cpmulla1u_w",
+ "mep_cpmulua1u_w",
+ "mep_cpmulla1_h",
+ "mep_cpmulua1_h",
+ "mep_cpmula1_b",
+ "mep_cpmula1u_b",
+ "mep_cpssda1_b",
+ "mep_cpssda1u_b",
+ "mep_cpssqa1_b",
+ "mep_cpssqa1u_b",
+ "mep_cpsllia1",
+ "mep_cpsraia1",
+ "mep_cpsrlia1",
+ "mep_cpslla1",
+ "mep_cpsraa1",
+ "mep_cpsrla1",
+ "mep_cpmovhla1_w",
+ "mep_cpmovhua1_w",
+ "mep_cppackla1_w",
+ "mep_cppackua1_w",
+ "mep_cppackla1_h",
+ "mep_cppackua1_h",
+ "mep_cppacka1_b",
+ "mep_cppacka1u_b",
+ "mep_cpmovlla1_w",
+ "mep_cpmovlua1_w",
+ "mep_cpmovula1_w",
+ "mep_cpmovuua1_w",
+ "mep_cpmovla1_h",
+ "mep_cpmovua1_h",
+ "mep_cpmova1_b",
+ "mep_cpsetla1_w",
+ "mep_cpsetua1_w",
+ "mep_cpseta1_h",
+ "mep_cpsadla1_h",
+ "mep_cpsadua1_h",
+ "mep_cpsada1_b",
+ "mep_cpsada1u_b",
+ "mep_cpabsla1_h",
+ "mep_cpabsua1_h",
+ "mep_cpabsa1_b",
+ "mep_cpabsa1u_b",
+ "mep_cpsubacla1_h",
+ "mep_cpsubacua1_h",
+ "mep_cpsubaca1_b",
+ "mep_cpsubaca1u_b",
+ "mep_cpsubla1_h",
+ "mep_cpsubua1_h",
+ "mep_cpsuba1_b",
+ "mep_cpsuba1u_b",
+ "mep_cpaddacla1_h",
+ "mep_cpaddacua1_h",
+ "mep_cpaddaca1_b",
+ "mep_cpaddaca1u_b",
+ "mep_cpaddla1_h",
+ "mep_cpaddua1_h",
+ "mep_cpadda1_b",
+ "mep_cpadda1u_b",
+ "mep_cdmovi",
+ "mep_cdmoviu",
+ "mep_cpmovi_w",
+ "mep_cpmoviu_w",
+ "mep_cpmovi_h",
+ "mep_cpmoviu_h",
+ "mep_cpmovi_b",
+ "mep_cdclipi3",
+ "mep_cdclipiu3",
+ "mep_cpclipi3_w",
+ "mep_cpclipiu3_w",
+ "mep_cpslai3_w",
+ "mep_cpslai3_h",
+ "mep_cdslli3",
+ "mep_cpslli3_w",
+ "mep_cpslli3_h",
+ "mep_cpslli3_b",
+ "mep_cdsrai3",
+ "mep_cpsrai3_w",
+ "mep_cpsrai3_h",
+ "mep_cpsrai3_b",
+ "mep_cdsrli3",
+ "mep_cpsrli3_w",
+ "mep_cpsrli3_h",
+ "mep_cpsrli3_b",
+ "mep_cpocmpge_w",
+ "mep_cpocmpgeu_w",
+ "mep_cpocmpge_h",
+ "mep_cpocmpge_b",
+ "mep_cpocmpgeu_b",
+ "mep_cpocmpgt_w",
+ "mep_cpocmpgtu_w",
+ "mep_cpocmpgt_h",
+ "mep_cpocmpgt_b",
+ "mep_cpocmpgtu_b",
+ "mep_cpocmpne_w",
+ "mep_cpocmpne_h",
+ "mep_cpocmpne_b",
+ "mep_cpocmpeq_w",
+ "mep_cpocmpeq_h",
+ "mep_cpocmpeq_b",
+ "mep_cpacmpge_w",
+ "mep_cpacmpgeu_w",
+ "mep_cpacmpge_h",
+ "mep_cpacmpge_b",
+ "mep_cpacmpgeu_b",
+ "mep_cpacmpgt_w",
+ "mep_cpacmpgtu_w",
+ "mep_cpacmpgt_h",
+ "mep_cpacmpgt_b",
+ "mep_cpacmpgtu_b",
+ "mep_cpacmpne_w",
+ "mep_cpacmpne_h",
+ "mep_cpacmpne_b",
+ "mep_cpacmpeq_w",
+ "mep_cpacmpeq_h",
+ "mep_cpacmpeq_b",
+ "mep_cpcmpge_w",
+ "mep_cpcmpgeu_w",
+ "mep_cpcmpge_h",
+ "mep_cpcmpge_b",
+ "mep_cpcmpgeu_b",
+ "mep_cpcmpgt_w",
+ "mep_cpcmpgtu_w",
+ "mep_cpcmpgt_h",
+ "mep_cpcmpgt_b",
+ "mep_cpcmpgtu_b",
+ "mep_cpcmpne_w",
+ "mep_cpcmpne_h",
+ "mep_cpcmpne_b",
+ "mep_cpcmpeq_w",
+ "mep_cpcmpeq_h",
+ "mep_cpcmpeq_b",
+ "mep_cpcmpeqz_b",
+ "mep_cdcastw",
+ "mep_cdcastuw",
+ "mep_cpcasth_w",
+ "mep_cpcastuh_w",
+ "mep_cpcastb_w",
+ "mep_cpcastub_w",
+ "mep_cpcastb_h",
+ "mep_cpcastub_h",
+ "mep_cpextl_h",
+ "mep_cpextlu_h",
+ "mep_cpextl_b",
+ "mep_cpextlu_b",
+ "mep_cpextu_h",
+ "mep_cpextuu_h",
+ "mep_cpextu_b",
+ "mep_cpextuu_b",
+ "mep_cpbcast_w",
+ "mep_cpbcast_h",
+ "mep_cpbcast_b",
+ "mep_cpccadd_b",
+ "mep_cphadd_w",
+ "mep_cphadd_h",
+ "mep_cphadd_b",
+ "mep_cphaddu_b",
+ "mep_cpnorm_w",
+ "mep_cpnorm_h",
+ "mep_cpldz_w",
+ "mep_cpldz_h",
+ "mep_cpabsz_w",
+ "mep_cpabsz_h",
+ "mep_cpabsz_b",
+ "mep_cpmovtocc",
+ "mep_cpmovtocsar1",
+ "mep_cpmovtocsar0",
+ "mep_cpmovfrcc",
+ "mep_cpmovfrcsar1",
+ "mep_cpmovfrcsar0",
+ "mep_cpmin3_w",
+ "mep_cpminu3_w",
+ "mep_cpmin3_h",
+ "mep_cpmin3_b",
+ "mep_cpminu3_b",
+ "mep_cpmax3_w",
+ "mep_cpmaxu3_w",
+ "mep_cpmax3_h",
+ "mep_cpmax3_b",
+ "mep_cpmaxu3_b",
+ "mep_cpabs3_h",
+ "mep_cpabs3_b",
+ "mep_cpabsu3_b",
+ "mep_cpaddsr3_w",
+ "mep_cpaddsr3_h",
+ "mep_cpaddsr3_b",
+ "mep_cpaddsru3_b",
+ "mep_cpave3_w",
+ "mep_cpave3_h",
+ "mep_cpave3_b",
+ "mep_cpaveu3_b",
+ "mep_cpextlsub3_b",
+ "mep_cpextlsubu3_b",
+ "mep_cpextusub3_b",
+ "mep_cpextusubu3_b",
+ "mep_cpextladd3_b",
+ "mep_cpextladdu3_b",
+ "mep_cpextuadd3_b",
+ "mep_cpextuaddu3_b",
+ "mep_cpssub3_w",
+ "mep_cpssub3_h",
+ "mep_cpsadd3_w",
+ "mep_cpsadd3_h",
+ "mep_cpsla3_w",
+ "mep_cpsla3_h",
+ "mep_cdsll3",
+ "mep_cpssll3_w",
+ "mep_cpsll3_w",
+ "mep_cpssll3_h",
+ "mep_cpsll3_h",
+ "mep_cpssll3_b",
+ "mep_cpsll3_b",
+ "mep_cdsra3",
+ "mep_cpssra3_w",
+ "mep_cpsra3_w",
+ "mep_cpssra3_h",
+ "mep_cpsra3_h",
+ "mep_cpssra3_b",
+ "mep_cpsra3_b",
+ "mep_cdsrl3",
+ "mep_cpssrl3_w",
+ "mep_cpsrl3_w",
+ "mep_cpssrl3_h",
+ "mep_cpsrl3_h",
+ "mep_cpssrl3_b",
+ "mep_cpsrl3_b",
+ "mep_cppack_h",
+ "mep_cppack_b",
+ "mep_cppacku_b",
+ "mep_cpunpackl_w",
+ "mep_cpunpackl_h",
+ "mep_cpunpackl_b",
+ "mep_cpunpacku_w",
+ "mep_cpunpacku_h",
+ "mep_cpunpacku_b",
+ "mep_cpfsftbs1",
+ "mep_cpfsftbs0",
+ "mep_cpfsftbi",
+ "mep_cpsel",
+ "mep_cpxor3",
+ "mep_cpnor3",
+ "mep_cpor3",
+ "mep_cpand3",
+ "mep_cdsub3",
+ "mep_cpsub3_w",
+ "mep_cpsub3_h",
+ "mep_cpsub3_b",
+ "mep_cdadd3",
+ "mep_cpadd3_w",
+ "mep_cpadd3_h",
+ "mep_cpadd3_b",
+ "mep_cmovh_rn_crm_p0",
+ "mep_cmovh_crn_rm_p0",
+ "mep_cmovc_rn_ccrm_p0",
+ "mep_cmovc_ccrn_rm_p0",
+ "mep_cmov_rn_crm_p0",
+ "mep_cmov_crn_rm_p0",
+ "mep_bsrv",
+ "mep_jsrv",
+ "mep_synccp",
+ "mep_bcpaf",
+ "mep_bcpat",
+ "mep_bcpne",
+ "mep_bcpeq",
+ "mep_lmcpm1",
+ "mep_smcpm1",
+ "mep_lwcpm1",
+ "mep_swcpm1",
+ "mep_lhcpm1",
+ "mep_shcpm1",
+ "mep_lbcpm1",
+ "mep_sbcpm1",
+ "mep_lmcpm0",
+ "mep_smcpm0",
+ "mep_lwcpm0",
+ "mep_swcpm0",
+ "mep_lhcpm0",
+ "mep_shcpm0",
+ "mep_lbcpm0",
+ "mep_sbcpm0",
+ "mep_lmcpa",
+ "mep_smcpa",
+ "mep_lwcpa",
+ "mep_swcpa",
+ "mep_lhcpa",
+ "mep_shcpa",
+ "mep_lbcpa",
+ "mep_sbcpa",
+ "mep_lmcp16",
+ "mep_smcp16",
+ "mep_lwcp16",
+ "mep_swcp16",
+ "mep_lmcpi",
+ "mep_smcpi",
+ "mep_lwcpi",
+ "mep_swcpi",
+ "mep_lmcp",
+ "mep_smcp",
+ "mep_lwcp",
+ "mep_swcp",
+ "mep_ssubu",
+ "mep_saddu",
+ "mep_ssub",
+ "mep_sadd",
+ "mep_clipu",
+ "mep_clip",
+ "mep_maxu",
+ "mep_minu",
+ "mep_max",
+ "mep_min",
+ "mep_ave",
+ "mep_abs",
+ "mep_ldz",
+ "mep_dbreak",
+ "mep_dret",
+ "mep_divu",
+ "mep_div",
+ "mep_maddru",
+ "mep_maddr",
+ "mep_maddu",
+ "mep_madd",
+ "mep_mulru",
+ "mep_mulr",
+ "mep_mulu",
+ "mep_mul",
+ "mep_cache",
+ "mep_tas",
+ "mep_btstm",
+ "mep_bnotm",
+ "mep_bclrm",
+ "mep_bsetm",
+ "mep_ldcb",
+ "mep_stcb",
+ "mep_syncm",
+ "mep_break",
+ "mep_swi",
+ "mep_sleep",
+ "mep_halt",
+ "mep_reti",
+ "mep_ei",
+ "mep_di",
+ "mep_ldc",
+ "mep_ldc_lo",
+ "mep_ldc_hi",
+ "mep_ldc_lp",
+ "mep_stc",
+ "mep_stc_lo",
+ "mep_stc_hi",
+ "mep_stc_lp",
+ "mep_erepeat",
+ "mep_repeat",
+ "mep_ret",
+ "mep_jsr",
+ "mep_jmp24",
+ "mep_jmp",
+ "mep_bsr24",
+ "mep_bsr12",
+ "mep_bne",
+ "mep_beq",
+ "mep_bgei",
+ "mep_blti",
+ "mep_bnei",
+ "mep_beqi",
+ "mep_bnez",
+ "mep_beqz",
+ "mep_bra",
+ "mep_fsft",
+ "mep_sll3",
+ "mep_slli",
+ "mep_srli",
+ "mep_srai",
+ "mep_sll",
+ "mep_srl",
+ "mep_sra",
+ "mep_xor3",
+ "mep_and3",
+ "mep_or3",
+ "mep_nor",
+ "mep_xor",
+ "mep_and",
+ "mep_or",
+ "mep_sltu3x",
+ "mep_slt3x",
+ "mep_add3x",
+ "mep_sl2ad3",
+ "mep_sl1ad3",
+ "mep_sltu3i",
+ "mep_slt3i",
+ "mep_sltu3",
+ "mep_slt3",
+ "mep_neg",
+ "mep_sbvck3",
+ "mep_sub",
+ "mep_advck3",
+ "mep_add3i",
+ "mep_add",
+ "mep_add3",
+ "mep_movh",
+ "mep_movu16",
+ "mep_movu24",
+ "mep_movi16",
+ "mep_movi8",
+ "mep_mov",
+ "mep_ssarb",
+ "mep_extuh",
+ "mep_extub",
+ "mep_exth",
+ "mep_extb",
+ "mep_lw24",
+ "mep_sw24",
+ "mep_lhu16",
+ "mep_lbu16",
+ "mep_lw16",
+ "mep_lh16",
+ "mep_lb16",
+ "mep_sw16",
+ "mep_sh16",
+ "mep_sb16",
+ "mep_lhu_tp",
+ "mep_lbu_tp",
+ "mep_lw_tp",
+ "mep_lh_tp",
+ "mep_lb_tp",
+ "mep_sw_tp",
+ "mep_sh_tp",
+ "mep_sb_tp",
+ "mep_lw_sp",
+ "mep_sw_sp",
+ "mep_lhu",
+ "mep_lbu",
+ "mep_lw",
+ "mep_lh",
+ "mep_lb",
+ "mep_sw",
+ "mep_sh",
+ "mep_sb",
+ "mep_dsp1",
+ "mep_dsp0",
+ "mep_dsp",
+ "mep_uci",
+ "mep_lhucpm1",
+ "mep_lbucpm1",
+ "mep_lhucpm0",
+ "mep_lbucpm0",
+ "mep_lhucpa",
+ "mep_lbucpa",
+ "mep_lhucp",
+ "mep_lhcp",
+ "mep_shcp",
+ "mep_lbucp",
+ "mep_lbcp",
+ "mep_sbcp",
+ "mep_casw3",
+ "mep_cash3",
+ "mep_casb3",
+ "mep_prefd",
+ "mep_pref",
+ "mep_ldcb_r",
+ "mep_stcb_r",
+ "mep_fcmpleis",
+ "mep_fcmpleis",
+ "mep_fcmplis",
+ "mep_fcmplis",
+ "mep_fcmpes",
+ "mep_fcmpes",
+ "mep_fcmpules",
+ "mep_fcmpules",
+ "mep_fcmpuls",
+ "mep_fcmpuls",
+ "mep_fcmpues",
+ "mep_fcmpues",
+ "mep_fcmpus",
+ "mep_fcmpus",
+ "mep_fcvtsw",
+ "mep_fcvtsw",
+ "mep_ftruncws",
+ "mep_ftruncws",
+ "mep_fnegs",
+ "mep_fnegs",
+ "mep_fabss",
+ "mep_fabss",
+ "mep_fsqrts",
+ "mep_fsqrts",
+ "mep_fdivs",
+ "mep_fdivs",
+ "mep_fmuls",
+ "mep_fmuls",
+ "mep_fsubs",
+ "mep_fsubs",
+ "mep_fadds",
+ "mep_fadds",
+ "mep_fmovs",
+ "mep_cextb",
+ "mep_cexth",
+ "mep_cextub",
+ "mep_cextuh",
+ "mep_xmula0",
+ "mep_cmula0",
+ "mep_cneg",
+ "mep_cneg",
+ "mep_cmovh2",
+ "mep_cmovh1",
+ "mep_cmovc2",
+ "mep_cmovc1",
+ "mep_cmov2",
+ "mep_cmov1",
+ "mep_cmovi",
+ "mep_cmovi",
+ "mep_cpmov",
+ "mep_cmov",
+ "mep_csrai3",
+ "mep_csrai3",
+ "mep_csrai",
+ "mep_csrai",
+ "mep_csra3",
+ "mep_csra3",
+ "mep_csra",
+ "mep_csra",
+ "mep_csrli3",
+ "mep_csrli3",
+ "mep_csrli",
+ "mep_csrli",
+ "mep_csrl3",
+ "mep_csrl3",
+ "mep_csrl",
+ "mep_csrl",
+ "mep_cslli3",
+ "mep_cslli3",
+ "mep_cslli",
+ "mep_cslli",
+ "mep_csll3",
+ "mep_csll3",
+ "mep_csll",
+ "mep_csll",
+ "mep_cxori3",
+ "mep_cxori3",
+ "mep_cxori",
+ "mep_cxori",
+ "mep_cxor3",
+ "mep_cxor3",
+ "mep_cxor",
+ "mep_cxor",
+ "mep_cnori3",
+ "mep_cnori3",
+ "mep_cnori",
+ "mep_cnori",
+ "mep_cnor3",
+ "mep_cnor3",
+ "mep_cnor",
+ "mep_cnor",
+ "mep_cori3",
+ "mep_cori3",
+ "mep_cori",
+ "mep_cori",
+ "mep_cor3",
+ "mep_cor3",
+ "mep_cor",
+ "mep_cor",
+ "mep_candi3",
+ "mep_candi3",
+ "mep_candi",
+ "mep_candi",
+ "mep_cand3",
+ "mep_cand3",
+ "mep_cand",
+ "mep_cand",
+ "mep_csubi3",
+ "mep_csubi3",
+ "mep_csubi",
+ "mep_csubi",
+ "mep_csub3",
+ "mep_csub3",
+ "mep_csub",
+ "mep_csub",
+ "mep_caddi3",
+ "mep_caddi3",
+ "mep_caddi",
+ "mep_caddi",
+ "mep_cadd3",
+ "mep_cadd3",
+ "mep_cadd",
+ "mep_cadd"
+};
+
+const struct cgen_insn cgen_insns[] = {
+ { 103,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmsbslla1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 103,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmsbslla1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 104,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmsbslua1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 104,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmsbslua1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 105,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmsbslla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 105,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmsbslla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 106,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmsbslua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 106,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmsbslua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 107,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmadslla1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 107,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmadslla1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 108,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmadslua1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 108,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmadslua1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 109,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmadslla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 109,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmadslla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 110,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmadslua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 110,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmadslua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 111,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmulslla1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 111,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmulslla1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 112,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmulslua1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 112,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmulslua1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 113,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmulslla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 113,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmulslla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 114,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmulslua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 114,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmulslua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 115,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmsbla1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 115,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmsbla1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 116,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmsbua1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 116,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmsbua1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 117,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmsbla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 117,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmsbla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 118,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmsbua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 118,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmsbua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 119,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmadla1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 119,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmadla1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 120,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmadua1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 120,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmadua1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 121,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmadla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 121,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmadla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 122,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsmadua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 122,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsmadua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 123,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmsbla1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 123,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmsbla1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 124,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmsbua1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 124,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmsbua1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 125,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmsbla1u_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 125,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmsbla1u_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 126,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmsbua1u_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 126,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmsbua1u_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 127,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmsbla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 127,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmsbla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 128,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmsbua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 128,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmsbua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 129,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmadla1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 129,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmadla1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 130,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmadua1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 130,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmadua1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 131,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmadla1u_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 131,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmadla1u_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 132,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmadua1u_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 132,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmadua1u_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 133,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmadla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 133,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmadla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 134,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmadua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 134,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmadua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 135,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmada1_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 135,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmada1_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 136,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmada1u_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 136,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmada1u_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 137,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmulla1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 137,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmulla1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 138,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmulua1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 138,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmulua1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 139,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmulla1u_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 139,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmulla1u_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 140,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmulua1u_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 140,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmulua1u_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 141,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmulla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 141,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmulla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 142,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmulua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 142,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmulua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 143,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmula1_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 143,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmula1_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 144,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmula1u_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 144,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmula1u_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 145,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssda1_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 145,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssda1_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 146,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssda1u_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 146,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssda1u_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 147,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssqa1_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 147,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssqa1_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 148,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssqa1u_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 148,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssqa1u_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 0,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmadila1_h_P1,
+ 4,
+ 0,
+ { 0, 1, 2, 3 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 1,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmadiua1_h_P1,
+ 4,
+ 0,
+ { 0, 1, 2, 3 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 2,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmadia1_b_P1,
+ 4,
+ 0,
+ { 0, 1, 2, 3 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 3,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmadia1u_b_P1,
+ 4,
+ 0,
+ { 0, 1, 2, 3 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 4,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmulila1_h_P1,
+ 4,
+ 0,
+ { 0, 1, 2, 3 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 5,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmuliua1_h_P1,
+ 4,
+ 0,
+ { 0, 1, 2, 3 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 6,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmulia1_b_P1,
+ 4,
+ 0,
+ { 0, 1, 2, 3 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 7,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmulia1u_b_P1,
+ 4,
+ 0,
+ { 0, 1, 2, 3 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 8,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpamadila1_h_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 9,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpamadiua1_h_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 10,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpamadia1_b_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 11,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpamadia1u_b_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 12,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpamulila1_h_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 13,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpamuliua1_h_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 14,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpamulia1_b_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 15,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpamulia1u_b_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 16,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmadila1s1_h_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 17,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmadiua1s1_h_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 18,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmadia1s1_b_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 19,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmadia1s1u_b_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 20,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmulila1s1_h_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 21,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmuliua1s1_h_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 22,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmulia1s1_b_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 23,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmulia1s1u_b_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 24,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmadila1s0_h_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 25,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmadiua1s0_h_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 26,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmadia1s0_b_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 27,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmadia1s0u_b_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 28,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmulila1s0_h_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 29,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmuliua1s0_h_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 30,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmulia1s0_b_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 31,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfmulia1s0u_b_P1,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 149,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsllia1_P1,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 149,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsllia1_1_p1,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 150,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsraia1_P1,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 150,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsraia1_1_p1,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 151,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsrlia1_P1,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 151,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrlia1_1_p1,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 152,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpslla1_C3,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 152,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpslla1_P1,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 153,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsraa1_C3,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 153,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsraa1_P1,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 154,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsrla1_C3,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 154,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrla1_P1,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 32,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacswp_P1,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 4 },
+ { 33,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaccpa1_P1,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 4 },
+ { 34,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacsuma1_P1,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 4 },
+ { 155,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovhla1_w_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 155,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovhla1_w_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 156,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovhua1_w_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 156,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovhua1_w_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 157,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cppackla1_w_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 157,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppackla1_w_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 158,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cppackua1_w_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 158,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppackua1_w_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 159,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cppackla1_h_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 } },
+ 4 },
+ { 159,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppackla1_h_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 } },
+ 4 },
+ { 160,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cppackua1_h_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 } },
+ 4 },
+ { 160,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppackua1_h_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 } },
+ 4 },
+ { 161,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cppacka1_b_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 } },
+ 4 },
+ { 161,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppacka1_b_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 } },
+ 4 },
+ { 162,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cppacka1u_b_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 } },
+ 4 },
+ { 162,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppacka1u_b_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 } },
+ 4 },
+ { 163,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovlla1_w_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 163,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovlla1_w_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 164,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovlua1_w_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 164,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovlua1_w_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 165,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovula1_w_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 165,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovula1_w_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 166,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovuua1_w_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 166,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovuua1_w_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 167,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovla1_h_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 } },
+ 4 },
+ { 167,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovla1_h_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 } },
+ 4 },
+ { 168,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovua1_h_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 } },
+ 4 },
+ { 168,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovua1_h_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 } },
+ 4 },
+ { 169,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmova1_b_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 } },
+ 4 },
+ { 169,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmova1_b_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 } },
+ 4 },
+ { 170,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsetla1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 170,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsetla1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 171,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsetua1_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 171,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsetua1_w_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 172,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpseta1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 172,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpseta1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 173,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsadla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 173,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsadla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 174,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsadua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 174,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsadua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 175,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsada1_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 175,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsada1_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 176,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsada1u_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 176,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsada1u_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 177,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpabsla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 177,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabsla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 178,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpabsua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 178,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabsua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 179,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpabsa1_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 179,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabsa1_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 180,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpabsa1u_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 180,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabsa1u_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 181,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsubacla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 181,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsubacla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 182,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsubacua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 182,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsubacua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 183,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsubaca1_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 183,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsubaca1_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 184,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsubaca1u_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 184,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsubaca1u_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 185,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsubla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 185,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsubla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 186,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsubua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 186,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsubua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 187,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsuba1_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 187,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsuba1_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 188,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsuba1u_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 188,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsuba1u_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 189,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpaddacla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 189,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddacla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 190,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpaddacua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 190,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddacua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 191,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpaddaca1_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 191,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddaca1_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 192,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpaddaca1u_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 192,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddaca1u_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 193,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpaddla1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 193,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddla1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 194,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpaddua1_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 194,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddua1_h_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 195,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpadda1_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 195,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpadda1_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 196,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpadda1u_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 196,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpadda1u_b_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 203,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovi_b_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 203,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovi_b_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 35,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_c1nop_P1,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 4 },
+ { 197,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdmovi_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 197,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdmovi_P0_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 198,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdmoviu_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 198,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdmoviu_P0_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 199,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovi_w_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 199,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovi_w_P0_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 200,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmoviu_w_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 200,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmoviu_w_P0_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 201,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovi_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 201,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovi_h_P0_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 204,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdclipi3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 204,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdclipi3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 205,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdclipiu3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 205,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdclipiu3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 206,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpclipi3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 206,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpclipi3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 207,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpclipiu3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 207,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpclipiu3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 208,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpslai3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 208,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpslai3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 209,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpslai3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 209,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpslai3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 210,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdslli3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 210,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdslli3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 211,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpslli3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 211,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpslli3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 212,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpslli3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 212,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpslli3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 213,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpslli3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 213,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpslli3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 214,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdsrai3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 214,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdsrai3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 215,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsrai3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 215,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrai3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 216,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsrai3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 216,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrai3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 217,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsrai3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 217,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrai3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 218,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdsrli3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 218,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdsrli3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 219,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsrli3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 219,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrli3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 220,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsrli3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 220,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrli3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 221,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsrli3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 221,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrli3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 341,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsla3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 341,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsla3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 342,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsla3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 342,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsla3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 343,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdsll3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 343,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdsll3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 344,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssll3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 344,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssll3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 345,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsll3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 345,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsll3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 346,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssll3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 346,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssll3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 347,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsll3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 347,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsll3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 348,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssll3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 348,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssll3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 349,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsll3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 349,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsll3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 350,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdsra3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 350,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdsra3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 351,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssra3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 351,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssra3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 352,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsra3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 352,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsra3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 353,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssra3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 353,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssra3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 354,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsra3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 354,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsra3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 355,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssra3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 355,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssra3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 356,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsra3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 356,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsra3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 357,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdsrl3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 357,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdsrl3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 358,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssrl3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 358,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssrl3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 359,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsrl3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 359,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrl3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 360,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssrl3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 360,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssrl3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 361,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsrl3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 361,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrl3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 362,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssrl3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 362,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssrl3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 363,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsrl3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 363,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrl3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 308,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmin3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 308,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmin3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 309,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpminu3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 309,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpminu3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 310,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmin3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 310,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmin3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 311,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmin3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 311,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmin3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 312,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpminu3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 312,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpminu3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 313,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmax3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 313,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmax3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 314,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmaxu3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 314,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmaxu3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 315,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmax3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 315,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmax3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 316,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmax3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 316,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmax3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 317,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmaxu3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 317,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmaxu3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 364,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cppack_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 364,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppack_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 365,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cppack_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 365,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppack_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 366,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cppacku_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 366,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppacku_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 377,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpxor3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_VECTOR, 1 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 } },
+ 4 },
+ { 377,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpxor3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_VECTOR, 1 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 } },
+ 4 },
+ { 378,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpnor3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_VECTOR, 1 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 } },
+ 4 },
+ { 378,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpnor3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_VECTOR, 1 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 } },
+ 4 },
+ { 379,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpor3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_VECTOR, 1 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 } },
+ 4 },
+ { 379,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpor3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_VECTOR, 1 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 } },
+ 4 },
+ { 380,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpand3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_VECTOR, 1 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 } },
+ 4 },
+ { 380,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpand3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_VECTOR, 1 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 }, { 0, 0, cgen_regnum_operand_type_VECTOR, 0 } },
+ 4 },
+ { 318,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpabs3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 318,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabs3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 319,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpabs3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 319,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabs3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 320,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpabsu3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 320,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabsu3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 321,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpaddsr3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 321,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddsr3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 322,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpaddsr3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 322,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddsr3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 323,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpaddsr3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 323,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddsr3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 324,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpaddsru3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 324,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddsru3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 325,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpave3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 325,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpave3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 326,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpave3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 326,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpave3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 327,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpave3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 327,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpave3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 328,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpaveu3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 328,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaveu3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 329,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextlsub3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 329,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextlsub3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 330,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextlsubu3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 330,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextlsubu3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 331,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextusub3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 331,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextusub3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 332,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextusubu3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 332,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextusubu3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 333,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextladd3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 333,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextladd3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 334,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextladdu3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 334,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextladdu3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 335,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextuadd3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 335,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextuadd3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 336,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextuaddu3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 336,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextuaddu3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 337,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssub3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 337,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssub3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 338,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpssub3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 338,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpssub3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 339,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsadd3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 339,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsadd3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 340,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsadd3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 340,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsadd3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 381,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdsub3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 381,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdsub3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 382,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsub3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 382,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsub3_w_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 383,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsub3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 383,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsub3_h_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 384,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsub3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 384,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsub3_b_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 385,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdadd3_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 385,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdadd3_P0_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 222,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpge_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 222,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpge_w_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 223,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpgeu_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 223,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpgeu_w_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 224,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpge_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 224,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpge_h_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 225,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpge_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 225,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpge_b_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 226,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpgeu_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 226,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpgeu_b_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 227,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpgt_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 227,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpgt_w_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 228,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpgtu_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 228,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpgtu_w_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 229,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpgt_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 229,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpgt_h_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 230,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpgt_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 230,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpgt_b_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 231,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpgtu_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 231,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpgtu_b_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 232,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpne_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 232,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpne_w_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 233,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpne_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 233,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpne_h_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 234,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpne_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 234,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpne_b_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 235,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpeq_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 235,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpeq_w_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 236,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpeq_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 236,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpeq_h_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 237,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpocmpeq_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 237,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpocmpeq_b_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 238,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpge_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 238,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpge_w_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 239,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpgeu_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 239,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpgeu_w_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 240,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpge_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 240,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpge_h_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 241,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpge_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 241,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpge_b_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 242,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpgeu_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 242,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpgeu_b_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 243,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpgt_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 243,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpgt_w_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 244,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpgtu_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 244,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpgtu_w_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 245,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpgt_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 245,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpgt_h_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 246,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpgt_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 246,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpgt_b_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 247,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpgtu_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 247,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpgtu_b_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 248,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpne_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 248,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpne_w_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 249,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpne_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 249,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpne_h_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 250,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpne_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 250,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpne_b_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 251,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpeq_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 251,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpeq_w_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 252,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpeq_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 252,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpeq_h_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 253,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpacmpeq_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 253,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacmpeq_b_P0_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 375,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpfsftbi_C3,
+ 4,
+ 1,
+ { 0, 1, 2, 3 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 375,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfsftbi_P0_P1,
+ 4,
+ 1,
+ { 0, 1, 2, 3 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 36,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfacla0s1_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 37,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfacua0s1_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 38,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfaca0s1_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 39,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfaca0s1u_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 40,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfsftbla0s1_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 41,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfsftbua0s1_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 42,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfsftba0s1_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 43,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfsftba0s1u_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 44,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfacla0s0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 45,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfacua0s0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 46,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfaca0s0_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 47,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfaca0s0u_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 48,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfsftbla0s0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 49,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfsftbua0s0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 50,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfsftba0s0_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 51,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfsftba0s0u_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 52,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsllia0_P0S,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 53,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsraia0_P0S,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 54,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrlia0_P0S,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 55,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpslla0_P0S,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 56,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsraa0_P0S,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 57,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsrla0_P0S,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 58,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaccpa0_P0S,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 4 },
+ { 59,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpacsuma0_P0S,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 4 },
+ { 60,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovhla0_w_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 61,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovhua0_w_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 62,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppackla0_w_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 63,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppackua0_w_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 64,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppackla0_h_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 } },
+ 4 },
+ { 65,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppackua0_h_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 } },
+ 4 },
+ { 66,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppacka0_b_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 } },
+ 4 },
+ { 67,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cppacka0u_b_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 } },
+ 4 },
+ { 68,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovlla0_w_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 69,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovlua0_w_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 70,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovula0_w_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 71,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovuua0_w_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 } },
+ 4 },
+ { 72,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovla0_h_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 } },
+ 4 },
+ { 73,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovua0_h_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 } },
+ 4 },
+ { 74,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmova0_b_P0S,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 } },
+ 4 },
+ { 75,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsetla0_w_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 76,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsetua0_w_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 77,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpseta0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 78,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsadla0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 79,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsadua0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 80,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsada0_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 81,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsada0u_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 82,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabsla0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 83,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabsua0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 84,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabsa0_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 85,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabsa0u_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 86,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsubacla0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 87,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsubacua0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 88,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsubaca0_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 89,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsubaca0u_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 90,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsubla0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 91,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsubua0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 92,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsuba0_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 93,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsuba0u_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 94,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddacla0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 95,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddacua0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 96,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddaca0_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 97,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddaca0u_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 98,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddla0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 99,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpaddua0_h_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 100,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpadda0_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 101,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpadda0u_b_P0S,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 254,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpge_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 254,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpge_w_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 255,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpgeu_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 255,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpgeu_w_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 256,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpge_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 256,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpge_h_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 257,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpge_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 257,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpge_b_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 258,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpgeu_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 258,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpgeu_b_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 259,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpgt_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 259,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpgt_w_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 260,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpgtu_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 260,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpgtu_w_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 261,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpgt_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 261,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpgt_h_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 262,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpgt_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 262,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpgt_b_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 263,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpgtu_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 263,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpgtu_b_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 264,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpne_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 264,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpne_w_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 265,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpne_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 265,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpne_h_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 266,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpne_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 266,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpne_b_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 267,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpeq_w_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 267,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpeq_w_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 268,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpeq_h_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 268,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpeq_h_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 269,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpeq_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 269,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpeq_b_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 270,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcmpeqz_b_C3,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 270,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcmpeqz_b_P0S_P1,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 302,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovtocc_C3,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 302,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovtocc_P0S_P1,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 303,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovtocsar1_C3,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 303,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovtocsar1_P0S_P1,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 304,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovtocsar0_C3,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 304,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovtocsar0_P0S_P1,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 305,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovfrcc_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 } },
+ 4 },
+ { 305,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovfrcc_P0S_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 } },
+ 4 },
+ { 306,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovfrcsar1_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 } },
+ 4 },
+ { 306,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovfrcsar1_P0S_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 } },
+ 4 },
+ { 307,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmovfrcsar0_C3,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 } },
+ 4 },
+ { 307,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmovfrcsar0_P0S_P1,
+ 1,
+ 1,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 } },
+ 4 },
+ { 271,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdcastw_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 271,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdcastw_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 272,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cdcastuw_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 272,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cdcastuw_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 273,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcasth_w_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 273,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcasth_w_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 274,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcastuh_w_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 274,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcastuh_w_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 275,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcastb_w_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 275,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcastb_w_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 276,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcastub_w_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 276,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcastub_w_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 277,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcastb_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 277,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcastb_h_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 278,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpcastub_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 278,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpcastub_h_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 279,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextl_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 279,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextl_h_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 280,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextlu_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4UHI, 1 }, { 0, 0, cgen_regnum_operand_type_V4UHI, 0 } },
+ 4 },
+ { 280,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextlu_h_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4UHI, 1 }, { 0, 0, cgen_regnum_operand_type_V4UHI, 0 } },
+ 4 },
+ { 281,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextl_b_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 281,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextl_b_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 282,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextlu_b_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 282,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextlu_b_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 283,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextu_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4UHI, 1 }, { 0, 0, cgen_regnum_operand_type_V4UHI, 0 } },
+ 4 },
+ { 283,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextu_h_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4UHI, 1 }, { 0, 0, cgen_regnum_operand_type_V4UHI, 0 } },
+ 4 },
+ { 284,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextuu_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4UHI, 1 }, { 0, 0, cgen_regnum_operand_type_V4UHI, 0 } },
+ 4 },
+ { 284,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextuu_h_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4UHI, 1 }, { 0, 0, cgen_regnum_operand_type_V4UHI, 0 } },
+ 4 },
+ { 285,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextu_b_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 285,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextu_b_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 286,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpextuu_b_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 286,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpextuu_b_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 287,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpbcast_w_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 287,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpbcast_w_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 288,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpbcast_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 288,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpbcast_h_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 289,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpbcast_b_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 289,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpbcast_b_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 290,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpccadd_b_C3,
+ 1,
+ 0,
+ { 0, 0 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 } },
+ 4 },
+ { 290,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpccadd_b_P0S_P1,
+ 1,
+ 0,
+ { 0, 0 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 } },
+ 4 },
+ { 291,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cphadd_w_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 291,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cphadd_w_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 292,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cphadd_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 292,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cphadd_h_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 293,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cphadd_b_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 293,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cphadd_b_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 294,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cphaddu_b_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 294,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cphaddu_b_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 295,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpnorm_w_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 295,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpnorm_w_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 296,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpnorm_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 296,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpnorm_h_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 297,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpldz_w_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 297,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpldz_w_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 298,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpldz_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 298,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpldz_h_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 299,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpabsz_w_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 299,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabsz_w_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 300,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpabsz_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 300,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabsz_h_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 301,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpabsz_b_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 301,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpabsz_b_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 646,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmov_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 646,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpmov_P0S_P1,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 373,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpfsftbs1_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 373,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfsftbs1_P0S_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 374,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpfsftbs0_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 374,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpfsftbs0_P0S_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 376,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpsel_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 376,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpsel_P0S_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 367,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpunpackl_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 367,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpunpackl_w_P0S_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 368,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpunpackl_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 368,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpunpackl_h_P0S_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 369,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpunpackl_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 369,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpunpackl_b_P0S_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 370,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpunpacku_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 1 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 370,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpunpacku_w_P0S_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2USI, 1 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 }, { 0, 0, cgen_regnum_operand_type_V2USI, 0 } },
+ 4 },
+ { 371,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpunpacku_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4UHI, 1 }, { 0, 0, cgen_regnum_operand_type_V4UHI, 0 }, { 0, 0, cgen_regnum_operand_type_V4UHI, 0 } },
+ 4 },
+ { 371,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpunpacku_h_P0S_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4UHI, 1 }, { 0, 0, cgen_regnum_operand_type_V4UHI, 0 }, { 0, 0, cgen_regnum_operand_type_V4UHI, 0 } },
+ 4 },
+ { 372,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpunpacku_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 372,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpunpacku_b_P0S_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8UQI, 1 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 }, { 0, 0, cgen_regnum_operand_type_V8UQI, 0 } },
+ 4 },
+ { 386,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpadd3_w_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 386,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpadd3_w_P0S_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V2SI, 1 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 }, { 0, 0, cgen_regnum_operand_type_V2SI, 0 } },
+ 4 },
+ { 387,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpadd3_h_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 387,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpadd3_h_P0S_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V4HI, 1 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 }, { 0, 0, cgen_regnum_operand_type_V4HI, 0 } },
+ 4 },
+ { 388,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpadd3_b_C3,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 388,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cpadd3_b_P0S_P1,
+ 3,
+ 1,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_V8QI, 1 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 }, { 0, 0, cgen_regnum_operand_type_V8QI, 0 } },
+ 4 },
+ { 102,
+ ISA_EXT1|ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_c0nop_P0_P0S,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 4 },
+ { 202,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cpmoviu_h_C3,
+ 2,
+ 1,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_V4UHI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 638,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cmovh_rn_crm,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 389,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cmovh_rn_crm_p0,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 16, 0, cgen_regnum_operand_type_DEFAULT, 0 }, { 32, 48, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 639,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cmovh_crn_rm,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 390,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cmovh_crn_rm_p0,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 32, 48, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 16, 0, cgen_regnum_operand_type_DEFAULT, 0 } },
+ 4 },
+ { 640,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cmovc_rn_ccrm,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 64, 80, cgen_regnum_operand_type_DEFAULT, 0 } },
+ 4 },
+ { 391,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cmovc_rn_ccrm_p0,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 16, 0, cgen_regnum_operand_type_DEFAULT, 0 }, { 64, 80, cgen_regnum_operand_type_DEFAULT, 0 } },
+ 4 },
+ { 641,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cmovc_ccrn_rm,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 64, 80, cgen_regnum_operand_type_DEFAULT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 392,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cmovc_ccrn_rm_p0,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 64, 80, cgen_regnum_operand_type_DEFAULT, 0 }, { 16, 0, cgen_regnum_operand_type_DEFAULT, 0 } },
+ 4 },
+ { 642,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cmov_rn_crm,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 393,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cmov_rn_crm_p0,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 16, 0, cgen_regnum_operand_type_DEFAULT, 0 }, { 32, 48, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 } },
+ 4 },
+ { 643,
+ ISA_EXT1,
+ GROUP_NORMAL,
+ CODE_FOR_cgen_intrinsic_cmov_crn_rm,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 394,
+ ISA_EXT1,
+ GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cmov_crn_rm_p0,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 32, 48, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 16, 0, cgen_regnum_operand_type_DEFAULT, 0 } },
+ 4 },
+ { 395,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bsrv,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 396,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_jsrv,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 397,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_synccp,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 2 },
+ { 398,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bcpaf,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 399,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bcpat,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 400,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bcpne,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 401,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bcpeq,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 402,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lmcpm1,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 403,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_smcpm1,
+ 3,
+ 0,
+ { 1, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 404,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lwcpm1,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 405,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_swcpm1,
+ 3,
+ 0,
+ { 1, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 406,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lhcpm1,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 407,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_shcpm1,
+ 3,
+ 0,
+ { 1, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 408,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lbcpm1,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 409,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sbcpm1,
+ 3,
+ 0,
+ { 1, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 410,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lmcpm0,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 411,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_smcpm0,
+ 3,
+ 0,
+ { 1, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 412,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lwcpm0,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 413,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_swcpm0,
+ 3,
+ 0,
+ { 1, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 414,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lhcpm0,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 415,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_shcpm0,
+ 3,
+ 0,
+ { 1, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 416,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lbcpm0,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 417,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sbcpm0,
+ 3,
+ 0,
+ { 1, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 418,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lmcpa,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 419,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_smcpa,
+ 3,
+ 0,
+ { 1, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 420,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lwcpa,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 421,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_swcpa,
+ 3,
+ 0,
+ { 1, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 422,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lhcpa,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 423,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_shcpa,
+ 3,
+ 0,
+ { 1, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 424,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lbcpa,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 425,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sbcpa,
+ 3,
+ 0,
+ { 1, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 426,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lmcp16,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 427,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_smcp16,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 428,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lwcp16,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 429,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_swcp16,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 430,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lmcpi,
+ 2,
+ 0,
+ { 0, 1, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 } },
+ 2 },
+ { 431,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_smcpi,
+ 2,
+ 0,
+ { 1, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 } },
+ 2 },
+ { 432,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lwcpi,
+ 2,
+ 0,
+ { 0, 1, 1 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 } },
+ 2 },
+ { 433,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_swcpi,
+ 2,
+ 0,
+ { 1, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 } },
+ 2 },
+ { 434,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lmcp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 435,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_smcp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_CP_DATA_BUS_INT, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 436,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lwcp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 437,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_swcp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 438,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ssubu,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 439,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_saddu,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 440,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ssub,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 441,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sadd,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 442,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_clipu,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 443,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_clip,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 444,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_maxu,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 445,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_minu,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 446,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_max,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 447,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_min,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 448,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ave,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 449,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_abs,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 450,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ldz,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 451,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_dbreak,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 2 },
+ { 452,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_dret,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 2 },
+ { 453,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_divu,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 454,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_div,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 455,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_maddru,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 456,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_maddr,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 457,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_maddu,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 458,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_madd,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 459,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_mulru,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 460,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_mulr,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 461,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_mulu,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 462,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_mul,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 463,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cache,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 464,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_tas,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 465,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_btstm,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 466,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bnotm,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_POINTER, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 467,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bclrm,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_POINTER, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 468,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bsetm,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_POINTER, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 469,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ldcb,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 470,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_stcb,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 471,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_syncm,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 2 },
+ { 472,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_break,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 2 },
+ { 473,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_swi,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 474,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sleep,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 2 },
+ { 475,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_halt,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 2 },
+ { 476,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_reti,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 2 },
+ { 477,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ei,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 2 },
+ { 478,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_di,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 2 },
+ { 479,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ldc,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 32, 16, cgen_regnum_operand_type_DEFAULT, 0 } },
+ 2 },
+ { 480,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ldc_lo,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
+ 2 },
+ { 481,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ldc_hi,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
+ 2 },
+ { 482,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ldc_lp,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
+ 2 },
+ { 483,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_stc,
+ 2,
+ 0,
+ { 1, 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 32, 16, cgen_regnum_operand_type_DEFAULT, 0 } },
+ 2 },
+ { 484,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_stc_lo,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 485,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_stc_hi,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 486,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_stc_lp,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 487,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_erepeat,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 488,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_repeat,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 489,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ret,
+ 0,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_DEFAULT, 0} },
+ 2 },
+ { 490,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_jsr,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 491,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_jmp24,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 492,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_jmp,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 494,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bsr12,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 2 },
+ { 493,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bsr24,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 495,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bne,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 496,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_beq,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 497,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bgei,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 498,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_blti,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 499,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bnei,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 500,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_beqi,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 4 },
+ { 501,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bnez,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 2 },
+ { 502,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_beqz,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 2 },
+ { 503,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_bra,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LABEL, 0 } },
+ 2 },
+ { 504,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_fsft,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 505,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sll3,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 506,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_slli,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 507,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_srli,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 508,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_srai,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 509,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sll,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 510,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_srl,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 511,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sra,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 512,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_xor3,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 513,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_and3,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 514,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_or3,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 515,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_nor,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 516,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_xor,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 517,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_and,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 518,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_or,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 519,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sltu3x,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 520,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_slt3x,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 521,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_add3x,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 522,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sl2ad3,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 523,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sl1ad3,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 524,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sltu3i,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 525,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_slt3i,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 526,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sltu3,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 527,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_slt3,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 528,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_neg,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 529,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sbvck3,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 530,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sub,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 531,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_advck3,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 532,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_add3i,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 533,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_add,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 534,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_add3,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 535,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_movh,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 536,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_movu16,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 537,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_movu24,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 539,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_movi8,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 538,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_movi16,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 540,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_mov,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 541,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ssarb,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 542,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_extuh,
+ 1,
+ 0,
+ { 0, 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
+ 2 },
+ { 543,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_extub,
+ 1,
+ 0,
+ { 0, 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
+ 2 },
+ { 544,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_exth,
+ 1,
+ 0,
+ { 0, 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
+ 2 },
+ { 545,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_extb,
+ 1,
+ 0,
+ { 0, 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 } },
+ 2 },
+ { 546,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lw24,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 547,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sw24,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 548,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lhu16,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 549,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lbu16,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 550,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lw16,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 551,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lh16,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 552,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lb16,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 553,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sw16,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 554,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sh16,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 555,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sb16,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 556,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lhu_tp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 557,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lbu_tp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 558,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lw_tp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 559,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lh_tp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 560,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lb_tp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 561,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sw_tp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 562,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sh_tp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 563,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sb_tp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 564,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lw_sp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 565,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sw_sp,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 2 },
+ { 566,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lhu,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 567,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lbu,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 568,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lw,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 569,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lh,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 570,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lb,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 571,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sw,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 572,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sh,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 573,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sb,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 574,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_dsp1,
+ 2,
+ 0,
+ { 0, 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 575,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_dsp0,
+ 1,
+ 0,
+ { 0 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 576,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_dsp,
+ 3,
+ 0,
+ { 0, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 577,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_uci,
+ 3,
+ 0,
+ { 0, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 578,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lhucpm1,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 579,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lbucpm1,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 580,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lhucpm0,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 581,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lbucpm0,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 582,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lhucpa,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 583,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lbucpa,
+ 3,
+ 0,
+ { 0, 1, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 584,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lhucp,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 585,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lhcp,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 586,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_shcp,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 587,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lbucp,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 588,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_lbcp,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 589,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_sbcp,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_SI, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 590,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_casw3,
+ 3,
+ 0,
+ { 0, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 591,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_cash3,
+ 3,
+ 0,
+ { 0, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 592,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_casb3,
+ 3,
+ 0,
+ { 0, 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 } },
+ 4 },
+ { 593,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_prefd,
+ 3,
+ 0,
+ { 0, 1, 2 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 4 },
+ { 594,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_pref,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 595,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_ldcb_r,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 1 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 },
+ { 596,
+ ISA_MEP|ISA_EXT1,
+ GROUP_NORMAL|GROUP_VLIW,
+ CODE_FOR_cgen_intrinsic_stcb_r,
+ 2,
+ 0,
+ { 0, 1 },
+ { { 0, 0, cgen_regnum_operand_type_LONG, 0 }, { 0, 0, cgen_regnum_operand_type_POINTER, 0 } },
+ 2 }
+};
+#endif
--- /dev/null
+; Toshiba MeP IVC2 Coprocessor description. -*- scheme -*-
+; Copyright (C) 2009 Red Hat, Inc.
+; This file is part of CGEN.
+; See file COPYING.CGEN for details.
+;
+
+;------------------------------------------------------------------------------
+; MeP-Integrator will redefine the isa pmacros below to allow the bit widths
+; specified below for each ME_MODULE using this coprocessor.
+; IVC2 uses the isas as follows:
+; C3 32
+; P0S 16
+; P0 48
+; P1 64
+;------------------------------------------------------------------------------
+; begin-isas
+(define-pmacro ivc2-core-isa () (ISA ext_core1))
+(define-pmacro ivc2-16-isa () (ISA ext_cop1_16))
+(define-pmacro ivc2-32-isa () (ISA ext_cop1_32))
+(define-pmacro ivc2-48-isa () (ISA ext_cop1_48))
+(define-pmacro ivc2-64-isa () (ISA ext_cop1_64))
+(define-pmacro all-ivc2-isas () (ISA ext_core1,ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64))
+(define-pmacro ivc2-p0s-isa () (ISA ext_cop1_16))
+(define-pmacro ivc2-p0-isa () (ISA ext_cop1_48))
+(define-pmacro ivc2-p0s-p0-isa () (ISA ext_cop1_16,ext_cop1_48))
+(define-pmacro ivc2-p1-isa () (ISA ext_cop1_64))
+(define-pmacro ivc2-p0s-p1-isa () (ISA ext_cop1_16,ext_cop1_64))
+(define-pmacro ivc2-p0-p1-isa () (ISA ext_cop1_48,ext_cop1_64))
+(define-pmacro ivc2-p0s-p0-p1-isa () (ISA ext_cop1_16,ext_cop1_48,ext_cop1_64))
+(define-pmacro ivc2-c3-isa () (ISA ext_cop1_32))
+; end-isas
+
+; register definitions
+; ---------------------
+; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
+; GDB will use the hardware table generated from this declaration. The operands use h-cr
+; from mep-core.cpu so that SID's semantic trace will be consistent between
+; the core and the coprocessor but use parse/print handlers which reference the hardware table
+; generated from this declarations
+(define-hardware
+ (name h-cr-ivc2)
+ (comment "64-bit coprocessor registers for ivc2 coprocessor")
+ (attrs VIRTUAL all-mep-core-isas (CDATA CP_DATA_BUS_INT))
+ (type register DI (64))
+ (set (index newval) (c-call VOID "h_cr64_set" index newval))
+ (get (index) (c-call DI "h_cr64_get" index))
+ (indices keyword "$c" (.map -reg-pair (.iota 8)))
+)
+
+; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
+; GDB will use the hardware table generated from this declaration. The operands use h-ccr
+; from mep-core.cpu so that SID's semantic trace will be consistent between
+; the core and the coprocessor but use parse/print handlers which reference the hardware table
+; generated from this declarations
+(define-hardware
+ (name h-ccr-ivc2)
+ (comment "Coprocessor control registers for ivc2 coprocessor")
+ (attrs VIRTUAL all-mep-isas)
+ (type register SI (32))
+ (set (index newval) (c-call VOID "h_ccr_set" index newval))
+ (get (index) (c-call SI "h_ccr_get" index))
+ (indices keyword ""
+ (.splice
+
+ ($csar0 0)
+ ($cc 1)
+ ($cofr0 4)
+ ($cofr1 5)
+ ($cofa0 6)
+ ($cofa1 7)
+
+ ($csar1 15)
+
+ ($acc0_0 16)
+ ($acc0_1 17)
+ ($acc0_2 18)
+ ($acc0_3 19)
+ ($acc0_4 20)
+ ($acc0_5 21)
+ ($acc0_6 22)
+ ($acc0_7 23)
+
+ ($acc1_0 24)
+ ($acc1_1 25)
+ ($acc1_2 26)
+ ($acc1_3 27)
+ ($acc1_4 28)
+ ($acc1_5 29)
+ ($acc1_6 30)
+ ($acc1_7 31)
+ (.unsplice (.map -ccr-reg-pair (.iota 32)))
+ )
+ )
+)
+
+(define-attr
+ (type bitset)
+ (for insn)
+ (name SLOTS)
+ (comment "slots for which this opcode is valid - c3, p0s, p0, p1")
+ (values CORE C3 P0S P0 P1)
+ (default CORE)
+ )
+
+;-----------------------------------------------------------------------------
+; macros for standard opcodes for each slot type
+
+; C3
+(dnf f-ivc2-2u4 "sub opcode field" (all-mep-isas) 4 2)
+(dnf f-ivc2-3u4 "sub opcode field" (all-mep-isas) 4 3)
+(dnf f-ivc2-8u4 "sub opcode field" (all-mep-isas) 4 8)
+(df f-ivc2-8s4 "sub opcode field" (all-mep-isas) 4 8 INT #f #f)
+(dnf f-ivc2-1u6 "sub opcode field" (all-mep-isas) 6 1)
+(dnf f-ivc2-2u6 "sub opcode field" (all-mep-isas) 6 2)
+(dnf f-ivc2-3u6 "sub opcode field" (all-mep-isas) 6 3)
+(dnf f-ivc2-6u6 "sub opcode field" (all-mep-isas) 6 6)
+(dnf f-ivc2-5u7 "sub opcode field" (all-mep-isas) 7 5)
+(dnf f-ivc2-4u8 "sub opcode field" (all-mep-isas) 8 4)
+(dnf f-ivc2-3u9 "sub opcode field" (all-mep-isas) 9 3)
+(dnf f-ivc2-5u16 "sub opcode field" (all-mep-isas) 16 5)
+(dnf f-ivc2-5u21 "sub opcode field" (all-mep-isas) 21 5)
+(dnf f-ivc2-5u26 "sub opcode field" (all-mep-isas) 26 5)
+(dnf f-ivc2-1u31 "sub opcode field" (all-mep-isas) 31 1)
+
+(dnf f-ivc2-4u16 "sub opcode field" (all-mep-isas) 16 4)
+(dnf f-ivc2-4u20 "sub opcode field" (all-mep-isas) 20 4)
+(dnf f-ivc2-4u24 "sub opcode field" (all-mep-isas) 24 4)
+(dnf f-ivc2-4u28 "sub opcode field" (all-mep-isas) 28 4)
+
+; P0S/P0/P1
+(dnf f-ivc2-2u0 "sub opcode field" (all-mep-isas) 0 2)
+(dnf f-ivc2-3u0 "sub opcode field" (all-mep-isas) 0 3)
+(dnf f-ivc2-4u0 "sub opcode field" (all-mep-isas) 0 4)
+(dnf f-ivc2-5u0 "sub opcode field" (all-mep-isas) 0 5)
+(dnf f-ivc2-8u0 "sub opcode field" (all-mep-isas) 0 8)
+(df f-ivc2-8s0 "sub opcode field" (all-mep-isas) 0 8 INT #f #f)
+(dnf f-ivc2-6u2 "sub opcode field" (all-mep-isas) 2 6)
+(dnf f-ivc2-5u3 "sub opcode field" (all-mep-isas) 3 5)
+(dnf f-ivc2-4u4 "sub opcode field" (all-mep-isas) 4 4)
+(dnf f-ivc2-3u5 "sub opcode field" (all-mep-isas) 5 3)
+(dnf f-ivc2-5u8 "sub opcode field" (all-mep-isas) 8 5)
+(dnf f-ivc2-4u10 "sub opcode field" (all-mep-isas) 10 4)
+(dnf f-ivc2-3u12 "sub opcode field" (all-mep-isas) 12 3)
+(dnf f-ivc2-5u13 "sub opcode field" (all-mep-isas) 13 5)
+(dnf f-ivc2-2u18 "sub opcode field" (all-mep-isas) 18 2)
+(dnf f-ivc2-5u18 "sub opcode field" (all-mep-isas) 18 5)
+(dnf f-ivc2-8u20 "sub opcode field" (all-mep-isas) 20 8)
+(df f-ivc2-8s20 "sub opcode field" (all-mep-isas) 20 8 INT #f #f)
+(dnf f-ivc2-5u23 "sub opcode field" (all-mep-isas) 23 5)
+(dnf f-ivc2-2u23 "sub opcode field" (all-mep-isas) 23 2)
+(dnf f-ivc2-3u25 "sub opcode field" (all-mep-isas) 25 3)
+
+(dnmf f-ivc2-imm16p0 "16-bit immediate in P0/P1" (all-mep-isas) UINT
+ (f-ivc2-8u0 f-ivc2-8u20)
+ (sequence () ; insert
+ (set (ifield f-ivc2-8u0) (and (srl (ifield f-ivc2-imm16p0) 8) #xff))
+ (set (ifield f-ivc2-8u20) (and (ifield f-ivc2-imm16p0) #xff))
+ )
+ (sequence () ; extract
+ (set (ifield f-ivc2-imm16p0) (or (ifield f-ivc2-8u20)
+ (sll (ifield f-ivc2-8u0) 8)))
+ )
+ )
+
+(dnmf f-ivc2-simm16p0 "16-bit immediate in P0/P1" (all-mep-isas) INT
+ (f-ivc2-8u0 f-ivc2-8u20)
+ (sequence () ; insert
+ (set (ifield f-ivc2-8u0) (and (srl (ifield f-ivc2-simm16p0) 8) #xff))
+ (set (ifield f-ivc2-8u20) (and (ifield f-ivc2-simm16p0) #xff))
+ )
+ (sequence () ; extract
+ (set (ifield f-ivc2-simm16p0) (or (ifield f-ivc2-8u20)
+ (sll (ifield f-ivc2-8u0) 8)))
+ )
+ )
+
+(dnop ivc2_csar0 "ivc2_csar0" (all-ivc2-isas) h-ccr-ivc2 0)
+(dnop ivc2_cc "ivc2_cc" (all-ivc2-isas) h-ccr-ivc2 1)
+(dnop ivc2_cofr0 "ivc2_cofr0" (all-ivc2-isas) h-ccr-ivc2 4)
+(dnop ivc2_cofr1 "ivc2_cofr1" (all-ivc2-isas) h-ccr-ivc2 5)
+(dnop ivc2_cofa0 "ivc2_cofa0" (all-ivc2-isas) h-ccr-ivc2 6)
+(dnop ivc2_cofa1 "ivc2_cofa1" (all-ivc2-isas) h-ccr-ivc2 7)
+
+(dnop ivc2_csar1 "ivc2_csar1" (all-ivc2-isas) h-ccr-ivc2 15)
+
+(dnop ivc2_acc0_0 "acc0_0" (all-ivc2-isas) h-ccr-ivc2 16)
+(dnop ivc2_acc0_1 "acc0_1" (all-ivc2-isas) h-ccr-ivc2 17)
+(dnop ivc2_acc0_2 "acc0_2" (all-ivc2-isas) h-ccr-ivc2 18)
+(dnop ivc2_acc0_3 "acc0_3" (all-ivc2-isas) h-ccr-ivc2 19)
+(dnop ivc2_acc0_4 "acc0_4" (all-ivc2-isas) h-ccr-ivc2 20)
+(dnop ivc2_acc0_5 "acc0_5" (all-ivc2-isas) h-ccr-ivc2 21)
+(dnop ivc2_acc0_6 "acc0_6" (all-ivc2-isas) h-ccr-ivc2 22)
+(dnop ivc2_acc0_7 "acc0_7" (all-ivc2-isas) h-ccr-ivc2 23)
+
+(dnop ivc2_acc1_0 "acc1_0" (all-ivc2-isas) h-ccr-ivc2 24)
+(dnop ivc2_acc1_1 "acc1_1" (all-ivc2-isas) h-ccr-ivc2 25)
+(dnop ivc2_acc1_2 "acc1_2" (all-ivc2-isas) h-ccr-ivc2 26)
+(dnop ivc2_acc1_3 "acc1_3" (all-ivc2-isas) h-ccr-ivc2 27)
+(dnop ivc2_acc1_4 "acc1_4" (all-ivc2-isas) h-ccr-ivc2 28)
+(dnop ivc2_acc1_5 "acc1_5" (all-ivc2-isas) h-ccr-ivc2 29)
+(dnop ivc2_acc1_6 "acc1_6" (all-ivc2-isas) h-ccr-ivc2 30)
+(dnop ivc2_acc1_7 "acc1_7" (all-ivc2-isas) h-ccr-ivc2 31)
+
+(dnop croc "$CRo C3" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u7)
+(dnop crqc "$CRq C3" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u21)
+(dnop crpc "$CRp C3" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u26)
+
+(dnop ivc-x-6-1 "filler" (all-mep-isas) h-uint f-ivc2-1u6)
+(dnop ivc-x-6-2 "filler" (all-mep-isas) h-uint f-ivc2-2u6)
+(dnop ivc-x-6-3 "filler" (all-mep-isas) h-uint f-ivc2-3u6)
+
+
+(dnop imm3p4 "Imm3p4" (all-mep-isas) h-uint f-ivc2-3u4)
+(dnop imm3p9 "Imm3p9" (all-mep-isas) h-uint f-ivc2-3u9)
+(dnop imm4p8 "Imm4p8" (all-mep-isas) h-uint f-ivc2-4u8)
+(dnop imm5p7 "Imm5p7" (all-mep-isas) h-uint f-ivc2-5u7)
+(dnop imm6p6 "Imm6p6" (all-mep-isas) h-uint f-ivc2-6u6)
+(dnop imm8p4 "Imm8p4" (all-mep-isas) h-uint f-ivc2-8u4)
+(dnop simm8p4 "sImm8p4" (all-mep-isas) h-sint f-ivc2-8s4)
+
+(dnop imm3p5 "Imm3p5" (all-mep-isas) h-uint f-ivc2-3u5)
+(dnop imm3p12 "Imm3p12" (all-mep-isas) h-uint f-ivc2-3u12)
+(dnop imm4p4 "Imm4p4" (all-mep-isas) h-uint f-ivc2-4u4)
+(dnop imm4p10 "Imm4p10" (all-mep-isas) h-uint f-ivc2-4u10)
+(dnop imm5p8 "Imm5p8" (all-mep-isas) h-uint f-ivc2-5u8)
+(dnop imm5p3 "Imm5p3" (all-mep-isas) h-uint f-ivc2-5u3)
+(dnop imm6p2 "Imm6p2" (all-mep-isas) h-uint f-ivc2-6u2)
+(dnop imm5p23 "Imm5p23" (all-mep-isas) h-uint f-ivc2-5u23)
+(dnop imm3p25 "Imm3p25" (all-mep-isas) h-uint f-ivc2-3u25)
+(dnop imm8p0 "Imm8p0" (all-mep-isas) h-uint f-ivc2-8u0)
+(dnop simm8p0 "sImm8p0" (all-mep-isas) h-sint f-ivc2-8s0)
+(dnop simm8p20 "sImm8p20" (all-mep-isas) h-sint f-ivc2-8s20)
+(dnop imm8p20 "Imm8p20" (all-mep-isas) h-uint f-ivc2-8u20)
+
+(dnop crop "$CRo Pn" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u23)
+(dnop crqp "$CRq Pn" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u13)
+(dnop crpp "$CRp Pn" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u18)
+
+(dnop ivc-x-0-2 "filler" (all-mep-isas) h-uint f-ivc2-2u0)
+(dnop ivc-x-0-3 "filler" (all-mep-isas) h-uint f-ivc2-3u0)
+(dnop ivc-x-0-4 "filler" (all-mep-isas) h-uint f-ivc2-4u0)
+(dnop ivc-x-0-5 "filler" (all-mep-isas) h-uint f-ivc2-5u0)
+
+(dpop imm16p0 "Imm16p0" (all-mep-isas) h-uint f-ivc2-imm16p0 "unsigned16_range")
+(dpop simm16p0 "sImm16p0" (all-mep-isas) h-sint f-ivc2-simm16p0 "signed16_range")
+
+
+(df f-ivc2-ccrn-c3hi "ccrn hi 2u28" (all-mep-isas) 28 2 UINT #f #f)
+(df f-ivc2-ccrn-c3lo "ccrn lo 4u4" (all-mep-isas) 4 4 UINT #f #f)
+
+(df f-ivc2-crn "ivc2 crn" (all-mep-isas) 0 4 UINT #f #f)
+(df f-ivc2-crm "ivc2 crm" (all-mep-isas) 4 4 UINT #f #f)
+(df f-ivc2-ccrn-h1 "ccrx hi 1u20" (all-mep-isas) 20 1 UINT #f #f)
+(df f-ivc2-ccrn-h2 "ccrx hi 2u20" (all-mep-isas) 20 2 UINT #f #f)
+(df f-ivc2-ccrn-lo "ccrx lo 4u0" (all-mep-isas) 0 4 UINT #f #f)
+(df f-ivc2-cmov1 "ivc2 cmov op1" (all-mep-isas) 8 12 UINT #f #f)
+(df f-ivc2-cmov2 "ivc2 cmov op2" (all-mep-isas) 22 6 UINT #f #f)
+(df f-ivc2-cmov3 "ivc2 cmov op2" (all-mep-isas) 28 4 UINT #f #f)
+
+(define-multi-ifield
+ (name f-ivc2-ccrn-c3)
+ (comment "Coprocessor register number field")
+ (attrs all-mep-isas)
+ (mode UINT)
+ (subfields f-ivc2-ccrn-c3hi f-ivc2-ccrn-c3lo)
+ (insert (sequence ()
+ (set (ifield f-ivc2-ccrn-c3hi) (and (srl (ifield f-ivc2-ccrn-c3) 4) #x3))
+ (set (ifield f-ivc2-ccrn-c3lo) (and (ifield f-ivc2-ccrn-c3) #xf))))
+ (extract (set (ifield f-ivc2-ccrn-c3)
+ (or (sll (ifield f-ivc2-ccrn-c3hi) 4)
+ (ifield f-ivc2-ccrn-c3lo))))
+ )
+
+(define-multi-ifield
+ (name f-ivc2-ccrn)
+ (comment "Coprocessor control register number field")
+ (attrs all-mep-isas)
+ (mode UINT)
+ (subfields f-ivc2-ccrn-h2 f-ivc2-ccrn-lo)
+ (insert (sequence ()
+ (set (ifield f-ivc2-ccrn-h2) (and (srl (ifield f-ivc2-ccrn) 4) #x3))
+ (set (ifield f-ivc2-ccrn-lo) (and (ifield f-ivc2-ccrn) #xf))))
+ (extract (set (ifield f-ivc2-ccrn)
+ (or (sll (ifield f-ivc2-ccrn-h2) 4)
+ (ifield f-ivc2-ccrn-lo))))
+ )
+
+(define-multi-ifield
+ (name f-ivc2-crnx)
+ (comment "Coprocessor register number field")
+ (attrs all-mep-isas)
+ (mode UINT)
+ (subfields f-ivc2-ccrn-h1 f-ivc2-ccrn-lo)
+ (insert (sequence ()
+ (set (ifield f-ivc2-ccrn-h1) (and (srl (ifield f-ivc2-crnx) 4) #x1))
+ (set (ifield f-ivc2-ccrn-lo) (and (ifield f-ivc2-crnx) #xf))))
+ (extract (set (ifield f-ivc2-crnx)
+ (or (sll (ifield f-ivc2-ccrn-h1) 4)
+ (ifield f-ivc2-ccrn-lo))))
+ )
+
+(dnop ivc2rm "reg Rm" (all-mep-isas (CDATA REGNUM)) h-gpr f-ivc2-crm)
+(dnop ivc2crn "copro Rn (0-31, 64-bit" (all-mep-isas (CDATA REGNUM)) h-cr64 f-ivc2-crnx)
+(dnop ivc2ccrn "copro control reg CCRn" (all-mep-isas (CDATA REGNUM)) h-ccr-ivc2 f-ivc2-ccrn)
+(dnop ivc2c3ccrn "copro control reg CCRn" (all-mep-isas (CDATA REGNUM)) h-ccr-ivc2 f-ivc2-ccrn-c3)
+
+; [--][--] [--][--] [--][--] [--]
+; 0----+-- --1----+ ----2--- -+--
+; 01234567 89012345 67890123 4567
+
+
+; 1111 nnnn mmmm 0111 1111 0000 0000 N000 cmov =crn,rm
+(dni cmov-crn-rm
+ "cmov CRn,Rm"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmov1"))
+ "cmov $crnx64,$rm"
+ (+ MAJ_15 crnx64 rm (f-sub4 #x7)
+ (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 0))
+ (set crnx64 (or (zext DI rm) (and DI crnx64 #xffffffff00000000)))
+ ()
+)
+
+; 1111 nnnn mmmm 0111 1111 0000 0000 N001 cmov =rm,crn
+(dni cmov-rn-crm
+ "cmov Rm,CRn"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmov2"))
+ "cmov $rm,$crnx64"
+ (+ MAJ_15 crnx64 rm (f-sub4 #x7)
+ (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 1))
+ (set rm crnx64)
+ ()
+)
+
+; 1111 nnnn mmmm 0111 1111 0000 0000 N000 cmov =crn,rm
+(dni cmovc-ccrn-rm
+ "cmovc CCRn,Rm"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovc1"))
+ "cmovc $ivc2c3ccrn,$rm"
+ (+ MAJ_15 ivc2c3ccrn rm (f-sub4 #x7)
+ (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-30 1) (f-31 0))
+ (set ivc2c3ccrn rm)
+ ()
+)
+
+; 1111 nnnn mmmm 0111 1111 0000 0000 N001 cmov =rm,crn
+(dni cmovc-rn-ccrm
+ "cmovc Rm,CCRn"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovc2"))
+ "cmovc $rm,$ivc2c3ccrn"
+ (+ MAJ_15 ivc2c3ccrn rm (f-sub4 #x7)
+ (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-30 1) (f-31 1))
+ (set rm ivc2c3ccrn)
+ ()
+)
+
+; 1111 nnnn mmmm 0111 1111 0000 0000 N000 cmov =crn,rm
+(dni cmovh-crn-rm
+ "cmovh CRn,Rm"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovh1"))
+ "cmovh $crnx64,$rm"
+ (+ MAJ_15 crnx64 rm (f-sub4 #x7)
+ (f-ivc2-4u16 #xF) (f-ivc2-4u20 1) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 0))
+ (set crnx64 (or (sll (zext DI rm) 32) (and DI crnx64 #xffffffff)))
+ ()
+)
+
+; 1111 nnnn mmmm 0111 1111 0000 0000 N001 cmov =rm,crn
+(dni cmovh-rn-crm
+ "cmovh Rm,CRn"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovh2"))
+ "cmovh $rm,$crnx64"
+ (+ MAJ_15 crnx64 rm (f-sub4 #x7)
+ (f-ivc2-4u16 #xF) (f-ivc2-4u20 1) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 1))
+ (set rm (srl crnx64 32))
+ ()
+)
+
+; nnnnmmmm 11110000 0000N000 0000 cmov =crn,rm
+(dni cmov-crn-rm-p0
+ "cmov CRn,Rm"
+ (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0))
+ "cmov $ivc2crn,$ivc2rm"
+ (+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf00) (f-21 0) (f-ivc2-cmov2 #x00) (f-ivc2-cmov3 0))
+ (set ivc2crn ivc2rm)
+ ()
+)
+
+; nnnnmmmm 11110000 0000N001 0000 cmov =rm,crn
+(dni cmov-rn-crm-p0
+ "cmov Rm,CRn"
+ (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0))
+ "cmov $ivc2rm,$ivc2crn"
+ (+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf00) (f-21 0) (f-ivc2-cmov2 #x10) (f-ivc2-cmov3 0))
+ (set ivc2rm ivc2crn)
+ ()
+)
+
+; nnnnmmmm 11110000 0000NN10 0000 cmovc =ccrn,rm
+(dni cmovc-ccrn-rm-p0
+ "cmovc CCRn,Rm"
+ (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0))
+ "cmovc $ivc2ccrn,$ivc2rm"
+ (+ ivc2ccrn ivc2rm (f-ivc2-cmov1 #xf00) (f-ivc2-cmov2 #x20) (f-ivc2-cmov3 0))
+ (set ivc2ccrn ivc2rm)
+ ()
+)
+
+; nnnnmmmm 11110000 0000NN11 0000 cmovc =rm,ccrn
+(dni cmovc-rn-ccrm-p0
+ "cmovc Rm,CCRn"
+ (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0))
+ "cmovc $ivc2rm,$ivc2ccrn"
+ (+ ivc2ccrn ivc2rm (f-ivc2-cmov1 #xf00) (f-ivc2-cmov2 #x30) (f-ivc2-cmov3 0))
+ (set ivc2rm ivc2ccrn)
+ ()
+)
+
+; nnnnmmmm 11110001 0000N000 0000 cmovh =crn,rm
+(dni cmovh-crn-rm-p0
+ "cmovh CRn,Rm"
+ (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0))
+ "cmovh $ivc2crn,$ivc2rm"
+ (+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf10) (f-21 0) (f-ivc2-cmov2 #x00) (f-ivc2-cmov3 0))
+ (set ivc2crn (or (sll (zext DI ivc2rm) 32) (and DI ivc2crn #xffffffff)))
+ ()
+)
+
+; nnnnmmmm 11110001 0000N001 0000 cmovh =rm,crn
+(dni cmovh-rn-crm-p0
+ "cmovh Rm,CRn"
+ (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0))
+ "cmovh $ivc2rm,$ivc2crn"
+ (+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf10) (f-21 0) (f-ivc2-cmov2 #x10) (f-ivc2-cmov3 0))
+ (set ivc2rm (srl ivc2crn 32))
+ ()
+)
+
+
+; 1111 000 ooooo 0111 00000 qqqqq ppppp 0 cpadd3.b =croc,crqc,crpc (c3_1)
+(dni cpadd3_b_C3 "cpadd3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpadd3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpadd3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 001 ooooo 0111 00000 qqqqq ppppp 0 cpadd3.h =croc,crqc,crpc (c3_1)
+(dni cpadd3_h_C3 "cpadd3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpadd3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpadd3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 010 ooooo 0111 00000 qqqqq ppppp 0 cpadd3.w =croc,crqc,crpc (c3_1)
+(dni cpadd3_w_C3 "cpadd3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpadd3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpadd3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 011 ooooo 0111 00000 qqqqq ppppp 0 cdadd3 =croc,crqc,crpc (c3_1)
+(dni cdadd3_C3 "cdadd3 $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdadd3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdadd3 $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cdadd3" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 100 ooooo 0111 00000 qqqqq ppppp 0 cpsub3.b =croc,crqc,crpc (c3_1)
+(dni cpsub3_b_C3 "cpsub3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpsub3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsub3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 101 ooooo 0111 00000 qqqqq ppppp 0 cpsub3.h =croc,crqc,crpc (c3_1)
+(dni cpsub3_h_C3 "cpsub3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsub3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsub3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 110 ooooo 0111 00000 qqqqq ppppp 0 cpsub3.w =croc,crqc,crpc (c3_1)
+(dni cpsub3_w_C3 "cpsub3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsub3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsub3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 111 ooooo 0111 00000 qqqqq ppppp 0 cdsub3 =croc,crqc,crpc (c3_1)
+(dni cdsub3_C3 "cdsub3 $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsub3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdsub3 $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cdsub3" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00001 qqqqq ppppp 0 cpand3 =croc,crqc,crpc (c3_1)
+(dni cpand3_C3 "cpand3 $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpand3") (CPTYPE VECT) (CRET FIRST))
+ "cpand3 $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpand3" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 001 ooooo 0111 00001 qqqqq ppppp 0 cpor3 =croc,crqc,crpc (c3_1)
+(dni cpor3_C3 "cpor3 $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpor3") (CPTYPE VECT) (CRET FIRST))
+ "cpor3 $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpor3" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 010 ooooo 0111 00001 qqqqq ppppp 0 cpnor3 =croc,crqc,crpc (c3_1)
+(dni cpnor3_C3 "cpnor3 $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnor3") (CPTYPE VECT) (CRET FIRST))
+ "cpnor3 $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpnor3" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 011 ooooo 0111 00001 qqqqq ppppp 0 cpxor3 =croc,crqc,crpc (c3_1)
+(dni cpxor3_C3 "cpxor3 $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpxor3") (CPTYPE VECT) (CRET FIRST))
+ "cpxor3 $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpxor3" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 100 ooooo 0111 00001 qqqqq ppppp 0 cpsel =croc,crqc,crpc (c3_1)
+(dni cpsel_C3 "cpsel $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsel") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpsel $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsel" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 iii ooooo 0111 11101 qqqqq ppppp 0 cpfsftbi =croc,crqc,crpc,imm3p4 (c3_1)
+(dni cpfsftbi_C3 "cpfsftbi $croc,$crqc,$crpc,imm3p4 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpfsftbi $croc,$crqc,$crpc,$imm3p4"
+ (+ MAJ_15 imm3p4 croc (f-sub4 7)
+ (f-ivc2-5u16 #x1d) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpfsftbi" pc crqc crpc imm3p4)) )
+ ()
+ )
+
+; 1111 110 ooooo 0111 00001 qqqqq ppppp 0 cpfsftbs0 =croc,crqc,crpc (c3_1)
+(dni cpfsftbs0_C3 "cpfsftbs0 $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbs0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpfsftbs0 $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpfsftbs0" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 111 ooooo 0111 00001 qqqqq ppppp 0 cpfsftbs1 =croc,crqc,crpc (c3_1)
+(dni cpfsftbs1_C3 "cpfsftbs1 $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbs1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpfsftbs1 $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpfsftbs1" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00010 qqqqq ppppp 0 cpunpacku.b =croc,crqc,crpc (c3_1)
+(dni cpunpacku_b_C3 "cpunpacku.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cpunpacku.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpunpacku_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 001 ooooo 0111 00010 qqqqq ppppp 0 cpunpacku.h =croc,crqc,crpc (c3_1)
+(dni cpunpacku_h_C3 "cpunpacku.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_h") (CPTYPE V4UHI) (CRET FIRST))
+ "cpunpacku.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
+ (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpunpacku_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 010 ooooo 0111 00010 qqqqq ppppp 0 cpunpacku.w =croc,crqc,crpc (c3_1)
+(dni cpunpacku_w_C3 "cpunpacku.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_w") (CPTYPE V2USI) (CRET FIRST))
+ "cpunpacku.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
+ (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpunpacku_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 100 ooooo 0111 00010 qqqqq ppppp 0 cpunpackl.b =croc,crqc,crpc (c3_1)
+(dni cpunpackl_b_C3 "cpunpackl.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpunpackl.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
+ (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpunpackl_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 101 ooooo 0111 00010 qqqqq ppppp 0 cpunpackl.h =croc,crqc,crpc (c3_1)
+(dni cpunpackl_h_C3 "cpunpackl.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpunpackl.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
+ (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpunpackl_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 110 ooooo 0111 00010 qqqqq ppppp 0 cpunpackl.w =croc,crqc,crpc (c3_1)
+(dni cpunpackl_w_C3 "cpunpackl.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpunpackl.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
+ (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpunpackl_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 100 ooooo 0111 00011 qqqqq ppppp 0 cppacku.b =croc,crqc,crpc (c3_1)
+(dni cppacku_b_C3 "cppacku.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacku_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cppacku.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
+ (f-ivc2-5u16 #x3) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cppacku_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 101 ooooo 0111 00011 qqqqq ppppp 0 cppack.b =croc,crqc,crpc (c3_1)
+(dni cppack_b_C3 "cppack.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppack_b") (CPTYPE V8QI) (CRET FIRST))
+ "cppack.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
+ (f-ivc2-5u16 #x3) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cppack_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 111 ooooo 0111 00011 qqqqq ppppp 0 cppack.h =croc,crqc,crpc (c3_1)
+(dni cppack_h_C3 "cppack.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppack_h") (CPTYPE V4HI) (CRET FIRST))
+ "cppack.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7)
+ (f-ivc2-5u16 #x3) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cppack_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 qqqqq ppppp 0 cpsrl3.b =croc,crqc,crpc (c3_1)
+(dni cpsrl3_b_C3 "cpsrl3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpsrl3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsrl3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 001 ooooo 0111 00100 qqqqq ppppp 0 cpssrl3.b =croc,crqc,crpc (c3_1)
+(dni cpssrl3_b_C3 "cpssrl3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpssrl3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpssrl3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 010 ooooo 0111 00100 qqqqq ppppp 0 cpsrl3.h =croc,crqc,crpc (c3_1)
+(dni cpsrl3_h_C3 "cpsrl3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsrl3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsrl3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 011 ooooo 0111 00100 qqqqq ppppp 0 cpssrl3.h =croc,crqc,crpc (c3_1)
+(dni cpssrl3_h_C3 "cpssrl3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpssrl3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpssrl3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 100 ooooo 0111 00100 qqqqq ppppp 0 cpsrl3.w =croc,crqc,crpc (c3_1)
+(dni cpsrl3_w_C3 "cpsrl3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsrl3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsrl3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 101 ooooo 0111 00100 qqqqq ppppp 0 cpssrl3.w =croc,crqc,crpc (c3_1)
+(dni cpssrl3_w_C3 "cpssrl3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpssrl3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpssrl3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 110 ooooo 0111 00100 qqqqq ppppp 0 cdsrl3 =croc,crqc,crpc (c3_1)
+(dni cdsrl3_C3 "cdsrl3 $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrl3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdsrl3 $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cdsrl3" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00101 qqqqq ppppp 0 cpsra3.b =croc,crqc,crpc (c3_1)
+(dni cpsra3_b_C3 "cpsra3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpsra3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsra3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 001 ooooo 0111 00101 qqqqq ppppp 0 cpssra3.b =croc,crqc,crpc (c3_1)
+(dni cpssra3_b_C3 "cpssra3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpssra3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
+ (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpssra3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 010 ooooo 0111 00101 qqqqq ppppp 0 cpsra3.h =croc,crqc,crpc (c3_1)
+(dni cpsra3_h_C3 "cpsra3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsra3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
+ (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsra3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 011 ooooo 0111 00101 qqqqq ppppp 0 cpssra3.h =croc,crqc,crpc (c3_1)
+(dni cpssra3_h_C3 "cpssra3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpssra3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
+ (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpssra3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 100 ooooo 0111 00101 qqqqq ppppp 0 cpsra3.w =croc,crqc,crpc (c3_1)
+(dni cpsra3_w_C3 "cpsra3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsra3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
+ (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsra3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 101 ooooo 0111 00101 qqqqq ppppp 0 cpssra3.w =croc,crqc,crpc (c3_1)
+(dni cpssra3_w_C3 "cpssra3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpssra3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
+ (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpssra3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 110 ooooo 0111 00101 qqqqq ppppp 0 cdsra3 =croc,crqc,crpc (c3_1)
+(dni cdsra3_C3 "cdsra3 $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsra3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdsra3 $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
+ (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cdsra3" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00110 qqqqq ppppp 0 cpsll3.b =croc,crqc,crpc (c3_1)
+(dni cpsll3_b_C3 "cpsll3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpsll3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsll3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 001 ooooo 0111 00110 qqqqq ppppp 0 cpssll3.b =croc,crqc,crpc (c3_1)
+(dni cpssll3_b_C3 "cpssll3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpssll3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
+ (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpssll3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 010 ooooo 0111 00110 qqqqq ppppp 0 cpsll3.h =croc,crqc,crpc (c3_1)
+(dni cpsll3_h_C3 "cpsll3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsll3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
+ (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsll3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 011 ooooo 0111 00110 qqqqq ppppp 0 cpssll3.h =croc,crqc,crpc (c3_1)
+(dni cpssll3_h_C3 "cpssll3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpssll3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
+ (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpssll3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 100 ooooo 0111 00110 qqqqq ppppp 0 cpsll3.w =croc,crqc,crpc (c3_1)
+(dni cpsll3_w_C3 "cpsll3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsll3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
+ (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsll3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 101 ooooo 0111 00110 qqqqq ppppp 0 cpssll3.w =croc,crqc,crpc (c3_1)
+(dni cpssll3_w_C3 "cpssll3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpssll3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
+ (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpssll3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 110 ooooo 0111 00110 qqqqq ppppp 0 cdsll3 =croc,crqc,crpc (c3_1)
+(dni cdsll3_C3 "cdsll3 $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsll3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdsll3 $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
+ (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cdsll3" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 010 ooooo 0111 00111 qqqqq ppppp 0 cpsla3.h =croc,crqc,crpc (c3_1)
+(dni cpsla3_h_C3 "cpsla3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsla3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsla3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
+ (f-ivc2-5u16 #x7) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsla3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 100 ooooo 0111 00111 qqqqq ppppp 0 cpsla3.w =croc,crqc,crpc (c3_1)
+(dni cpsla3_w_C3 "cpsla3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsla3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsla3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
+ (f-ivc2-5u16 #x7) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsla3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 010 ooooo 0111 01000 qqqqq ppppp 0 cpsadd3.h =croc,crqc,crpc (c3_1)
+(dni cpsadd3_h_C3 "cpsadd3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadd3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsadd3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
+ (f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsadd3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 011 ooooo 0111 01000 qqqqq ppppp 0 cpsadd3.w =croc,crqc,crpc (c3_1)
+(dni cpsadd3_w_C3 "cpsadd3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadd3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsadd3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
+ (f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpsadd3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 110 ooooo 0111 01000 qqqqq ppppp 0 cpssub3.h =croc,crqc,crpc (c3_1)
+(dni cpssub3_h_C3 "cpssub3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssub3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpssub3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
+ (f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cofr0 0)
+ (set croc (c-call DI "ivc2_cpssub3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 111 ooooo 0111 01000 qqqqq ppppp 0 cpssub3.w =croc,crqc,crpc (c3_1)
+(dni cpssub3_w_C3 "cpssub3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssub3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpssub3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7)
+ (f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cofr0 0)
+ (set croc (c-call DI "ivc2_cpssub3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 01001 qqqqq ppppp 0 cpextuaddu3.b =croc,crqc,crpc (c3_1)
+(dni cpextuaddu3_b_C3 "cpextuaddu3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuaddu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextuaddu3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextuaddu3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 001 ooooo 0111 01001 qqqqq ppppp 0 cpextuadd3.b =croc,crqc,crpc (c3_1)
+(dni cpextuadd3_b_C3 "cpextuadd3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuadd3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextuadd3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
+ (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextuadd3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 010 ooooo 0111 01001 qqqqq ppppp 0 cpextladdu3.b =croc,crqc,crpc (c3_1)
+(dni cpextladdu3_b_C3 "cpextladdu3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextladdu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextladdu3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
+ (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextladdu3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 011 ooooo 0111 01001 qqqqq ppppp 0 cpextladd3.b =croc,crqc,crpc (c3_1)
+(dni cpextladd3_b_C3 "cpextladd3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextladd3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextladd3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
+ (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextladd3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 100 ooooo 0111 01001 qqqqq ppppp 0 cpextusubu3.b =croc,crqc,crpc (c3_1)
+(dni cpextusubu3_b_C3 "cpextusubu3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextusubu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextusubu3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
+ (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextusubu3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 101 ooooo 0111 01001 qqqqq ppppp 0 cpextusub3.b =croc,crqc,crpc (c3_1)
+(dni cpextusub3_b_C3 "cpextusub3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextusub3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextusub3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
+ (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextusub3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 110 ooooo 0111 01001 qqqqq ppppp 0 cpextlsubu3.b =croc,crqc,crpc (c3_1)
+(dni cpextlsubu3_b_C3 "cpextlsubu3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlsubu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextlsubu3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
+ (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextlsubu3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 111 ooooo 0111 01001 qqqqq ppppp 0 cpextlsub3.b =croc,crqc,crpc (c3_1)
+(dni cpextlsub3_b_C3 "cpextlsub3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlsub3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextlsub3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7)
+ (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextlsub3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 01010 qqqqq ppppp 0 cpaveu3.b =croc,crqc,crpc (c3_1)
+(dni cpaveu3_b_C3 "cpaveu3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaveu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpaveu3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpaveu3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 001 ooooo 0111 01010 qqqqq ppppp 0 cpave3.b =croc,crqc,crpc (c3_1)
+(dni cpave3_b_C3 "cpave3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpave3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
+ (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpave3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 010 ooooo 0111 01010 qqqqq ppppp 0 cpave3.h =croc,crqc,crpc (c3_1)
+(dni cpave3_h_C3 "cpave3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpave3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
+ (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpave3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 011 ooooo 0111 01010 qqqqq ppppp 0 cpave3.w =croc,crqc,crpc (c3_1)
+(dni cpave3_w_C3 "cpave3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpave3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
+ (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpave3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 100 ooooo 0111 01010 qqqqq ppppp 0 cpaddsru3.b =croc,crqc,crpc (c3_1)
+(dni cpaddsru3_b_C3 "cpaddsru3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsru3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpaddsru3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
+ (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpaddsru3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 101 ooooo 0111 01010 qqqqq ppppp 0 cpaddsr3.b =croc,crqc,crpc (c3_1)
+(dni cpaddsr3_b_C3 "cpaddsr3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpaddsr3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
+ (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpaddsr3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 110 ooooo 0111 01010 qqqqq ppppp 0 cpaddsr3.h =croc,crqc,crpc (c3_1)
+(dni cpaddsr3_h_C3 "cpaddsr3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpaddsr3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
+ (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpaddsr3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 111 ooooo 0111 01010 qqqqq ppppp 0 cpaddsr3.w =croc,crqc,crpc (c3_1)
+(dni cpaddsr3_w_C3 "cpaddsr3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpaddsr3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7)
+ (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpaddsr3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 01011 qqqqq ppppp 0 cpabsu3.b =croc,crqc,crpc (c3_1)
+(dni cpabsu3_b_C3 "cpabsu3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpabsu3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #xb) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpabsu3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 001 ooooo 0111 01011 qqqqq ppppp 0 cpabs3.b =croc,crqc,crpc (c3_1)
+(dni cpabs3_b_C3 "cpabs3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabs3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpabs3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
+ (f-ivc2-5u16 #xb) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpabs3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 010 ooooo 0111 01011 qqqqq ppppp 0 cpabs3.h =croc,crqc,crpc (c3_1)
+(dni cpabs3_h_C3 "cpabs3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabs3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpabs3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
+ (f-ivc2-5u16 #xb) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpabs3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 01100 qqqqq ppppp 0 cpmaxu3.b =croc,crqc,crpc (c3_1)
+(dni cpmaxu3_b_C3 "cpmaxu3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmaxu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpmaxu3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmaxu3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 001 ooooo 0111 01100 qqqqq ppppp 0 cpmax3.b =croc,crqc,crpc (c3_1)
+(dni cpmax3_b_C3 "cpmax3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpmax3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
+ (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmax3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 011 ooooo 0111 01100 qqqqq ppppp 0 cpmax3.h =croc,crqc,crpc (c3_1)
+(dni cpmax3_h_C3 "cpmax3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpmax3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
+ (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmax3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 100 ooooo 0111 01100 qqqqq ppppp 0 cpmaxu3.w =croc,crqc,crpc (c3_1)
+(dni cpmaxu3_w_C3 "cpmaxu3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmaxu3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmaxu3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
+ (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmaxu3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 101 ooooo 0111 01100 qqqqq ppppp 0 cpmax3.w =croc,crqc,crpc (c3_1)
+(dni cpmax3_w_C3 "cpmax3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmax3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
+ (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmax3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 01101 qqqqq ppppp 0 cpminu3.b =croc,crqc,crpc (c3_1)
+(dni cpminu3_b_C3 "cpminu3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpminu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpminu3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpminu3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 001 ooooo 0111 01101 qqqqq ppppp 0 cpmin3.b =croc,crqc,crpc (c3_1)
+(dni cpmin3_b_C3 "cpmin3.b $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpmin3.b $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
+ (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmin3_b" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 011 ooooo 0111 01101 qqqqq ppppp 0 cpmin3.h =croc,crqc,crpc (c3_1)
+(dni cpmin3_h_C3 "cpmin3.h $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpmin3.h $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
+ (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmin3_h" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 100 ooooo 0111 01101 qqqqq ppppp 0 cpminu3.w =croc,crqc,crpc (c3_1)
+(dni cpminu3_w_C3 "cpminu3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpminu3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpminu3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
+ (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpminu3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 101 ooooo 0111 01101 qqqqq ppppp 0 cpmin3.w =croc,crqc,crpc (c3_1)
+(dni cpmin3_w_C3 "cpmin3.w $croc,$crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmin3.w $croc,$crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
+ (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmin3_w" pc crqc crpc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10000 00000 00000 0 cpmovfrcsar0 =croc (c3_1)
+(dni cpmovfrcsar0_C3 "cpmovfrcsar0 $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcsar0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpmovfrcsar0 $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x10) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmovfrcsar0" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10000 00000 01111 0 cpmovfrcsar1 =croc (c3_1)
+(dni cpmovfrcsar1_C3 "cpmovfrcsar1 $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcsar1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpmovfrcsar1 $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x10) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #xf) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmovfrcsar1" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10000 00000 00001 0 cpmovfrcc =croc (c3_1)
+(dni cpmovfrcc_C3 "cpmovfrcc $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcc") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpmovfrcc $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x10) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x1) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmovfrcc" pc)) )
+ ()
+ )
+
+; 1111 0000 0000 0111 10000 qqqqq 10000 0 cpmovtocsar0 crqc (c3_1)
+(dni cpmovtocsar0_C3 "cpmovtocsar0 $crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar0"))
+ "cpmovtocsar0 $crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
+ (f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpmovtocsar0" pc crqc) )
+ ()
+ )
+
+; 1111 0000 0000 0111 10000 qqqqq 11111 0 cpmovtocsar1 crqc (c3_1)
+(dni cpmovtocsar1_C3 "cpmovtocsar1 $crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar1"))
+ "cpmovtocsar1 $crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
+ (f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x1f) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpmovtocsar1" pc crqc) )
+ ()
+ )
+
+; 1111 0000 0000 0111 10000 qqqqq 10001 0 cpmovtocc crqc (c3_1)
+(dni cpmovtocc_C3 "cpmovtocc $crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocc"))
+ "cpmovtocc $crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
+ (f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpmovtocc" pc crqc) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 00000 0 cpmov =croc,crqc (c3_1)
+(dni cpmov_C3 "cpmov $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmov") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpmov $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmov" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 00001 0 cpabsz.b =croc,crqc (c3_1)
+(dni cpabsz_b_C3 "cpabsz.b $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpabsz.b $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpabsz_b" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 00010 0 cpabsz.h =croc,crqc (c3_1)
+(dni cpabsz_h_C3 "cpabsz.h $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpabsz.h $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x2) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpabsz_h" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 00011 0 cpabsz.w =croc,crqc (c3_1)
+(dni cpabsz_w_C3 "cpabsz.w $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpabsz.w $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x3) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpabsz_w" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 00100 0 cpldz.h =croc,crqc (c3_1)
+(dni cpldz_h_C3 "cpldz.h $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpldz_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpldz.h $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x4) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpldz_h" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 00101 0 cpldz.w =croc,crqc (c3_1)
+(dni cpldz_w_C3 "cpldz.w $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpldz_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpldz.w $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x5) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpldz_w" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 00110 0 cpnorm.h =croc,crqc (c3_1)
+(dni cpnorm_h_C3 "cpnorm.h $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnorm_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpnorm.h $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x6) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpnorm_h" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 00111 0 cpnorm.w =croc,crqc (c3_1)
+(dni cpnorm_w_C3 "cpnorm.w $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnorm_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpnorm.w $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x7) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpnorm_w" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 01000 0 cphaddu.b =croc,crqc (c3_1)
+(dni cphaddu_b_C3 "cphaddu.b $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphaddu_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cphaddu.b $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x8) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cphaddu_b" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 01001 0 cphadd.b =croc,crqc (c3_1)
+(dni cphadd_b_C3 "cphadd.b $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_b") (CPTYPE V8QI) (CRET FIRST))
+ "cphadd.b $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x9) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cphadd_b" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 01010 0 cphadd.h =croc,crqc (c3_1)
+(dni cphadd_h_C3 "cphadd.h $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_h") (CPTYPE V4HI) (CRET FIRST))
+ "cphadd.h $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xa) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cphadd_h" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 01011 0 cphadd.w =croc,crqc (c3_1)
+(dni cphadd_w_C3 "cphadd.w $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_w") (CPTYPE V2SI) (CRET FIRST))
+ "cphadd.w $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xb) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cphadd_w" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 01100 0 cpccadd.b +crqc (c3_1)
+(dni cpccadd_b_C3 "cpccadd.b $crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpccadd_b") (CPTYPE V8QI) (CRET FIRSTCOPY))
+ "cpccadd.b $crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xc) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpccadd_b" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 01101 0 cpbcast.b =croc,crqc (c3_1)
+(dni cpbcast_b_C3 "cpbcast.b $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpbcast.b $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xd) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpbcast_b" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 01110 0 cpbcast.h =croc,crqc (c3_1)
+(dni cpbcast_h_C3 "cpbcast.h $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpbcast.h $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xe) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpbcast_h" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 01111 0 cpbcast.w =croc,crqc (c3_1)
+(dni cpbcast_w_C3 "cpbcast.w $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpbcast.w $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xf) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpbcast_w" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 10000 0 cpextuu.b =croc,crqc (c3_1)
+(dni cpextuu_b_C3 "cpextuu.b $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuu_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cpextuu.b $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextuu_b" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 10001 0 cpextu.b =croc,crqc (c3_1)
+(dni cpextu_b_C3 "cpextu.b $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextu_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cpextu.b $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextu_b" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 10010 0 cpextuu.h =croc,crqc (c3_1)
+(dni cpextuu_h_C3 "cpextuu.h $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuu_h") (CPTYPE V4UHI) (CRET FIRST))
+ "cpextuu.h $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x12) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextuu_h" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 10011 0 cpextu.h =croc,crqc (c3_1)
+(dni cpextu_h_C3 "cpextu.h $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextu_h") (CPTYPE V4UHI) (CRET FIRST))
+ "cpextu.h $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x13) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextu_h" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 10100 0 cpextlu.b =croc,crqc (c3_1)
+(dni cpextlu_b_C3 "cpextlu.b $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlu_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cpextlu.b $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x14) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextlu_b" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 10101 0 cpextl.b =croc,crqc (c3_1)
+(dni cpextl_b_C3 "cpextl.b $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextl_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextl.b $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x15) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextl_b" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 10110 0 cpextlu.h =croc,crqc (c3_1)
+(dni cpextlu_h_C3 "cpextlu.h $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlu_h") (CPTYPE V4UHI) (CRET FIRST))
+ "cpextlu.h $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x16) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextlu_h" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 10111 0 cpextl.h =croc,crqc (c3_1)
+(dni cpextl_h_C3 "cpextl.h $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextl_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpextl.h $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x17) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpextl_h" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 11000 0 cpcastub.h =croc,crqc (c3_1)
+(dni cpcastub_h_C3 "cpcastub.h $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastub_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpcastub.h $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x18) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpcastub_h" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 11001 0 cpcastb.h =croc,crqc (c3_1)
+(dni cpcastb_h_C3 "cpcastb.h $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastb_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpcastb.h $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x19) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpcastb_h" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 11100 0 cpcastub.w =croc,crqc (c3_1)
+(dni cpcastub_w_C3 "cpcastub.w $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastub_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpcastub.w $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1c) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpcastub_w" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 11101 0 cpcastb.w =croc,crqc (c3_1)
+(dni cpcastb_w_C3 "cpcastb.w $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastb_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpcastb.w $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1d) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpcastb_w" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 11110 0 cpcastuh.w =croc,crqc (c3_1)
+(dni cpcastuh_w_C3 "cpcastuh.w $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastuh_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpcastuh.w $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1e) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpcastuh_w" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 11111 0 cpcasth.w =croc,crqc (c3_1)
+(dni cpcasth_w_C3 "cpcasth.w $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcasth_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpcasth.w $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1f) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpcasth_w" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 11010 0 cdcastuw =croc,crqc (c3_1)
+(dni cdcastuw_C3 "cdcastuw $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdcastuw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdcastuw $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1a) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cdcastuw" pc crqc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 10001 qqqqq 11011 0 cdcastw =croc,crqc (c3_1)
+(dni cdcastw_C3 "cdcastw $croc,$crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdcastw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdcastw $croc,$crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1b) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cdcastw" pc crqc)) )
+ ()
+ )
+
+; 1111 0000 0000 0111 10010 qqqqq ppppp 0 cpcmpeqz.b crqc,crpc (c3_1)
+(dni cpcmpeqz_b_C3 "cpcmpeqz.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeqz_b") (CPTYPE V8QI))
+ "cpcmpeqz.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpeqz_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0001 0111 10010 qqqqq ppppp 0 cpcmpeq.b crqc,crpc (c3_1)
+(dni cpcmpeq_b_C3 "cpcmpeq.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_b") (CPTYPE V8QI))
+ "cpcmpeq.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpeq_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0011 0111 10010 qqqqq ppppp 0 cpcmpeq.h crqc,crpc (c3_1)
+(dni cpcmpeq_h_C3 "cpcmpeq.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_h") (CPTYPE V4HI))
+ "cpcmpeq.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x3) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpeq_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0101 0111 10010 qqqqq ppppp 0 cpcmpeq.w crqc,crpc (c3_1)
+(dni cpcmpeq_w_C3 "cpcmpeq.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_w") (CPTYPE V2SI))
+ "cpcmpeq.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpeq_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1001 0111 10010 qqqqq ppppp 0 cpcmpne.b crqc,crpc (c3_1)
+(dni cpcmpne_b_C3 "cpcmpne.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_b") (CPTYPE V8QI))
+ "cpcmpne.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpne_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1011 0111 10010 qqqqq ppppp 0 cpcmpne.h crqc,crpc (c3_1)
+(dni cpcmpne_h_C3 "cpcmpne.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_h") (CPTYPE V4HI))
+ "cpcmpne.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpne_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1101 0111 10010 qqqqq ppppp 0 cpcmpne.w crqc,crpc (c3_1)
+(dni cpcmpne_w_C3 "cpcmpne.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_w") (CPTYPE V2SI))
+ "cpcmpne.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpne_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0000 0111 10010 qqqqq ppppp 0 cpcmpgtu.b crqc,crpc (c3_1)
+(dni cpcmpgtu_b_C3 "cpcmpgtu.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_b") (CPTYPE V8UQI))
+ "cpcmpgtu.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgtu_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0001 0111 10010 qqqqq ppppp 0 cpcmpgt.b crqc,crpc (c3_1)
+(dni cpcmpgt_b_C3 "cpcmpgt.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_b") (CPTYPE V8QI))
+ "cpcmpgt.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgt_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0011 0111 10010 qqqqq ppppp 0 cpcmpgt.h crqc,crpc (c3_1)
+(dni cpcmpgt_h_C3 "cpcmpgt.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_h") (CPTYPE V4HI))
+ "cpcmpgt.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgt_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0100 0111 10010 qqqqq ppppp 0 cpcmpgtu.w crqc,crpc (c3_1)
+(dni cpcmpgtu_w_C3 "cpcmpgtu.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_w") (CPTYPE V2USI))
+ "cpcmpgtu.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgtu_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0101 0111 10010 qqqqq ppppp 0 cpcmpgt.w crqc,crpc (c3_1)
+(dni cpcmpgt_w_C3 "cpcmpgt.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_w") (CPTYPE V2SI))
+ "cpcmpgt.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgt_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 1000 0111 10010 qqqqq ppppp 0 cpcmpgeu.b crqc,crpc (c3_1)
+(dni cpcmpgeu_b_C3 "cpcmpgeu.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_b") (CPTYPE V8UQI))
+ "cpcmpgeu.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x18) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgeu_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 1001 0111 10010 qqqqq ppppp 0 cpcmpge.b crqc,crpc (c3_1)
+(dni cpcmpge_b_C3 "cpcmpge.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_b") (CPTYPE V8QI))
+ "cpcmpge.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x19) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpge_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 1011 0111 10010 qqqqq ppppp 0 cpcmpge.h crqc,crpc (c3_1)
+(dni cpcmpge_h_C3 "cpcmpge.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_h") (CPTYPE V4HI))
+ "cpcmpge.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1b) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpge_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 1100 0111 10010 qqqqq ppppp 0 cpcmpgeu.w crqc,crpc (c3_1)
+(dni cpcmpgeu_w_C3 "cpcmpgeu.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_w") (CPTYPE V2USI))
+ "cpcmpgeu.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1c) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgeu_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 1101 0111 10010 qqqqq ppppp 0 cpcmpge.w crqc,crpc (c3_1)
+(dni cpcmpge_w_C3 "cpcmpge.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_w") (CPTYPE V2SI))
+ "cpcmpge.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1d) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpge_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0010 0001 0111 10010 qqqqq ppppp 0 cpacmpeq.b crqc,crpc (c3_1)
+(dni cpacmpeq_b_C3 "cpacmpeq.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_b") (CPTYPE V8QI))
+ "cpacmpeq.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpeq_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0010 0011 0111 10010 qqqqq ppppp 0 cpacmpeq.h crqc,crpc (c3_1)
+(dni cpacmpeq_h_C3 "cpacmpeq.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_h") (CPTYPE V4HI))
+ "cpacmpeq.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x3) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpeq_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0010 0101 0111 10010 qqqqq ppppp 0 cpacmpeq.w crqc,crpc (c3_1)
+(dni cpacmpeq_w_C3 "cpacmpeq.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_w") (CPTYPE V2SI))
+ "cpacmpeq.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x5) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpeq_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0010 1001 0111 10010 qqqqq ppppp 0 cpacmpne.b crqc,crpc (c3_1)
+(dni cpacmpne_b_C3 "cpacmpne.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_b") (CPTYPE V8QI))
+ "cpacmpne.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x9) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpne_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0010 1011 0111 10010 qqqqq ppppp 0 cpacmpne.h crqc,crpc (c3_1)
+(dni cpacmpne_h_C3 "cpacmpne.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_h") (CPTYPE V4HI))
+ "cpacmpne.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #xb) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpne_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0010 1101 0111 10010 qqqqq ppppp 0 cpacmpne.w crqc,crpc (c3_1)
+(dni cpacmpne_w_C3 "cpacmpne.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_w") (CPTYPE V2SI))
+ "cpacmpne.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #xd) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpne_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 0000 0111 10010 qqqqq ppppp 0 cpacmpgtu.b crqc,crpc (c3_1)
+(dni cpacmpgtu_b_C3 "cpacmpgtu.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgtu_b") (CPTYPE V8UQI))
+ "cpacmpgtu.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x10) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpgtu_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 0001 0111 10010 qqqqq ppppp 0 cpacmpgt.b crqc,crpc (c3_1)
+(dni cpacmpgt_b_C3 "cpacmpgt.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_b") (CPTYPE V8QI))
+ "cpacmpgt.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x11) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpgt_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 0011 0111 10010 qqqqq ppppp 0 cpacmpgt.h crqc,crpc (c3_1)
+(dni cpacmpgt_h_C3 "cpacmpgt.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_h") (CPTYPE V4HI))
+ "cpacmpgt.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x13) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpgt_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 0100 0111 10010 qqqqq ppppp 0 cpacmpgtu.w crqc,crpc (c3_1)
+(dni cpacmpgtu_w_C3 "cpacmpgtu.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgtu_w") (CPTYPE V2USI))
+ "cpacmpgtu.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x14) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpgtu_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 0101 0111 10010 qqqqq ppppp 0 cpacmpgt.w crqc,crpc (c3_1)
+(dni cpacmpgt_w_C3 "cpacmpgt.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_w") (CPTYPE V2SI))
+ "cpacmpgt.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x15) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpgt_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 1000 0111 10010 qqqqq ppppp 0 cpacmpgeu.b crqc,crpc (c3_1)
+(dni cpacmpgeu_b_C3 "cpacmpgeu.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgeu_b") (CPTYPE V8UQI))
+ "cpacmpgeu.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x18) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpgeu_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 1001 0111 10010 qqqqq ppppp 0 cpacmpge.b crqc,crpc (c3_1)
+(dni cpacmpge_b_C3 "cpacmpge.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_b") (CPTYPE V8QI))
+ "cpacmpge.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x19) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpge_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 1011 0111 10010 qqqqq ppppp 0 cpacmpge.h crqc,crpc (c3_1)
+(dni cpacmpge_h_C3 "cpacmpge.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_h") (CPTYPE V4HI))
+ "cpacmpge.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1b) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpge_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 1100 0111 10010 qqqqq ppppp 0 cpacmpgeu.w crqc,crpc (c3_1)
+(dni cpacmpgeu_w_C3 "cpacmpgeu.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgeu_w") (CPTYPE V2USI))
+ "cpacmpgeu.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1c) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpgeu_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 1101 0111 10010 qqqqq ppppp 0 cpacmpge.w crqc,crpc (c3_1)
+(dni cpacmpge_w_C3 "cpacmpge.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_w") (CPTYPE V2SI))
+ "cpacmpge.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1d) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpacmpge_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0100 0001 0111 10010 qqqqq ppppp 0 cpocmpeq.b crqc,crpc (c3_1)
+(dni cpocmpeq_b_C3 "cpocmpeq.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_b") (CPTYPE V8QI))
+ "cpocmpeq.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpeq_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0100 0011 0111 10010 qqqqq ppppp 0 cpocmpeq.h crqc,crpc (c3_1)
+(dni cpocmpeq_h_C3 "cpocmpeq.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_h") (CPTYPE V4HI))
+ "cpocmpeq.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x3) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpeq_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0100 0101 0111 10010 qqqqq ppppp 0 cpocmpeq.w crqc,crpc (c3_1)
+(dni cpocmpeq_w_C3 "cpocmpeq.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_w") (CPTYPE V2SI))
+ "cpocmpeq.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x5) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpeq_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0100 1001 0111 10010 qqqqq ppppp 0 cpocmpne.b crqc,crpc (c3_1)
+(dni cpocmpne_b_C3 "cpocmpne.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_b") (CPTYPE V8QI))
+ "cpocmpne.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x9) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpne_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0100 1011 0111 10010 qqqqq ppppp 0 cpocmpne.h crqc,crpc (c3_1)
+(dni cpocmpne_h_C3 "cpocmpne.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_h") (CPTYPE V4HI))
+ "cpocmpne.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xb) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpne_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0100 1101 0111 10010 qqqqq ppppp 0 cpocmpne.w crqc,crpc (c3_1)
+(dni cpocmpne_w_C3 "cpocmpne.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_w") (CPTYPE V2SI))
+ "cpocmpne.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xd) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpne_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0101 0000 0111 10010 qqqqq ppppp 0 cpocmpgtu.b crqc,crpc (c3_1)
+(dni cpocmpgtu_b_C3 "cpocmpgtu.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgtu_b") (CPTYPE V8UQI))
+ "cpocmpgtu.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x10) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpgtu_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0101 0001 0111 10010 qqqqq ppppp 0 cpocmpgt.b crqc,crpc (c3_1)
+(dni cpocmpgt_b_C3 "cpocmpgt.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_b") (CPTYPE V8QI))
+ "cpocmpgt.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x11) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpgt_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0101 0011 0111 10010 qqqqq ppppp 0 cpocmpgt.h crqc,crpc (c3_1)
+(dni cpocmpgt_h_C3 "cpocmpgt.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_h") (CPTYPE V4HI))
+ "cpocmpgt.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x13) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpgt_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0101 0100 0111 10010 qqqqq ppppp 0 cpocmpgtu.w crqc,crpc (c3_1)
+(dni cpocmpgtu_w_C3 "cpocmpgtu.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgtu_w") (CPTYPE V2USI))
+ "cpocmpgtu.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x14) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpgtu_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0101 0101 0111 10010 qqqqq ppppp 0 cpocmpgt.w crqc,crpc (c3_1)
+(dni cpocmpgt_w_C3 "cpocmpgt.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_w") (CPTYPE V2SI))
+ "cpocmpgt.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x15) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpgt_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0101 1000 0111 10010 qqqqq ppppp 0 cpocmpgeu.b crqc,crpc (c3_1)
+(dni cpocmpgeu_b_C3 "cpocmpgeu.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgeu_b") (CPTYPE V8UQI))
+ "cpocmpgeu.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x18) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpgeu_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0101 1001 0111 10010 qqqqq ppppp 0 cpocmpge.b crqc,crpc (c3_1)
+(dni cpocmpge_b_C3 "cpocmpge.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_b") (CPTYPE V8QI))
+ "cpocmpge.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x19) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpge_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0101 1011 0111 10010 qqqqq ppppp 0 cpocmpge.h crqc,crpc (c3_1)
+(dni cpocmpge_h_C3 "cpocmpge.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_h") (CPTYPE V4HI))
+ "cpocmpge.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1b) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpge_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0101 1100 0111 10010 qqqqq ppppp 0 cpocmpgeu.w crqc,crpc (c3_1)
+(dni cpocmpgeu_w_C3 "cpocmpgeu.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgeu_w") (CPTYPE V2USI))
+ "cpocmpgeu.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1c) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpgeu_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0101 1101 0111 10010 qqqqq ppppp 0 cpocmpge.w crqc,crpc (c3_1)
+(dni cpocmpge_w_C3 "cpocmpge.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_w") (CPTYPE V2SI))
+ "cpocmpge.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1d) (f-sub4 7)
+ (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpocmpge_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 00xx xiii 0111 10100 qqqqq ppppp 0 cpsrli3.b =crqc,crpc,imm3p9 (c3_imm)
+(dni cpsrli3_b_C3 "cpsrli3.b $crqc,$crpc,imm3p9 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpsrli3.b $crqc,$crpc,$imm3p9"
+ (+ MAJ_15 ivc-x-6-3 (f-ivc2-2u4 #x0) imm3p9 (f-sub4 7)
+ (f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpsrli3_b" pc crpc imm3p9)) )
+ ()
+ )
+
+; 1111 01xx iiii 0111 10100 qqqqq ppppp 0 cpsrli3.h =crqc,crpc,imm4p8 (c3_imm)
+(dni cpsrli3_h_C3 "cpsrli3.h $crqc,$crpc,imm4p8 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsrli3.h $crqc,$crpc,$imm4p8"
+ (+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7)
+ (f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpsrli3_h" pc crpc imm4p8)) )
+ ()
+ )
+
+; 1111 10xi iiii 0111 10100 qqqqq ppppp 0 cpsrli3.w =crqc,crpc,imm5p7 (c3_imm)
+(dni cpsrli3_w_C3 "cpsrli3.w $crqc,$crpc,imm5p7 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsrli3.w $crqc,$crpc,$imm5p7"
+ (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7)
+ (f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpsrli3_w" pc crpc imm5p7)) )
+ ()
+ )
+
+; 1111 11ii iiii 0111 10100 qqqqq ppppp 0 cdsrli3 =crqc,crpc,imm6p6 (c3_imm)
+(dni cdsrli3_C3 "cdsrli3 $crqc,$crpc,imm6p6 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdsrli3 $crqc,$crpc,$imm6p6"
+ (+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7)
+ (f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cdsrli3" pc crpc imm6p6)) )
+ ()
+ )
+
+; 1111 00xx xiii 0111 10101 qqqqq ppppp 0 cpsrai3.b =crqc,crpc,imm3p9 (c3_imm)
+(dni cpsrai3_b_C3 "cpsrai3.b $crqc,$crpc,imm3p9 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpsrai3.b $crqc,$crpc,$imm3p9"
+ (+ MAJ_15 ivc-x-6-3 (f-ivc2-2u4 #x0) imm3p9 (f-sub4 7)
+ (f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpsrai3_b" pc crpc imm3p9)) )
+ ()
+ )
+
+; 1111 01xx iiii 0111 10101 qqqqq ppppp 0 cpsrai3.h =crqc,crpc,imm4p8 (c3_imm)
+(dni cpsrai3_h_C3 "cpsrai3.h $crqc,$crpc,imm4p8 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsrai3.h $crqc,$crpc,$imm4p8"
+ (+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7)
+ (f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpsrai3_h" pc crpc imm4p8)) )
+ ()
+ )
+
+; 1111 10xi iiii 0111 10101 qqqqq ppppp 0 cpsrai3.w =crqc,crpc,imm5p7 (c3_imm)
+(dni cpsrai3_w_C3 "cpsrai3.w $crqc,$crpc,imm5p7 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsrai3.w $crqc,$crpc,$imm5p7"
+ (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7)
+ (f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpsrai3_w" pc crpc imm5p7)) )
+ ()
+ )
+
+; 1111 11ii iiii 0111 10101 qqqqq ppppp 0 cdsrai3 =crqc,crpc,imm6p6 (c3_imm)
+(dni cdsrai3_C3 "cdsrai3 $crqc,$crpc,imm6p6 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrai3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdsrai3 $crqc,$crpc,$imm6p6"
+ (+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7)
+ (f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cdsrai3" pc crpc imm6p6)) )
+ ()
+ )
+
+; 1111 00xx xiii 0111 10110 qqqqq ppppp 0 cpslli3.b =crqc,crpc,imm3p9 (c3_imm)
+(dni cpslli3_b_C3 "cpslli3.b $crqc,$crpc,imm3p9 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpslli3.b $crqc,$crpc,$imm3p9"
+ (+ MAJ_15 ivc-x-6-3 (f-ivc2-2u4 #x0) imm3p9 (f-sub4 7)
+ (f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpslli3_b" pc crpc imm3p9)) )
+ ()
+ )
+
+; 1111 01xx iiii 0111 10110 qqqqq ppppp 0 cpslli3.h =crqc,crpc,imm4p8 (c3_imm)
+(dni cpslli3_h_C3 "cpslli3.h $crqc,$crpc,imm4p8 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpslli3.h $crqc,$crpc,$imm4p8"
+ (+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7)
+ (f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpslli3_h" pc crpc imm4p8)) )
+ ()
+ )
+
+; 1111 10xi iiii 0111 10110 qqqqq ppppp 0 cpslli3.w =crqc,crpc,imm5p7 (c3_imm)
+(dni cpslli3_w_C3 "cpslli3.w $crqc,$crpc,imm5p7 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpslli3.w $crqc,$crpc,$imm5p7"
+ (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7)
+ (f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpslli3_w" pc crpc imm5p7)) )
+ ()
+ )
+
+; 1111 11ii iiii 0111 10110 qqqqq ppppp 0 cdslli3 =crqc,crpc,imm6p6 (c3_imm)
+(dni cdslli3_C3 "cdslli3 $crqc,$crpc,imm6p6 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdslli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdslli3 $crqc,$crpc,$imm6p6"
+ (+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7)
+ (f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cdslli3" pc crpc imm6p6)) )
+ ()
+ )
+
+; 1111 01xx iiii 0111 10111 qqqqq ppppp 0 cpslai3.h =crqc,crpc,imm4p8 (c3_imm)
+(dni cpslai3_h_C3 "cpslai3.h $crqc,$crpc,imm4p8 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslai3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpslai3.h $crqc,$crpc,$imm4p8"
+ (+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7)
+ (f-ivc2-5u16 #x17) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpslai3_h" pc crpc imm4p8)) )
+ ()
+ )
+
+; 1111 10xi iiii 0111 10111 qqqqq ppppp 0 cpslai3.w =crqc,crpc,imm5p7 (c3_imm)
+(dni cpslai3_w_C3 "cpslai3.w $crqc,$crpc,imm5p7 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslai3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpslai3.w $crqc,$crpc,$imm5p7"
+ (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7)
+ (f-ivc2-5u16 #x17) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpslai3_w" pc crpc imm5p7)) )
+ ()
+ )
+
+; 1111 00xi iiii 0111 11000 qqqqq ppppp 0 cpclipiu3.w =crqc,crpc,imm5p7 (c3_imm)
+(dni cpclipiu3_w_C3 "cpclipiu3.w $crqc,$crpc,imm5p7 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpclipiu3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpclipiu3.w $crqc,$crpc,$imm5p7"
+ (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x0) imm5p7 (f-sub4 7)
+ (f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpclipiu3_w" pc crpc imm5p7)) )
+ ()
+ )
+
+; 1111 01xi iiii 0111 11000 qqqqq ppppp 0 cpclipi3.w =crqc,crpc,imm5p7 (c3_imm)
+(dni cpclipi3_w_C3 "cpclipi3.w $crqc,$crpc,imm5p7 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpclipi3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpclipi3.w $crqc,$crpc,$imm5p7"
+ (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x1) imm5p7 (f-sub4 7)
+ (f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpclipi3_w" pc crpc imm5p7)) )
+ ()
+ )
+
+; 1111 10ii iiii 0111 11000 qqqqq ppppp 0 cdclipiu3 =crqc,crpc,imm6p6 (c3_imm)
+(dni cdclipiu3_C3 "cdclipiu3 $crqc,$crpc,imm6p6 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdclipiu3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdclipiu3 $crqc,$crpc,$imm6p6"
+ (+ MAJ_15 (f-ivc2-2u4 #x2) imm6p6 (f-sub4 7)
+ (f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cdclipiu3" pc crpc imm6p6)) )
+ ()
+ )
+
+; 1111 11ii iiii 0111 11000 qqqqq ppppp 0 cdclipi3 =crqc,crpc,imm6p6 (c3_imm)
+(dni cdclipi3_C3 "cdclipi3 $crqc,$crpc,imm6p6 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdclipi3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdclipi3 $crqc,$crpc,$imm6p6"
+ (+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7)
+ (f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cdclipi3" pc crpc imm6p6)) )
+ ()
+ )
+
+; 1111 iiii iiii 0111 11001 qqqqq 00000 0 cpmovi.b =crqc,simm8p4 (c3_imm)
+(dni cpmovi_b_C3 "cpmovi.b $crqc,simm8p4 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpmovi.b $crqc,$simm8p4"
+ (+ MAJ_15 simm8p4 (f-sub4 7)
+ (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpmovi_b" pc simm8p4)) )
+ ()
+ )
+
+; 1111 iiii iiii 0111 11001 qqqqq 00010 0 cpmoviu.h =crqc,imm8p4 (c3_imm)
+(dni cpmoviu_h_C3 "cpmoviu.h $crqc,imm8p4 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmoviu_h") (CPTYPE V4UHI) (CRET FIRST))
+ "cpmoviu.h $crqc,$imm8p4"
+ (+ MAJ_15 imm8p4 (f-sub4 7)
+ (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x2) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpmoviu_h" pc imm8p4)) )
+ ()
+ )
+
+; 1111 iiii iiii 0111 11001 qqqqq 00011 0 cpmovi.h =crqc,simm8p4 (c3_imm)
+(dni cpmovi_h_C3 "cpmovi.h $crqc,simm8p4 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpmovi.h $crqc,$simm8p4"
+ (+ MAJ_15 simm8p4 (f-sub4 7)
+ (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x3) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpmovi_h" pc simm8p4)) )
+ ()
+ )
+
+; 1111 iiii iiii 0111 11001 qqqqq 00100 0 cpmoviu.w =crqc,imm8p4 (c3_imm)
+(dni cpmoviu_w_C3 "cpmoviu.w $crqc,imm8p4 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmoviu_w") (CPTYPE V2USI) (CRET FIRST))
+ "cpmoviu.w $crqc,$imm8p4"
+ (+ MAJ_15 imm8p4 (f-sub4 7)
+ (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x4) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpmoviu_w" pc imm8p4)) )
+ ()
+ )
+
+; 1111 iiii iiii 0111 11001 qqqqq 00101 0 cpmovi.w =crqc,simm8p4 (c3_imm)
+(dni cpmovi_w_C3 "cpmovi.w $crqc,simm8p4 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovi.w $crqc,$simm8p4"
+ (+ MAJ_15 simm8p4 (f-sub4 7)
+ (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x5) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cpmovi_w" pc simm8p4)) )
+ ()
+ )
+
+; 1111 iiii iiii 0111 11001 qqqqq 00110 0 cdmoviu =crqc,imm8p4 (c3_imm)
+(dni cdmoviu_C3 "cdmoviu $crqc,imm8p4 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdmoviu") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdmoviu $crqc,$imm8p4"
+ (+ MAJ_15 imm8p4 (f-sub4 7)
+ (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x6) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cdmoviu" pc imm8p4)) )
+ ()
+ )
+
+; 1111 iiii iiii 0111 11001 qqqqq 00111 0 cdmovi =crqc,simm8p4 (c3_imm)
+(dni cdmovi_C3 "cdmovi $crqc,simm8p4 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdmovi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdmovi $crqc,$simm8p4"
+ (+ MAJ_15 simm8p4 (f-sub4 7)
+ (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x7) (f-ivc2-1u31 #x0) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqc (c-call DI "ivc2_cdmovi" pc simm8p4)) )
+ ()
+ )
+
+; 1111 0000 0000 0111 00000 qqqqq ppppp 1 cpadda1u.b crqc,crpc (c3_1)
+(dni cpadda1u_b_C3 "cpadda1u.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1u_b") (CPTYPE V8UQI))
+ "cpadda1u.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpadda1u_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0001 0111 00000 qqqqq ppppp 1 cpadda1.b crqc,crpc (c3_1)
+(dni cpadda1_b_C3 "cpadda1.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1_b") (CPTYPE V8QI))
+ "cpadda1.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpadda1_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0010 0111 00000 qqqqq ppppp 1 cpaddua1.h crqc,crpc (c3_1)
+(dni cpaddua1_h_C3 "cpaddua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddua1_h") (CPTYPE V4HI))
+ "cpaddua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x2) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpaddua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0011 0111 00000 qqqqq ppppp 1 cpaddla1.h crqc,crpc (c3_1)
+(dni cpaddla1_h_C3 "cpaddla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddla1_h") (CPTYPE V4HI))
+ "cpaddla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x3) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpaddla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0100 0111 00000 qqqqq ppppp 1 cpaddaca1u.b crqc,crpc (c3_1)
+(dni cpaddaca1u_b_C3 "cpaddaca1u.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1u_b") (CPTYPE V8UQI))
+ "cpaddaca1u.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x4) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpaddaca1u_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0101 0111 00000 qqqqq ppppp 1 cpaddaca1.b crqc,crpc (c3_1)
+(dni cpaddaca1_b_C3 "cpaddaca1.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1_b") (CPTYPE V8QI))
+ "cpaddaca1.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpaddaca1_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0110 0111 00000 qqqqq ppppp 1 cpaddacua1.h crqc,crpc (c3_1)
+(dni cpaddacua1_h_C3 "cpaddacua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacua1_h") (CPTYPE V4HI))
+ "cpaddacua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x6) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpaddacua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0111 0111 00000 qqqqq ppppp 1 cpaddacla1.h crqc,crpc (c3_1)
+(dni cpaddacla1_h_C3 "cpaddacla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacla1_h") (CPTYPE V4HI))
+ "cpaddacla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x7) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpaddacla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1000 0111 00000 qqqqq ppppp 1 cpsuba1u.b crqc,crpc (c3_1)
+(dni cpsuba1u_b_C3 "cpsuba1u.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1u_b") (CPTYPE V8UQI))
+ "cpsuba1u.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x8) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsuba1u_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1001 0111 00000 qqqqq ppppp 1 cpsuba1.b crqc,crpc (c3_1)
+(dni cpsuba1_b_C3 "cpsuba1.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1_b") (CPTYPE V8QI))
+ "cpsuba1.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsuba1_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1010 0111 00000 qqqqq ppppp 1 cpsubua1.h crqc,crpc (c3_1)
+(dni cpsubua1_h_C3 "cpsubua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubua1_h") (CPTYPE V4HI))
+ "cpsubua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xa) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsubua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1011 0111 00000 qqqqq ppppp 1 cpsubla1.h crqc,crpc (c3_1)
+(dni cpsubla1_h_C3 "cpsubla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubla1_h") (CPTYPE V4HI))
+ "cpsubla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpsubla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1100 0111 00000 qqqqq ppppp 1 cpsubaca1u.b crqc,crpc (c3_1)
+(dni cpsubaca1u_b_C3 "cpsubaca1u.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1u_b") (CPTYPE V8UQI))
+ "cpsubaca1u.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xc) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsubaca1u_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1101 0111 00000 qqqqq ppppp 1 cpsubaca1.b crqc,crpc (c3_1)
+(dni cpsubaca1_b_C3 "cpsubaca1.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1_b") (CPTYPE V8QI))
+ "cpsubaca1.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsubaca1_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1110 0111 00000 qqqqq ppppp 1 cpsubacua1.h crqc,crpc (c3_1)
+(dni cpsubacua1_h_C3 "cpsubacua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacua1_h") (CPTYPE V4HI))
+ "cpsubacua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xe) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsubacua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1111 0111 00000 qqqqq ppppp 1 cpsubacla1.h crqc,crpc (c3_1)
+(dni cpsubacla1_h_C3 "cpsubacla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacla1_h") (CPTYPE V4HI))
+ "cpsubacla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xf) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsubacla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0000 0111 00000 qqqqq ppppp 1 cpabsa1u.b crqc,crpc (c3_1)
+(dni cpabsa1u_b_C3 "cpabsa1u.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1u_b") (CPTYPE V8UQI))
+ "cpabsa1u.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpabsa1u_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0001 0111 00000 qqqqq ppppp 1 cpabsa1.b crqc,crpc (c3_1)
+(dni cpabsa1_b_C3 "cpabsa1.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1_b") (CPTYPE V8QI))
+ "cpabsa1.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpabsa1_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0010 0111 00000 qqqqq ppppp 1 cpabsua1.h crqc,crpc (c3_1)
+(dni cpabsua1_h_C3 "cpabsua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsua1_h") (CPTYPE V4HI))
+ "cpabsua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x12) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpabsua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0011 0111 00000 qqqqq ppppp 1 cpabsla1.h crqc,crpc (c3_1)
+(dni cpabsla1_h_C3 "cpabsla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsla1_h") (CPTYPE V4HI))
+ "cpabsla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpabsla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0100 0111 00000 qqqqq ppppp 1 cpsada1u.b crqc,crpc (c3_1)
+(dni cpsada1u_b_C3 "cpsada1u.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1u_b") (CPTYPE V8UQI))
+ "cpsada1u.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsada1u_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0101 0111 00000 qqqqq ppppp 1 cpsada1.b crqc,crpc (c3_1)
+(dni cpsada1_b_C3 "cpsada1.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1_b") (CPTYPE V8QI))
+ "cpsada1.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsada1_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0110 0111 00000 qqqqq ppppp 1 cpsadua1.h crqc,crpc (c3_1)
+(dni cpsadua1_h_C3 "cpsadua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadua1_h") (CPTYPE V4HI))
+ "cpsadua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x16) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsadua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0111 0111 00000 qqqqq ppppp 1 cpsadla1.h crqc,crpc (c3_1)
+(dni cpsadla1_h_C3 "cpsadla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadla1_h") (CPTYPE V4HI))
+ "cpsadla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x17) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsadla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0010 0000 0111 00000 qqqqq ppppp 1 cpseta1.h crqc,crpc (c3_1)
+(dni cpseta1_h_C3 "cpseta1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpseta1_h") (CPTYPE V4HI))
+ "cpseta1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x0) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpseta1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0010 0010 0111 00000 qqqqq ppppp 1 cpsetua1.w crqc,crpc (c3_1)
+(dni cpsetua1_w_C3 "cpsetua1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetua1_w") (CPTYPE V2SI))
+ "cpsetua1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x2) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsetua1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0010 0011 0111 00000 qqqqq ppppp 1 cpsetla1.w crqc,crpc (c3_1)
+(dni cpsetla1_w_C3 "cpsetla1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetla1_w") (CPTYPE V2SI))
+ "cpsetla1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x3) (f-sub4 7)
+ (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpsetla1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 00000 1 cpmova1.b =croc (c3_1)
+(dni cpmova1_b_C3 "cpmova1.b $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmova1_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpmova1.b $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmova1_b" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 00010 1 cpmovua1.h =croc (c3_1)
+(dni cpmovua1_h_C3 "cpmovua1.h $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovua1_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpmovua1.h $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x2) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmovua1_h" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 00011 1 cpmovla1.h =croc (c3_1)
+(dni cpmovla1_h_C3 "cpmovla1.h $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovla1_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpmovla1.h $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x3) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmovla1_h" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 00100 1 cpmovuua1.w =croc (c3_1)
+(dni cpmovuua1_w_C3 "cpmovuua1.w $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovuua1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovuua1.w $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x4) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmovuua1_w" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 00101 1 cpmovula1.w =croc (c3_1)
+(dni cpmovula1_w_C3 "cpmovula1.w $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovula1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovula1.w $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x5) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmovula1_w" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 00110 1 cpmovlua1.w =croc (c3_1)
+(dni cpmovlua1_w_C3 "cpmovlua1.w $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovlua1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovlua1.w $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x6) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmovlua1_w" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 00111 1 cpmovlla1.w =croc (c3_1)
+(dni cpmovlla1_w_C3 "cpmovlla1.w $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovlla1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovlla1.w $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x7) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmovlla1_w" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 10000 1 cppacka1u.b =croc (c3_1)
+(dni cppacka1u_b_C3 "cppacka1u.b $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacka1u_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cppacka1u.b $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cppacka1u_b" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 10001 1 cppacka1.b =croc (c3_1)
+(dni cppacka1_b_C3 "cppacka1.b $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacka1_b") (CPTYPE V8QI) (CRET FIRST))
+ "cppacka1.b $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cppacka1_b" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 10010 1 cppackua1.h =croc (c3_1)
+(dni cppackua1_h_C3 "cppackua1.h $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackua1_h") (CPTYPE V4HI) (CRET FIRST))
+ "cppackua1.h $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x12) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cppackua1_h" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 10011 1 cppackla1.h =croc (c3_1)
+(dni cppackla1_h_C3 "cppackla1.h $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackla1_h") (CPTYPE V4HI) (CRET FIRST))
+ "cppackla1.h $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x13) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cppackla1_h" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 10100 1 cppackua1.w =croc (c3_1)
+(dni cppackua1_w_C3 "cppackua1.w $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackua1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cppackua1.w $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x14) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cppackua1_w" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 10101 1 cppackla1.w =croc (c3_1)
+(dni cppackla1_w_C3 "cppackla1.w $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackla1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cppackla1.w $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x15) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cppackla1_w" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 10110 1 cpmovhua1.w =croc (c3_1)
+(dni cpmovhua1_w_C3 "cpmovhua1.w $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovhua1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovhua1.w $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x16) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmovhua1_w" pc)) )
+ ()
+ )
+
+; 1111 000 ooooo 0111 00100 00000 10111 1 cpmovhla1.w =croc (c3_1)
+(dni cpmovhla1_w_C3 "cpmovhla1.w $croc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovhla1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovhla1.w $croc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
+ (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x17) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set croc (c-call DI "ivc2_cpmovhla1_w" pc)) )
+ ()
+ )
+
+; 1111 0000 0000 0111 00010 qqqqq 00000 1 cpsrla1 crqc (c3_1)
+(dni cpsrla1_C3 "cpsrla1 $crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrla1"))
+ "cpsrla1 $crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
+ (f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsrla1" pc crqc) )
+ ()
+ )
+
+; 1111 0000 0001 0111 00010 qqqqq 00000 1 cpsraa1 crqc (c3_1)
+(dni cpsraa1_C3 "cpsraa1 $crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsraa1"))
+ "cpsraa1 $crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7)
+ (f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsraa1" pc crqc) )
+ ()
+ )
+
+; 1111 0000 0010 0111 00010 qqqqq 00000 1 cpslla1 crqc (c3_1)
+(dni cpslla1_C3 "cpslla1 $crqc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslla1"))
+ "cpslla1 $crqc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x2) (f-sub4 7)
+ (f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpslla1" pc crqc) )
+ ()
+ )
+
+; 1111 00xi iiii 0111 00011 00000 00000 1 cpsrlia1 imm5p7 (c3_imm)
+(dni cpsrlia1_P1 "cpsrlia1 imm5p7 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrlia1"))
+ "cpsrlia1 $imm5p7"
+ (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x0) imm5p7 (f-sub4 7)
+ (f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsrlia1" pc imm5p7) )
+ ()
+ )
+
+; 1111 01xi iiii 0111 00011 00000 00000 1 cpsraia1 imm5p7 (c3_imm)
+(dni cpsraia1_P1 "cpsraia1 imm5p7 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsraia1"))
+ "cpsraia1 $imm5p7"
+ (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x1) imm5p7 (f-sub4 7)
+ (f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsraia1" pc imm5p7) )
+ ()
+ )
+
+; 1111 10xi iiii 0111 00011 00000 00000 1 cpsllia1 imm5p7 (c3_imm)
+(dni cpsllia1_P1 "cpsllia1 imm5p7 C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsllia1"))
+ "cpsllia1 $imm5p7"
+ (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7)
+ (f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsllia1" pc imm5p7) )
+ ()
+ )
+
+; 1111 0000 0000 0111 00001 qqqqq ppppp 1 cpssqa1u.b crqc,crpc (c3_1)
+(dni cpssqa1u_b_C3 "cpssqa1u.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1u_b") (CPTYPE V8UQI))
+ "cpssqa1u.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpssqa1u_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0001 0111 00001 qqqqq ppppp 1 cpssqa1.b crqc,crpc (c3_1)
+(dni cpssqa1_b_C3 "cpssqa1.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1_b") (CPTYPE V8QI))
+ "cpssqa1.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpssqa1_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0100 0111 00001 qqqqq ppppp 1 cpssda1u.b crqc,crpc (c3_1)
+(dni cpssda1u_b_C3 "cpssda1u.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1u_b") (CPTYPE V8UQI))
+ "cpssda1u.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x4) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpssda1u_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 0101 0111 00001 qqqqq ppppp 1 cpssda1.b crqc,crpc (c3_1)
+(dni cpssda1_b_C3 "cpssda1.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1_b") (CPTYPE V8QI))
+ "cpssda1.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpssda1_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1000 0111 00001 qqqqq ppppp 1 cpmula1u.b crqc,crpc (c3_1)
+(dni cpmula1u_b_C3 "cpmula1u.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1u_b") (CPTYPE V8UQI))
+ "cpmula1u.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x8) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpmula1u_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1001 0111 00001 qqqqq ppppp 1 cpmula1.b crqc,crpc (c3_1)
+(dni cpmula1_b_C3 "cpmula1.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1_b") (CPTYPE V8QI))
+ "cpmula1.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpmula1_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1010 0111 00001 qqqqq ppppp 1 cpmulua1.h crqc,crpc (c3_1)
+(dni cpmulua1_h_C3 "cpmulua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_h") (CPTYPE V4HI))
+ "cpmulua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xa) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpmulua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1011 0111 00001 qqqqq ppppp 1 cpmulla1.h crqc,crpc (c3_1)
+(dni cpmulla1_h_C3 "cpmulla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_h") (CPTYPE V4HI))
+ "cpmulla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpmulla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1100 0111 00001 qqqqq ppppp 1 cpmulua1u.w crqc,crpc (c3_1)
+(dni cpmulua1u_w_C3 "cpmulua1u.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1u_w") (CPTYPE V2USI))
+ "cpmulua1u.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xc) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpmulua1u_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1101 0111 00001 qqqqq ppppp 1 cpmulla1u.w crqc,crpc (c3_1)
+(dni cpmulla1u_w_C3 "cpmulla1u.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1u_w") (CPTYPE V2USI))
+ "cpmulla1u.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpmulla1u_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1110 0111 00001 qqqqq ppppp 1 cpmulua1.w crqc,crpc (c3_1)
+(dni cpmulua1_w_C3 "cpmulua1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_w") (CPTYPE V2SI))
+ "cpmulua1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xe) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpmulua1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0000 1111 0111 00001 qqqqq ppppp 1 cpmulla1.w crqc,crpc (c3_1)
+(dni cpmulla1_w_C3 "cpmulla1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_w") (CPTYPE V2SI))
+ "cpmulla1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xf) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpmulla1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0000 0111 00001 qqqqq ppppp 1 cpmada1u.b crqc,crpc (c3_1)
+(dni cpmada1u_b_C3 "cpmada1u.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1u_b") (CPTYPE V8UQI))
+ "cpmada1u.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmada1u_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0001 0111 00001 qqqqq ppppp 1 cpmada1.b crqc,crpc (c3_1)
+(dni cpmada1_b_C3 "cpmada1.b $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1_b") (CPTYPE V8QI))
+ "cpmada1.b $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmada1_b" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0010 0111 00001 qqqqq ppppp 1 cpmadua1.h crqc,crpc (c3_1)
+(dni cpmadua1_h_C3 "cpmadua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_h") (CPTYPE V4HI))
+ "cpmadua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x12) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmadua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0011 0111 00001 qqqqq ppppp 1 cpmadla1.h crqc,crpc (c3_1)
+(dni cpmadla1_h_C3 "cpmadla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_h") (CPTYPE V4HI))
+ "cpmadla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmadla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0100 0111 00001 qqqqq ppppp 1 cpmadua1u.w crqc,crpc (c3_1)
+(dni cpmadua1u_w_C3 "cpmadua1u.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1u_w") (CPTYPE V2USI))
+ "cpmadua1u.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmadua1u_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0101 0111 00001 qqqqq ppppp 1 cpmadla1u.w crqc,crpc (c3_1)
+(dni cpmadla1u_w_C3 "cpmadla1u.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1u_w") (CPTYPE V2USI))
+ "cpmadla1u.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmadla1u_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0110 0111 00001 qqqqq ppppp 1 cpmadua1.w crqc,crpc (c3_1)
+(dni cpmadua1_w_C3 "cpmadua1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_w") (CPTYPE V2SI))
+ "cpmadua1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x16) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmadua1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 0111 0111 00001 qqqqq ppppp 1 cpmadla1.w crqc,crpc (c3_1)
+(dni cpmadla1_w_C3 "cpmadla1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_w") (CPTYPE V2SI))
+ "cpmadla1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x17) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmadla1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 1010 0111 00001 qqqqq ppppp 1 cpmsbua1.h crqc,crpc (c3_1)
+(dni cpmsbua1_h_C3 "cpmsbua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_h") (CPTYPE V4HI))
+ "cpmsbua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1a) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmsbua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 1011 0111 00001 qqqqq ppppp 1 cpmsbla1.h crqc,crpc (c3_1)
+(dni cpmsbla1_h_C3 "cpmsbla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_h") (CPTYPE V4HI))
+ "cpmsbla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1b) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmsbla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 1100 0111 00001 qqqqq ppppp 1 cpmsbua1u.w crqc,crpc (c3_1)
+(dni cpmsbua1u_w_C3 "cpmsbua1u.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1u_w") (CPTYPE V2USI))
+ "cpmsbua1u.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1c) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmsbua1u_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 1101 0111 00001 qqqqq ppppp 1 cpmsbla1u.w crqc,crpc (c3_1)
+(dni cpmsbla1u_w_C3 "cpmsbla1u.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1u_w") (CPTYPE V2USI))
+ "cpmsbla1u.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1d) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmsbla1u_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 1110 0111 00001 qqqqq ppppp 1 cpmsbua1.w crqc,crpc (c3_1)
+(dni cpmsbua1_w_C3 "cpmsbua1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_w") (CPTYPE V2SI))
+ "cpmsbua1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1e) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmsbua1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0001 1111 0111 00001 qqqqq ppppp 1 cpmsbla1.w crqc,crpc (c3_1)
+(dni cpmsbla1_w_C3 "cpmsbla1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_w") (CPTYPE V2SI))
+ "cpmsbla1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1f) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmsbla1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 0010 0111 00001 qqqqq ppppp 1 cpsmadua1.h crqc,crpc (c3_1)
+(dni cpsmadua1_h_C3 "cpsmadua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_h") (CPTYPE V4HI))
+ "cpsmadua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x12) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 0011 0111 00001 qqqqq ppppp 1 cpsmadla1.h crqc,crpc (c3_1)
+(dni cpsmadla1_h_C3 "cpsmadla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_h") (CPTYPE V4HI))
+ "cpsmadla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x13) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 0110 0111 00001 qqqqq ppppp 1 cpsmadua1.w crqc,crpc (c3_1)
+(dni cpsmadua1_w_C3 "cpsmadua1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_w") (CPTYPE V2SI))
+ "cpsmadua1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x16) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadua1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 0111 0111 00001 qqqqq ppppp 1 cpsmadla1.w crqc,crpc (c3_1)
+(dni cpsmadla1_w_C3 "cpsmadla1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_w") (CPTYPE V2SI))
+ "cpsmadla1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x17) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadla1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 1010 0111 00001 qqqqq ppppp 1 cpsmsbua1.h crqc,crpc (c3_1)
+(dni cpsmsbua1_h_C3 "cpsmsbua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_h") (CPTYPE V4HI))
+ "cpsmsbua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1a) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 1011 0111 00001 qqqqq ppppp 1 cpsmsbla1.h crqc,crpc (c3_1)
+(dni cpsmsbla1_h_C3 "cpsmsbla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_h") (CPTYPE V4HI))
+ "cpsmsbla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1b) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 1110 0111 00001 qqqqq ppppp 1 cpsmsbua1.w crqc,crpc (c3_1)
+(dni cpsmsbua1_w_C3 "cpsmsbua1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_w") (CPTYPE V2SI))
+ "cpsmsbua1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1e) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbua1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0011 1111 0111 00001 qqqqq ppppp 1 cpsmsbla1.w crqc,crpc (c3_1)
+(dni cpsmsbla1_w_C3 "cpsmsbla1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_w") (CPTYPE V2SI))
+ "cpsmsbla1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1f) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbla1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0100 1010 0111 00001 qqqqq ppppp 1 cpmulslua1.h crqc,crpc (c3_1)
+(dni cpmulslua1_h_C3 "cpmulslua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_h") (CPTYPE V4HI))
+ "cpmulslua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xa) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmulslua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0100 1011 0111 00001 qqqqq ppppp 1 cpmulslla1.h crqc,crpc (c3_1)
+(dni cpmulslla1_h_C3 "cpmulslla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_h") (CPTYPE V4HI))
+ "cpmulslla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xb) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmulslla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0100 1110 0111 00001 qqqqq ppppp 1 cpmulslua1.w crqc,crpc (c3_1)
+(dni cpmulslua1_w_C3 "cpmulslua1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_w") (CPTYPE V2SI))
+ "cpmulslua1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xe) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmulslua1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0100 1111 0111 00001 qqqqq ppppp 1 cpmulslla1.w crqc,crpc (c3_1)
+(dni cpmulslla1_w_C3 "cpmulslla1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_w") (CPTYPE V2SI))
+ "cpmulslla1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xf) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmulslla1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0111 0010 0111 00001 qqqqq ppppp 1 cpsmadslua1.h crqc,crpc (c3_1)
+(dni cpsmadslua1_h_C3 "cpsmadslua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_h") (CPTYPE V4HI))
+ "cpsmadslua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x12) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadslua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0111 0011 0111 00001 qqqqq ppppp 1 cpsmadslla1.h crqc,crpc (c3_1)
+(dni cpsmadslla1_h_C3 "cpsmadslla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_h") (CPTYPE V4HI))
+ "cpsmadslla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x13) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadslla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0111 0110 0111 00001 qqqqq ppppp 1 cpsmadslua1.w crqc,crpc (c3_1)
+(dni cpsmadslua1_w_C3 "cpsmadslua1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_w") (CPTYPE V2SI))
+ "cpsmadslua1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x16) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadslua1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0111 0111 0111 00001 qqqqq ppppp 1 cpsmadslla1.w crqc,crpc (c3_1)
+(dni cpsmadslla1_w_C3 "cpsmadslla1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_w") (CPTYPE V2SI))
+ "cpsmadslla1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x17) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadslla1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0111 1010 0111 00001 qqqqq ppppp 1 cpsmsbslua1.h crqc,crpc (c3_1)
+(dni cpsmsbslua1_h_C3 "cpsmsbslua1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_h") (CPTYPE V4HI))
+ "cpsmsbslua1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1a) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbslua1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0111 1011 0111 00001 qqqqq ppppp 1 cpsmsbslla1.h crqc,crpc (c3_1)
+(dni cpsmsbslla1_h_C3 "cpsmsbslla1.h $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_h") (CPTYPE V4HI))
+ "cpsmsbslla1.h $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1b) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbslla1_h" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0111 1110 0111 00001 qqqqq ppppp 1 cpsmsbslua1.w crqc,crpc (c3_1)
+(dni cpsmsbslua1_w_C3 "cpsmsbslua1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_w") (CPTYPE V2SI))
+ "cpsmsbslua1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1e) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbslua1_w" pc crqc crpc) )
+ ()
+ )
+
+; 1111 0111 1111 0111 00001 qqqqq ppppp 1 cpsmsbslla1.w crqc,crpc (c3_1)
+(dni cpsmsbslla1_w_C3 "cpsmsbslla1.w $crqc,$crpc C3"
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_w") (CPTYPE V2SI))
+ "cpsmsbslla1.w $crqc,$crpc"
+ (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1f) (f-sub4 7)
+ (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbslla1_w" pc crqc crpc) )
+ ()
+ )
+
+; 00000 00000 00000 00000 c0nop (p0_1)
+(dni c0nop_P0_P0S "c0nop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p0-isa (SLOTS P0,P0S) (INTRINSIC "c0nop"))
+ "c0nop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x0) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x0) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_c0nop" pc) )
+ ()
+ )
+
+; 00001 qqqqq ppppp ooooo cpadd3.b =crop,crqp,crpp (p0_1)
+(dni cpadd3_b_P0S_P1 "cpadd3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpadd3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpadd3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00010 qqqqq ppppp ooooo cpadd3.h =crop,crqp,crpp (p0_1)
+(dni cpadd3_h_P0S_P1 "cpadd3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpadd3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x2) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpadd3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 00011 qqqqq ppppp ooooo cpadd3.w =crop,crqp,crpp (p0_1)
+(dni cpadd3_w_P0S_P1 "cpadd3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpadd3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x3) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpadd3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 00101 qqqqq ppppp ooooo cpunpacku.b =crop,crqp,crpp (p0_1)
+(dni cpunpacku_b_P0S_P1 "cpunpacku.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cpunpacku.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x5) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpunpacku_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00110 qqqqq ppppp ooooo cpunpacku.h =crop,crqp,crpp (p0_1)
+(dni cpunpacku_h_P0S_P1 "cpunpacku.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_h") (CPTYPE V4UHI) (CRET FIRST))
+ "cpunpacku.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x6) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpunpacku_h" pc crqp crpp)) )
+ ()
+ )
+
+; 00111 qqqqq ppppp ooooo cpunpacku.w =crop,crqp,crpp (p0_1)
+(dni cpunpacku_w_P0S_P1 "cpunpacku.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_w") (CPTYPE V2USI) (CRET FIRST))
+ "cpunpacku.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x7) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpunpacku_w" pc crqp crpp)) )
+ ()
+ )
+
+; 01001 qqqqq ppppp ooooo cpunpackl.b =crop,crqp,crpp (p0_1)
+(dni cpunpackl_b_P0S_P1 "cpunpackl.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpunpackl.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x9) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpunpackl_b" pc crqp crpp)) )
+ ()
+ )
+
+; 01010 qqqqq ppppp ooooo cpunpackl.h =crop,crqp,crpp (p0_1)
+(dni cpunpackl_h_P0S_P1 "cpunpackl.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpunpackl.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xa) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpunpackl_h" pc crqp crpp)) )
+ ()
+ )
+
+; 01011 qqqqq ppppp ooooo cpunpackl.w =crop,crqp,crpp (p0_1)
+(dni cpunpackl_w_P0S_P1 "cpunpackl.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpunpackl.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xb) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpunpackl_w" pc crqp crpp)) )
+ ()
+ )
+
+; 00100 qqqqq ppppp ooooo cpsel =crop,crqp,crpp (p0_1)
+(dni cpsel_P0S_P1 "cpsel $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpsel") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpsel $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x4) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsel" pc crqp crpp)) )
+ ()
+ )
+
+; 01100 qqqqq ppppp ooooo cpfsftbs0 =crop,crqp,crpp (p0_1)
+(dni cpfsftbs0_P0S_P1 "cpfsftbs0 $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpfsftbs0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpfsftbs0 $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xc) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpfsftbs0" pc crqp crpp)) )
+ ()
+ )
+
+; 01101 qqqqq ppppp ooooo cpfsftbs1 =crop,crqp,crpp (p0_1)
+(dni cpfsftbs1_P0S_P1 "cpfsftbs1 $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpfsftbs1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpfsftbs1 $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xd) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpfsftbs1" pc crqp crpp)) )
+ ()
+ )
+
+; 10000 qqqqq 00000 ooooo cpmov =crop,crqp (p0_1)
+(dni cpmov_P0S_P1 "cpmov $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmov") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpmov $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x0) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmov" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 00001 ooooo cpabsz.b =crop,crqp (p0_1)
+(dni cpabsz_b_P0S_P1 "cpabsz.b $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpabsz.b $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpabsz_b" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 00010 ooooo cpabsz.h =crop,crqp (p0_1)
+(dni cpabsz_h_P0S_P1 "cpabsz.h $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpabsz.h $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpabsz_h" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 00011 ooooo cpabsz.w =crop,crqp (p0_1)
+(dni cpabsz_w_P0S_P1 "cpabsz.w $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpabsz.w $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpabsz_w" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 00100 ooooo cpldz.h =crop,crqp (p0_1)
+(dni cpldz_h_P0S_P1 "cpldz.h $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpldz_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpldz.h $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpldz_h" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 00101 ooooo cpldz.w =crop,crqp (p0_1)
+(dni cpldz_w_P0S_P1 "cpldz.w $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpldz_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpldz.w $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpldz_w" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 00110 ooooo cpnorm.h =crop,crqp (p0_1)
+(dni cpnorm_h_P0S_P1 "cpnorm.h $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpnorm_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpnorm.h $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpnorm_h" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 00111 ooooo cpnorm.w =crop,crqp (p0_1)
+(dni cpnorm_w_P0S_P1 "cpnorm.w $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpnorm_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpnorm.w $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpnorm_w" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 01000 ooooo cphaddu.b =crop,crqp (p0_1)
+(dni cphaddu_b_P0S_P1 "cphaddu.b $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphaddu_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cphaddu.b $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cphaddu_b" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 01001 ooooo cphadd.b =crop,crqp (p0_1)
+(dni cphadd_b_P0S_P1 "cphadd.b $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_b") (CPTYPE V8QI) (CRET FIRST))
+ "cphadd.b $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cphadd_b" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 01010 ooooo cphadd.h =crop,crqp (p0_1)
+(dni cphadd_h_P0S_P1 "cphadd.h $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_h") (CPTYPE V4HI) (CRET FIRST))
+ "cphadd.h $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cphadd_h" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 01011 ooooo cphadd.w =crop,crqp (p0_1)
+(dni cphadd_w_P0S_P1 "cphadd.w $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_w") (CPTYPE V2SI) (CRET FIRST))
+ "cphadd.w $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cphadd_w" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 01100 00000 cpccadd.b +crqp (p0_1)
+(dni cpccadd_b_P0S_P1 "cpccadd.b $crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpccadd_b") (CPTYPE V8QI) (CRET FIRSTCOPY))
+ "cpccadd.b $crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xc) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqp (c-call DI "ivc2_cpccadd_b" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 01101 ooooo cpbcast.b =crop,crqp (p0_1)
+(dni cpbcast_b_P0S_P1 "cpbcast.b $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpbcast.b $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpbcast_b" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 01110 ooooo cpbcast.h =crop,crqp (p0_1)
+(dni cpbcast_h_P0S_P1 "cpbcast.h $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpbcast.h $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpbcast_h" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 01111 ooooo cpbcast.w =crop,crqp (p0_1)
+(dni cpbcast_w_P0S_P1 "cpbcast.w $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpbcast.w $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpbcast_w" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 10000 ooooo cpextuu.b =crop,crqp (p0_1)
+(dni cpextuu_b_P0S_P1 "cpextuu.b $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextuu_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cpextuu.b $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x10) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextuu_b" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 10001 ooooo cpextu.b =crop,crqp (p0_1)
+(dni cpextu_b_P0S_P1 "cpextu.b $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextu_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cpextu.b $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x11) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextu_b" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 10010 ooooo cpextuu.h =crop,crqp (p0_1)
+(dni cpextuu_h_P0S_P1 "cpextuu.h $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextuu_h") (CPTYPE V4UHI) (CRET FIRST))
+ "cpextuu.h $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x12) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextuu_h" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 10011 ooooo cpextu.h =crop,crqp (p0_1)
+(dni cpextu_h_P0S_P1 "cpextu.h $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextu_h") (CPTYPE V4UHI) (CRET FIRST))
+ "cpextu.h $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x13) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextu_h" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 10100 ooooo cpextlu.b =crop,crqp (p0_1)
+(dni cpextlu_b_P0S_P1 "cpextlu.b $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextlu_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cpextlu.b $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x14) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextlu_b" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 10101 ooooo cpextl.b =crop,crqp (p0_1)
+(dni cpextl_b_P0S_P1 "cpextl.b $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextl_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextl.b $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x15) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextl_b" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 10110 ooooo cpextlu.h =crop,crqp (p0_1)
+(dni cpextlu_h_P0S_P1 "cpextlu.h $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextlu_h") (CPTYPE V4UHI) (CRET FIRST))
+ "cpextlu.h $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x16) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextlu_h" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 10111 ooooo cpextl.h =crop,crqp (p0_1)
+(dni cpextl_h_P0S_P1 "cpextl.h $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextl_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpextl.h $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x17) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextl_h" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 11000 ooooo cpcastub.h =crop,crqp (p0_1)
+(dni cpcastub_h_P0S_P1 "cpcastub.h $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastub_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpcastub.h $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x18) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpcastub_h" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 11001 ooooo cpcastb.h =crop,crqp (p0_1)
+(dni cpcastb_h_P0S_P1 "cpcastb.h $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastb_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpcastb.h $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x19) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpcastb_h" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 11100 ooooo cpcastub.w =crop,crqp (p0_1)
+(dni cpcastub_w_P0S_P1 "cpcastub.w $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastub_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpcastub.w $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1c) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpcastub_w" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 11101 ooooo cpcastb.w =crop,crqp (p0_1)
+(dni cpcastb_w_P0S_P1 "cpcastb.w $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastb_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpcastb.w $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1d) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpcastb_w" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 11110 ooooo cpcastuh.w =crop,crqp (p0_1)
+(dni cpcastuh_w_P0S_P1 "cpcastuh.w $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastuh_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpcastuh.w $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1e) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpcastuh_w" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 11111 ooooo cpcasth.w =crop,crqp (p0_1)
+(dni cpcasth_w_P0S_P1 "cpcasth.w $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcasth_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpcasth.w $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1f) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpcasth_w" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 11010 ooooo cdcastuw =crop,crqp (p0_1)
+(dni cdcastuw_P0S_P1 "cdcastuw $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cdcastuw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdcastuw $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1a) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cdcastuw" pc crqp)) )
+ ()
+ )
+
+; 10000 qqqqq 11011 ooooo cdcastw =crop,crqp (p0_1)
+(dni cdcastw_P0S_P1 "cdcastw $crop,$crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cdcastw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdcastw $crop,$crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1b) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cdcastw" pc crqp)) )
+ ()
+ )
+
+; 10001 00000 00000 ooooo cpmovfrcsar0 =crop (p0_1)
+(dni cpmovfrcsar0_P0S_P1 "cpmovfrcsar0 $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcsar0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpmovfrcsar0 $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x0) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovfrcsar0" pc)) )
+ ()
+ )
+
+; 10001 00000 01111 ooooo cpmovfrcsar1 =crop (p0_1)
+(dni cpmovfrcsar1_P0S_P1 "cpmovfrcsar1 $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcsar1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpmovfrcsar1 $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovfrcsar1" pc)) )
+ ()
+ )
+
+; 10001 00000 00001 ooooo cpmovfrcc =crop (p0_1)
+(dni cpmovfrcc_P0S_P1 "cpmovfrcc $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcc") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpmovfrcc $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovfrcc" pc)) )
+ ()
+ )
+
+; 10001 qqqqq 10000 00000 cpmovtocsar0 crqp (p0_1)
+(dni cpmovtocsar0_P0S_P1 "cpmovtocsar0 $crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar0"))
+ "cpmovtocsar0 $crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpmovtocsar0" pc crqp) )
+ ()
+ )
+
+; 10001 qqqqq 11111 00000 cpmovtocsar1 crqp (p0_1)
+(dni cpmovtocsar1_P0S_P1 "cpmovtocsar1 $crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar1"))
+ "cpmovtocsar1 $crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x1f) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpmovtocsar1" pc crqp) )
+ ()
+ )
+
+; 10001 qqqqq 10001 00000 cpmovtocc crqp (p0_1)
+(dni cpmovtocc_P0S_P1 "cpmovtocc $crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocc"))
+ "cpmovtocc $crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpmovtocc" pc crqp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 00000 cpcmpeqz.b crqp,crpp (p0_1)
+(dni cpcmpeqz_b_P0S_P1 "cpcmpeqz.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeqz_b") (CPTYPE V8QI))
+ "cpcmpeqz.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpeqz_b" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 00001 cpcmpeq.b crqp,crpp (p0_1)
+(dni cpcmpeq_b_P0S_P1 "cpcmpeq.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_b") (CPTYPE V8QI))
+ "cpcmpeq.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpeq_b" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 00011 cpcmpeq.h crqp,crpp (p0_1)
+(dni cpcmpeq_h_P0S_P1 "cpcmpeq.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_h") (CPTYPE V4HI))
+ "cpcmpeq.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpeq_h" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 00101 cpcmpeq.w crqp,crpp (p0_1)
+(dni cpcmpeq_w_P0S_P1 "cpcmpeq.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_w") (CPTYPE V2SI))
+ "cpcmpeq.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpeq_w" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 01001 cpcmpne.b crqp,crpp (p0_1)
+(dni cpcmpne_b_P0S_P1 "cpcmpne.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_b") (CPTYPE V8QI))
+ "cpcmpne.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpne_b" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 01011 cpcmpne.h crqp,crpp (p0_1)
+(dni cpcmpne_h_P0S_P1 "cpcmpne.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_h") (CPTYPE V4HI))
+ "cpcmpne.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpne_h" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 01101 cpcmpne.w crqp,crpp (p0_1)
+(dni cpcmpne_w_P0S_P1 "cpcmpne.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_w") (CPTYPE V2SI))
+ "cpcmpne.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpne_w" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 10000 cpcmpgtu.b crqp,crpp (p0_1)
+(dni cpcmpgtu_b_P0S_P1 "cpcmpgtu.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_b") (CPTYPE V8UQI))
+ "cpcmpgtu.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgtu_b" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 10001 cpcmpgt.b crqp,crpp (p0_1)
+(dni cpcmpgt_b_P0S_P1 "cpcmpgt.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_b") (CPTYPE V8QI))
+ "cpcmpgt.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgt_b" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 10011 cpcmpgt.h crqp,crpp (p0_1)
+(dni cpcmpgt_h_P0S_P1 "cpcmpgt.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_h") (CPTYPE V4HI))
+ "cpcmpgt.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgt_h" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 10100 cpcmpgtu.w crqp,crpp (p0_1)
+(dni cpcmpgtu_w_P0S_P1 "cpcmpgtu.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_w") (CPTYPE V2USI))
+ "cpcmpgtu.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgtu_w" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 10101 cpcmpgt.w crqp,crpp (p0_1)
+(dni cpcmpgt_w_P0S_P1 "cpcmpgt.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_w") (CPTYPE V2SI))
+ "cpcmpgt.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgt_w" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 11000 cpcmpgeu.b crqp,crpp (p0_1)
+(dni cpcmpgeu_b_P0S_P1 "cpcmpgeu.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_b") (CPTYPE V8UQI))
+ "cpcmpgeu.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgeu_b" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 11001 cpcmpge.b crqp,crpp (p0_1)
+(dni cpcmpge_b_P0S_P1 "cpcmpge.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_b") (CPTYPE V8QI))
+ "cpcmpge.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpge_b" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 11011 cpcmpge.h crqp,crpp (p0_1)
+(dni cpcmpge_h_P0S_P1 "cpcmpge.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_h") (CPTYPE V4HI))
+ "cpcmpge.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpge_h" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 11100 cpcmpgeu.w crqp,crpp (p0_1)
+(dni cpcmpgeu_w_P0S_P1 "cpcmpgeu.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_w") (CPTYPE V2USI))
+ "cpcmpgeu.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpgeu_w" pc crqp crpp) )
+ ()
+ )
+
+; 10010 qqqqq ppppp 11101 cpcmpge.w crqp,crpp (p0_1)
+(dni cpcmpge_w_P0S_P1 "cpcmpge.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_w") (CPTYPE V2SI))
+ "cpcmpge.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
+ (c-call "ivc2_cpcmpge_w" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 00000 cpadda0u.b crqp,crpp (p0_1)
+(dni cpadda0u_b_P0S "cpadda0u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0u_b") (CPTYPE V8UQI))
+ "cpadda0u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpadda0u_b" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 00001 cpadda0.b crqp,crpp (p0_1)
+(dni cpadda0_b_P0S "cpadda0.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0_b") (CPTYPE V8QI))
+ "cpadda0.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpadda0_b" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 00010 cpaddua0.h crqp,crpp (p0_1)
+(dni cpaddua0_h_P0S "cpaddua0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddua0_h") (CPTYPE V4HI))
+ "cpaddua0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpaddua0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 00011 cpaddla0.h crqp,crpp (p0_1)
+(dni cpaddla0_h_P0S "cpaddla0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddla0_h") (CPTYPE V4HI))
+ "cpaddla0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (c-call "ivc2_cpaddla0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 00100 cpaddaca0u.b crqp,crpp (p0_1)
+(dni cpaddaca0u_b_P0S "cpaddaca0u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0u_b") (CPTYPE V8UQI))
+ "cpaddaca0u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpaddaca0u_b" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 00101 cpaddaca0.b crqp,crpp (p0_1)
+(dni cpaddaca0_b_P0S "cpaddaca0.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0_b") (CPTYPE V8QI))
+ "cpaddaca0.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpaddaca0_b" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 00110 cpaddacua0.h crqp,crpp (p0_1)
+(dni cpaddacua0_h_P0S "cpaddacua0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacua0_h") (CPTYPE V4HI))
+ "cpaddacua0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpaddacua0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 00111 cpaddacla0.h crqp,crpp (p0_1)
+(dni cpaddacla0_h_P0S "cpaddacla0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacla0_h") (CPTYPE V4HI))
+ "cpaddacla0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpaddacla0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 01000 cpsuba0u.b crqp,crpp (p0_1)
+(dni cpsuba0u_b_P0S "cpsuba0u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0u_b") (CPTYPE V8UQI))
+ "cpsuba0u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpsuba0u_b" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 01001 cpsuba0.b crqp,crpp (p0_1)
+(dni cpsuba0_b_P0S "cpsuba0.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0_b") (CPTYPE V8QI))
+ "cpsuba0.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpsuba0_b" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 01010 cpsubua0.h crqp,crpp (p0_1)
+(dni cpsubua0_h_P0S "cpsubua0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubua0_h") (CPTYPE V4HI))
+ "cpsubua0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpsubua0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 01011 cpsubla0.h crqp,crpp (p0_1)
+(dni cpsubla0_h_P0S "cpsubla0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubla0_h") (CPTYPE V4HI))
+ "cpsubla0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (c-call "ivc2_cpsubla0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 01100 cpsubaca0u.b crqp,crpp (p0_1)
+(dni cpsubaca0u_b_P0S "cpsubaca0u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0u_b") (CPTYPE V8UQI))
+ "cpsubaca0u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpsubaca0u_b" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 01101 cpsubaca0.b crqp,crpp (p0_1)
+(dni cpsubaca0_b_P0S "cpsubaca0.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0_b") (CPTYPE V8QI))
+ "cpsubaca0.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpsubaca0_b" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 01110 cpsubacua0.h crqp,crpp (p0_1)
+(dni cpsubacua0_h_P0S "cpsubacua0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacua0_h") (CPTYPE V4HI))
+ "cpsubacua0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpsubacua0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 01111 cpsubacla0.h crqp,crpp (p0_1)
+(dni cpsubacla0_h_P0S "cpsubacla0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacla0_h") (CPTYPE V4HI))
+ "cpsubacla0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpsubacla0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 10000 cpabsa0u.b crqp,crpp (p0_1)
+(dni cpabsa0u_b_P0S "cpabsa0u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0u_b") (CPTYPE V8UQI))
+ "cpabsa0u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpabsa0u_b" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 10001 cpabsa0.b crqp,crpp (p0_1)
+(dni cpabsa0_b_P0S "cpabsa0.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0_b") (CPTYPE V8QI))
+ "cpabsa0.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpabsa0_b" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 10010 cpabsua0.h crqp,crpp (p0_1)
+(dni cpabsua0_h_P0S "cpabsua0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsua0_h") (CPTYPE V4HI))
+ "cpabsua0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpabsua0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 10011 cpabsla0.h crqp,crpp (p0_1)
+(dni cpabsla0_h_P0S "cpabsla0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsla0_h") (CPTYPE V4HI))
+ "cpabsla0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (c-call "ivc2_cpabsla0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 10100 cpsada0u.b crqp,crpp (p0_1)
+(dni cpsada0u_b_P0S "cpsada0u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0u_b") (CPTYPE V8UQI))
+ "cpsada0u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpsada0u_b" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 10101 cpsada0.b crqp,crpp (p0_1)
+(dni cpsada0_b_P0S "cpsada0.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0_b") (CPTYPE V8QI))
+ "cpsada0.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpsada0_b" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 10110 cpsadua0.h crqp,crpp (p0_1)
+(dni cpsadua0_h_P0S "cpsadua0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadua0_h") (CPTYPE V4HI))
+ "cpsadua0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpsadua0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 10111 cpsadla0.h crqp,crpp (p0_1)
+(dni cpsadla0_h_P0S "cpsadla0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadla0_h") (CPTYPE V4HI))
+ "cpsadla0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpsadla0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 11011 cpseta0.h crqp,crpp (p0_1)
+(dni cpseta0_h_P0S "cpseta0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpseta0_h") (CPTYPE V4HI))
+ "cpseta0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpseta0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 11100 cpsetua0.w crqp,crpp (p0_1)
+(dni cpsetua0_w_P0S "cpsetua0.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetua0_w") (CPTYPE V2SI))
+ "cpsetua0.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpsetua0_w" pc crqp crpp) )
+ ()
+ )
+
+; 11000 qqqqq ppppp 11101 cpsetla0.w crqp,crpp (p0_1)
+(dni cpsetla0_w_P0S "cpsetla0.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetla0_w") (CPTYPE V2SI))
+ "cpsetla0.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (c-call "ivc2_cpsetla0_w" pc crqp crpp) )
+ ()
+ )
+
+; 11001 00000 00001 ooooo cpmova0.b =crop (p0_1)
+(dni cpmova0_b_P0S "cpmova0.b $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmova0_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpmova0.b $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmova0_b" pc)) )
+ ()
+ )
+
+; 11001 00000 00010 ooooo cpmovua0.h =crop (p0_1)
+(dni cpmovua0_h_P0S "cpmovua0.h $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovua0_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpmovua0.h $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovua0_h" pc)) )
+ ()
+ )
+
+; 11001 00000 00011 ooooo cpmovla0.h =crop (p0_1)
+(dni cpmovla0_h_P0S "cpmovla0.h $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovla0_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpmovla0.h $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovla0_h" pc)) )
+ ()
+ )
+
+; 11001 00000 00100 ooooo cpmovuua0.w =crop (p0_1)
+(dni cpmovuua0_w_P0S "cpmovuua0.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovuua0_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovuua0.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovuua0_w" pc)) )
+ ()
+ )
+
+; 11001 00000 00101 ooooo cpmovula0.w =crop (p0_1)
+(dni cpmovula0_w_P0S "cpmovula0.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovula0_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovula0.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovula0_w" pc)) )
+ ()
+ )
+
+; 11001 00000 00110 ooooo cpmovlua0.w =crop (p0_1)
+(dni cpmovlua0_w_P0S "cpmovlua0.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovlua0_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovlua0.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovlua0_w" pc)) )
+ ()
+ )
+
+; 11001 00000 00111 ooooo cpmovlla0.w =crop (p0_1)
+(dni cpmovlla0_w_P0S "cpmovlla0.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovlla0_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovlla0.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovlla0_w" pc)) )
+ ()
+ )
+
+; 11001 00000 01000 ooooo cppacka0u.b =crop (p0_1)
+(dni cppacka0u_b_P0S "cppacka0u.b $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppacka0u_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cppacka0u.b $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppacka0u_b" pc)) )
+ ()
+ )
+
+; 11001 00000 01001 ooooo cppacka0.b =crop (p0_1)
+(dni cppacka0_b_P0S "cppacka0.b $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppacka0_b") (CPTYPE V8QI) (CRET FIRST))
+ "cppacka0.b $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppacka0_b" pc)) )
+ ()
+ )
+
+; 11001 00000 01010 ooooo cppackua0.h =crop (p0_1)
+(dni cppackua0_h_P0S "cppackua0.h $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackua0_h") (CPTYPE V4HI) (CRET FIRST))
+ "cppackua0.h $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppackua0_h" pc)) )
+ ()
+ )
+
+; 11001 00000 01011 ooooo cppackla0.h =crop (p0_1)
+(dni cppackla0_h_P0S "cppackla0.h $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackla0_h") (CPTYPE V4HI) (CRET FIRST))
+ "cppackla0.h $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppackla0_h" pc)) )
+ ()
+ )
+
+; 11001 00000 01100 ooooo cppackua0.w =crop (p0_1)
+(dni cppackua0_w_P0S "cppackua0.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackua0_w") (CPTYPE V2SI) (CRET FIRST))
+ "cppackua0.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xc) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppackua0_w" pc)) )
+ ()
+ )
+
+; 11001 00000 01101 ooooo cppackla0.w =crop (p0_1)
+(dni cppackla0_w_P0S "cppackla0.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackla0_w") (CPTYPE V2SI) (CRET FIRST))
+ "cppackla0.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppackla0_w" pc)) )
+ ()
+ )
+
+; 11001 00000 01110 ooooo cpmovhua0.w =crop (p0_1)
+(dni cpmovhua0_w_P0S "cpmovhua0.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovhua0_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovhua0.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovhua0_w" pc)) )
+ ()
+ )
+
+; 11001 00000 01111 ooooo cpmovhla0.w =crop (p0_1)
+(dni cpmovhla0_w_P0S "cpmovhla0.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovhla0_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovhla0.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovhla0_w" pc)) )
+ ()
+ )
+
+; 11001 00000 10000 00000 cpacsuma0 (p0_1)
+(dni cpacsuma0_P0S "cpacsuma0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpacsuma0"))
+ "cpacsuma0"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpacsuma0" pc) )
+ ()
+ )
+
+; 11001 00000 10001 00000 cpaccpa0 (p0_1)
+(dni cpaccpa0_P0S "cpaccpa0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaccpa0"))
+ "cpaccpa0"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpaccpa0" pc) )
+ ()
+ )
+
+; 11001 qqqqq 11000 00000 cpsrla0 crqp (p0_1)
+(dni cpsrla0_P0S "cpsrla0 $crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsrla0"))
+ "cpsrla0 $crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x18) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpsrla0" pc crqp) )
+ ()
+ )
+
+; 11001 qqqqq 11001 00000 cpsraa0 crqp (p0_1)
+(dni cpsraa0_P0S "cpsraa0 $crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsraa0"))
+ "cpsraa0 $crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x19) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpsraa0" pc crqp) )
+ ()
+ )
+
+; 11001 qqqqq 11010 00000 cpslla0 crqp (p0_1)
+(dni cpslla0_P0S "cpslla0 $crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpslla0"))
+ "cpslla0 $crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x1a) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpslla0" pc crqp) )
+ ()
+ )
+
+; 11001 00000 11100 iiiii cpsrlia0 imm5p23 (p0_1)
+(dni cpsrlia0_P0S "cpsrlia0 imm5p23 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsrlia0"))
+ "cpsrlia0 $imm5p23"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1c) imm5p23 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpsrlia0" pc imm5p23) )
+ ()
+ )
+
+; 11001 00000 11101 iiiii cpsraia0 imm5p23 (p0_1)
+(dni cpsraia0_P0S "cpsraia0 imm5p23 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsraia0"))
+ "cpsraia0 $imm5p23"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1d) imm5p23 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpsraia0" pc imm5p23) )
+ ()
+ )
+
+; 11001 00000 11110 iiiii cpsllia0 imm5p23 (p0_1)
+(dni cpsllia0_P0S "cpsllia0 imm5p23 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsllia0"))
+ "cpsllia0 $imm5p23"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1e) imm5p23 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpsllia0" pc imm5p23) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 00000 cpfsftba0s0u.b crqp,crpp (p0_1)
+(dni cpfsftba0s0u_b_P0S "cpfsftba0s0u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0u_b") (CPTYPE V8UQI))
+ "cpfsftba0s0u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpfsftba0s0u_b" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 00001 cpfsftba0s0.b crqp,crpp (p0_1)
+(dni cpfsftba0s0_b_P0S "cpfsftba0s0.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0_b") (CPTYPE V8QI))
+ "cpfsftba0s0.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpfsftba0s0_b" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 00010 cpfsftbua0s0.h crqp,crpp (p0_1)
+(dni cpfsftbua0s0_h_P0S "cpfsftbua0s0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s0_h") (CPTYPE V4HI))
+ "cpfsftbua0s0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpfsftbua0s0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 00011 cpfsftbla0s0.h crqp,crpp (p0_1)
+(dni cpfsftbla0s0_h_P0S "cpfsftbla0s0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s0_h") (CPTYPE V4HI))
+ "cpfsftbla0s0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (c-call "ivc2_cpfsftbla0s0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 00100 cpfaca0s0u.b crqp,crpp (p0_1)
+(dni cpfaca0s0u_b_P0S "cpfaca0s0u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0u_b") (CPTYPE V8UQI))
+ "cpfaca0s0u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpfaca0s0u_b" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 00101 cpfaca0s0.b crqp,crpp (p0_1)
+(dni cpfaca0s0_b_P0S "cpfaca0s0.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0_b") (CPTYPE V8QI))
+ "cpfaca0s0.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpfaca0s0_b" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 00110 cpfacua0s0.h crqp,crpp (p0_1)
+(dni cpfacua0s0_h_P0S "cpfacua0s0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s0_h") (CPTYPE V4HI))
+ "cpfacua0s0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpfacua0s0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 00111 cpfacla0s0.h crqp,crpp (p0_1)
+(dni cpfacla0s0_h_P0S "cpfacla0s0.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s0_h") (CPTYPE V4HI))
+ "cpfacla0s0.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpfacla0s0_h" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 01000 cpfsftba0s1u.b crqp,crpp (p0_1)
+(dni cpfsftba0s1u_b_P0S "cpfsftba0s1u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1u_b") (CPTYPE V8UQI))
+ "cpfsftba0s1u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpfsftba0s1u_b" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 01001 cpfsftba0s1.b crqp,crpp (p0_1)
+(dni cpfsftba0s1_b_P0S "cpfsftba0s1.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1_b") (CPTYPE V8QI))
+ "cpfsftba0s1.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpfsftba0s1_b" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 01010 cpfsftbua0s1.h crqp,crpp (p0_1)
+(dni cpfsftbua0s1_h_P0S "cpfsftbua0s1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s1_h") (CPTYPE V4HI))
+ "cpfsftbua0s1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (c-call "ivc2_cpfsftbua0s1_h" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 01011 cpfsftbla0s1.h crqp,crpp (p0_1)
+(dni cpfsftbla0s1_h_P0S "cpfsftbla0s1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s1_h") (CPTYPE V4HI))
+ "cpfsftbla0s1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (c-call "ivc2_cpfsftbla0s1_h" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 01100 cpfaca0s1u.b crqp,crpp (p0_1)
+(dni cpfaca0s1u_b_P0S "cpfaca0s1u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1u_b") (CPTYPE V8UQI))
+ "cpfaca0s1u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpfaca0s1u_b" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 01101 cpfaca0s1.b crqp,crpp (p0_1)
+(dni cpfaca0s1_b_P0S "cpfaca0s1.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1_b") (CPTYPE V8QI))
+ "cpfaca0s1.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpfaca0s1_b" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 01110 cpfacua0s1.h crqp,crpp (p0_1)
+(dni cpfacua0s1_h_P0S "cpfacua0s1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s1_h") (CPTYPE V4HI))
+ "cpfacua0s1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpfacua0s1_h" pc crqp crpp) )
+ ()
+ )
+
+; 11111 qqqqq ppppp 01111 cpfacla0s1.h crqp,crpp (p0_1)
+(dni cpfacla0s1_h_P0S "cpfacla0s1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s1_h") (CPTYPE V4HI))
+ "cpfacla0s1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_cofa0 0)
+ (c-call "ivc2_cpfacla0s1_h" pc crqp crpp) )
+ ()
+ )
+
+; xxxxxiii 01000 qqqqq ppppp ooooo cpfsftbi =crop,crqp,crpp,imm3p5 (p0_1)
+(dni cpfsftbi_P0_P1 "cpfsftbi $crop,$crqp,$crpp,imm3p5 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpfsftbi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cpfsftbi $crop,$crqp,$crpp,$imm3p5"
+ (+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x8) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpfsftbi" pc crqp crpp imm3p5)) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 00001 cpacmpeq.b crqp,crpp (p0_1)
+(dni cpacmpeq_b_P0_P1 "cpacmpeq.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_b") (CPTYPE V8QI))
+ "cpacmpeq.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpeq_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 00011 cpacmpeq.h crqp,crpp (p0_1)
+(dni cpacmpeq_h_P0_P1 "cpacmpeq.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_h") (CPTYPE V4HI))
+ "cpacmpeq.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpeq_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 00101 cpacmpeq.w crqp,crpp (p0_1)
+(dni cpacmpeq_w_P0_P1 "cpacmpeq.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_w") (CPTYPE V2SI))
+ "cpacmpeq.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpeq_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 01001 cpacmpne.b crqp,crpp (p0_1)
+(dni cpacmpne_b_P0_P1 "cpacmpne.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_b") (CPTYPE V8QI))
+ "cpacmpne.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpne_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 01011 cpacmpne.h crqp,crpp (p0_1)
+(dni cpacmpne_h_P0_P1 "cpacmpne.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_h") (CPTYPE V4HI))
+ "cpacmpne.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpne_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 01101 cpacmpne.w crqp,crpp (p0_1)
+(dni cpacmpne_w_P0_P1 "cpacmpne.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_w") (CPTYPE V2SI))
+ "cpacmpne.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpne_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 10000 cpacmpgtu.b crqp,crpp (p0_1)
+(dni cpacmpgtu_b_P0_P1 "cpacmpgtu.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgtu_b") (CPTYPE V8UQI))
+ "cpacmpgtu.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpgtu_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 10001 cpacmpgt.b crqp,crpp (p0_1)
+(dni cpacmpgt_b_P0_P1 "cpacmpgt.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_b") (CPTYPE V8QI))
+ "cpacmpgt.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpgt_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 10011 cpacmpgt.h crqp,crpp (p0_1)
+(dni cpacmpgt_h_P0_P1 "cpacmpgt.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_h") (CPTYPE V4HI))
+ "cpacmpgt.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpgt_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 10100 cpacmpgtu.w crqp,crpp (p0_1)
+(dni cpacmpgtu_w_P0_P1 "cpacmpgtu.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgtu_w") (CPTYPE V2USI))
+ "cpacmpgtu.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpgtu_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 10101 cpacmpgt.w crqp,crpp (p0_1)
+(dni cpacmpgt_w_P0_P1 "cpacmpgt.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_w") (CPTYPE V2SI))
+ "cpacmpgt.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpgt_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 11000 cpacmpgeu.b crqp,crpp (p0_1)
+(dni cpacmpgeu_b_P0_P1 "cpacmpgeu.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgeu_b") (CPTYPE V8UQI))
+ "cpacmpgeu.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpgeu_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 11001 cpacmpge.b crqp,crpp (p0_1)
+(dni cpacmpge_b_P0_P1 "cpacmpge.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_b") (CPTYPE V8QI))
+ "cpacmpge.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpge_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 11011 cpacmpge.h crqp,crpp (p0_1)
+(dni cpacmpge_h_P0_P1 "cpacmpge.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_h") (CPTYPE V4HI))
+ "cpacmpge.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpge_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 11100 cpacmpgeu.w crqp,crpp (p0_1)
+(dni cpacmpgeu_w_P0_P1 "cpacmpgeu.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgeu_w") (CPTYPE V2USI))
+ "cpacmpgeu.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpgeu_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 10011 qqqqq ppppp 11101 cpacmpge.w crqp,crpp (p0_1)
+(dni cpacmpge_w_P0_P1 "cpacmpge.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_w") (CPTYPE V2SI))
+ "cpacmpge.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpacmpge_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 00001 cpocmpeq.b crqp,crpp (p0_1)
+(dni cpocmpeq_b_P0_P1 "cpocmpeq.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_b") (CPTYPE V8QI))
+ "cpocmpeq.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpeq_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 00011 cpocmpeq.h crqp,crpp (p0_1)
+(dni cpocmpeq_h_P0_P1 "cpocmpeq.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_h") (CPTYPE V4HI))
+ "cpocmpeq.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpeq_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 00101 cpocmpeq.w crqp,crpp (p0_1)
+(dni cpocmpeq_w_P0_P1 "cpocmpeq.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_w") (CPTYPE V2SI))
+ "cpocmpeq.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpeq_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 01001 cpocmpne.b crqp,crpp (p0_1)
+(dni cpocmpne_b_P0_P1 "cpocmpne.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_b") (CPTYPE V8QI))
+ "cpocmpne.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpne_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 01011 cpocmpne.h crqp,crpp (p0_1)
+(dni cpocmpne_h_P0_P1 "cpocmpne.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_h") (CPTYPE V4HI))
+ "cpocmpne.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpne_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 01101 cpocmpne.w crqp,crpp (p0_1)
+(dni cpocmpne_w_P0_P1 "cpocmpne.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_w") (CPTYPE V2SI))
+ "cpocmpne.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpne_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 10000 cpocmpgtu.b crqp,crpp (p0_1)
+(dni cpocmpgtu_b_P0_P1 "cpocmpgtu.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgtu_b") (CPTYPE V8UQI))
+ "cpocmpgtu.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpgtu_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 10001 cpocmpgt.b crqp,crpp (p0_1)
+(dni cpocmpgt_b_P0_P1 "cpocmpgt.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_b") (CPTYPE V8QI))
+ "cpocmpgt.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpgt_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 10011 cpocmpgt.h crqp,crpp (p0_1)
+(dni cpocmpgt_h_P0_P1 "cpocmpgt.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_h") (CPTYPE V4HI))
+ "cpocmpgt.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpgt_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 10100 cpocmpgtu.w crqp,crpp (p0_1)
+(dni cpocmpgtu_w_P0_P1 "cpocmpgtu.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgtu_w") (CPTYPE V2USI))
+ "cpocmpgtu.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpgtu_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 10101 cpocmpgt.w crqp,crpp (p0_1)
+(dni cpocmpgt_w_P0_P1 "cpocmpgt.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_w") (CPTYPE V2SI))
+ "cpocmpgt.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpgt_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 11000 cpocmpgeu.b crqp,crpp (p0_1)
+(dni cpocmpgeu_b_P0_P1 "cpocmpgeu.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgeu_b") (CPTYPE V8UQI))
+ "cpocmpgeu.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpgeu_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 11001 cpocmpge.b crqp,crpp (p0_1)
+(dni cpocmpge_b_P0_P1 "cpocmpge.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_b") (CPTYPE V8QI))
+ "cpocmpge.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpge_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 11011 cpocmpge.h crqp,crpp (p0_1)
+(dni cpocmpge_h_P0_P1 "cpocmpge.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_h") (CPTYPE V4HI))
+ "cpocmpge.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpge_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 11100 cpocmpgeu.w crqp,crpp (p0_1)
+(dni cpocmpgeu_w_P0_P1 "cpocmpgeu.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgeu_w") (CPTYPE V2USI))
+ "cpocmpgeu.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpgeu_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 10011 qqqqq ppppp 11101 cpocmpge.w crqp,crpp (p0_1)
+(dni cpocmpge_w_P0_P1 "cpocmpge.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_w") (CPTYPE V2SI))
+ "cpocmpge.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_cpocmpge_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000011 10100 qqqqq ppppp ooooo cdadd3 =crop,crqp,crpp (p0_1)
+(dni cdadd3_P0_P1 "cdadd3 $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdadd3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdadd3 $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cdadd3" pc crqp crpp)) )
+ ()
+ )
+
+; 00000100 10100 qqqqq ppppp ooooo cpsub3.b =crop,crqp,crpp (p0_1)
+(dni cpsub3_b_P0_P1 "cpsub3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpsub3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x4) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsub3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00000101 10100 qqqqq ppppp ooooo cpsub3.h =crop,crqp,crpp (p0_1)
+(dni cpsub3_h_P0_P1 "cpsub3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsub3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x5) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsub3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 00000110 10100 qqqqq ppppp ooooo cpsub3.w =crop,crqp,crpp (p0_1)
+(dni cpsub3_w_P0_P1 "cpsub3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsub3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x6) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsub3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 00000111 10100 qqqqq ppppp ooooo cdsub3 =crop,crqp,crpp (p0_1)
+(dni cdsub3_P0_P1 "cdsub3 $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsub3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdsub3 $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x7) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cdsub3" pc crqp crpp)) )
+ ()
+ )
+
+; 00001010 10100 qqqqq ppppp ooooo cpsadd3.h =crop,crqp,crpp (p0_1)
+(dni cpsadd3_h_P0_P1 "cpsadd3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsadd3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsadd3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #xa) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsadd3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 00001011 10100 qqqqq ppppp ooooo cpsadd3.w =crop,crqp,crpp (p0_1)
+(dni cpsadd3_w_P0_P1 "cpsadd3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsadd3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsadd3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #xb) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsadd3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 00001110 10100 qqqqq ppppp ooooo cpssub3.h =crop,crqp,crpp (p0_1)
+(dni cpssub3_h_P0_P1 "cpssub3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssub3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpssub3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #xe) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cofr0 0)
+ (set crop (c-call DI "ivc2_cpssub3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 00001111 10100 qqqqq ppppp ooooo cpssub3.w =crop,crqp,crpp (p0_1)
+(dni cpssub3_w_P0_P1 "cpssub3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssub3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpssub3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #xf) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_cofr0 0)
+ (set crop (c-call DI "ivc2_cpssub3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 00010000 10100 qqqqq ppppp ooooo cpextuaddu3.b =crop,crqp,crpp (p0_1)
+(dni cpextuaddu3_b_P0_P1 "cpextuaddu3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextuaddu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextuaddu3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x10) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextuaddu3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00010001 10100 qqqqq ppppp ooooo cpextuadd3.b =crop,crqp,crpp (p0_1)
+(dni cpextuadd3_b_P0_P1 "cpextuadd3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextuadd3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextuadd3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x11) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextuadd3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00010010 10100 qqqqq ppppp ooooo cpextladdu3.b =crop,crqp,crpp (p0_1)
+(dni cpextladdu3_b_P0_P1 "cpextladdu3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextladdu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextladdu3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x12) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextladdu3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00010011 10100 qqqqq ppppp ooooo cpextladd3.b =crop,crqp,crpp (p0_1)
+(dni cpextladd3_b_P0_P1 "cpextladd3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextladd3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextladd3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x13) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextladd3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00010100 10100 qqqqq ppppp ooooo cpextusubu3.b =crop,crqp,crpp (p0_1)
+(dni cpextusubu3_b_P0_P1 "cpextusubu3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextusubu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextusubu3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x14) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextusubu3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00010101 10100 qqqqq ppppp ooooo cpextusub3.b =crop,crqp,crpp (p0_1)
+(dni cpextusub3_b_P0_P1 "cpextusub3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextusub3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextusub3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x15) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextusub3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00010110 10100 qqqqq ppppp ooooo cpextlsubu3.b =crop,crqp,crpp (p0_1)
+(dni cpextlsubu3_b_P0_P1 "cpextlsubu3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextlsubu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextlsubu3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x16) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextlsubu3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00010111 10100 qqqqq ppppp ooooo cpextlsub3.b =crop,crqp,crpp (p0_1)
+(dni cpextlsub3_b_P0_P1 "cpextlsub3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextlsub3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpextlsub3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x17) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpextlsub3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00011000 10100 qqqqq ppppp ooooo cpaveu3.b =crop,crqp,crpp (p0_1)
+(dni cpaveu3_b_P0_P1 "cpaveu3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaveu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpaveu3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x18) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpaveu3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00011001 10100 qqqqq ppppp ooooo cpave3.b =crop,crqp,crpp (p0_1)
+(dni cpave3_b_P0_P1 "cpave3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpave3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x19) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpave3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00011010 10100 qqqqq ppppp ooooo cpave3.h =crop,crqp,crpp (p0_1)
+(dni cpave3_h_P0_P1 "cpave3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpave3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1a) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpave3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 00011011 10100 qqqqq ppppp ooooo cpave3.w =crop,crqp,crpp (p0_1)
+(dni cpave3_w_P0_P1 "cpave3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpave3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1b) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpave3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 00011100 10100 qqqqq ppppp ooooo cpaddsru3.b =crop,crqp,crpp (p0_1)
+(dni cpaddsru3_b_P0_P1 "cpaddsru3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsru3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpaddsru3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpaddsru3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00011101 10100 qqqqq ppppp ooooo cpaddsr3.b =crop,crqp,crpp (p0_1)
+(dni cpaddsr3_b_P0_P1 "cpaddsr3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpaddsr3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpaddsr3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00011110 10100 qqqqq ppppp ooooo cpaddsr3.h =crop,crqp,crpp (p0_1)
+(dni cpaddsr3_h_P0_P1 "cpaddsr3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpaddsr3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1e) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpaddsr3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 00011111 10100 qqqqq ppppp ooooo cpaddsr3.w =crop,crqp,crpp (p0_1)
+(dni cpaddsr3_w_P0_P1 "cpaddsr3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpaddsr3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1f) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpaddsr3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 00100000 10100 qqqqq ppppp ooooo cpabsu3.b =crop,crqp,crpp (p0_1)
+(dni cpabsu3_b_P0_P1 "cpabsu3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabsu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpabsu3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x20) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpabsu3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00100001 10100 qqqqq ppppp ooooo cpabs3.b =crop,crqp,crpp (p0_1)
+(dni cpabs3_b_P0_P1 "cpabs3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabs3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpabs3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x21) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpabs3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00100010 10100 qqqqq ppppp ooooo cpabs3.h =crop,crqp,crpp (p0_1)
+(dni cpabs3_h_P0_P1 "cpabs3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabs3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpabs3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x22) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpabs3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 00100100 10100 qqqqq ppppp ooooo cpand3 =crop,crqp,crpp (p0_1)
+(dni cpand3_P0_P1 "cpand3 $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpand3") (CPTYPE VECT) (CRET FIRST))
+ "cpand3 $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x24) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpand3" pc crqp crpp)) )
+ ()
+ )
+
+; 00100101 10100 qqqqq ppppp ooooo cpor3 =crop,crqp,crpp (p0_1)
+(dni cpor3_P0_P1 "cpor3 $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpor3") (CPTYPE VECT) (CRET FIRST))
+ "cpor3 $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x25) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpor3" pc crqp crpp)) )
+ ()
+ )
+
+; 00100110 10100 qqqqq ppppp ooooo cpnor3 =crop,crqp,crpp (p0_1)
+(dni cpnor3_P0_P1 "cpnor3 $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpnor3") (CPTYPE VECT) (CRET FIRST))
+ "cpnor3 $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x26) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpnor3" pc crqp crpp)) )
+ ()
+ )
+
+; 00100111 10100 qqqqq ppppp ooooo cpxor3 =crop,crqp,crpp (p0_1)
+(dni cpxor3_P0_P1 "cpxor3 $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpxor3") (CPTYPE VECT) (CRET FIRST))
+ "cpxor3 $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x27) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpxor3" pc crqp crpp)) )
+ ()
+ )
+
+; 00101100 10100 qqqqq ppppp ooooo cppacku.b =crop,crqp,crpp (p0_1)
+(dni cppacku_b_P0_P1 "cppacku.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppacku_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cppacku.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x2c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppacku_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00101101 10100 qqqqq ppppp ooooo cppack.b =crop,crqp,crpp (p0_1)
+(dni cppack_b_P0_P1 "cppack.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppack_b") (CPTYPE V8QI) (CRET FIRST))
+ "cppack.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x2d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppack_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00101111 10100 qqqqq ppppp ooooo cppack.h =crop,crqp,crpp (p0_1)
+(dni cppack_h_P0_P1 "cppack.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppack_h") (CPTYPE V4HI) (CRET FIRST))
+ "cppack.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x2f) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppack_h" pc crqp crpp)) )
+ ()
+ )
+
+; 00110000 10100 qqqqq ppppp ooooo cpmaxu3.b =crop,crqp,crpp (p0_1)
+(dni cpmaxu3_b_P0_P1 "cpmaxu3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmaxu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpmaxu3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x30) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmaxu3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00110001 10100 qqqqq ppppp ooooo cpmax3.b =crop,crqp,crpp (p0_1)
+(dni cpmax3_b_P0_P1 "cpmax3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpmax3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x31) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmax3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00110011 10100 qqqqq ppppp ooooo cpmax3.h =crop,crqp,crpp (p0_1)
+(dni cpmax3_h_P0_P1 "cpmax3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpmax3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x33) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmax3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 00110100 10100 qqqqq ppppp ooooo cpmaxu3.w =crop,crqp,crpp (p0_1)
+(dni cpmaxu3_w_P0_P1 "cpmaxu3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmaxu3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmaxu3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x34) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmaxu3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 00110101 10100 qqqqq ppppp ooooo cpmax3.w =crop,crqp,crpp (p0_1)
+(dni cpmax3_w_P0_P1 "cpmax3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmax3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x35) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmax3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 00111000 10100 qqqqq ppppp ooooo cpminu3.b =crop,crqp,crpp (p0_1)
+(dni cpminu3_b_P0_P1 "cpminu3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpminu3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpminu3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x38) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpminu3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00111001 10100 qqqqq ppppp ooooo cpmin3.b =crop,crqp,crpp (p0_1)
+(dni cpmin3_b_P0_P1 "cpmin3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpmin3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x39) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmin3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 00111011 10100 qqqqq ppppp ooooo cpmin3.h =crop,crqp,crpp (p0_1)
+(dni cpmin3_h_P0_P1 "cpmin3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpmin3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x3b) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmin3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 00111100 10100 qqqqq ppppp ooooo cpminu3.w =crop,crqp,crpp (p0_1)
+(dni cpminu3_w_P0_P1 "cpminu3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpminu3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpminu3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x3c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpminu3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 00111101 10100 qqqqq ppppp ooooo cpmin3.w =crop,crqp,crpp (p0_1)
+(dni cpmin3_w_P0_P1 "cpmin3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmin3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x3d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmin3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 01000000 10100 qqqqq ppppp ooooo cpsrl3.b =crop,crqp,crpp (p0_1)
+(dni cpsrl3_b_P0_P1 "cpsrl3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpsrl3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x40) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsrl3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 01000001 10100 qqqqq ppppp ooooo cpssrl3.b =crop,crqp,crpp (p0_1)
+(dni cpssrl3_b_P0_P1 "cpssrl3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpssrl3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x41) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpssrl3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 01000010 10100 qqqqq ppppp ooooo cpsrl3.h =crop,crqp,crpp (p0_1)
+(dni cpsrl3_h_P0_P1 "cpsrl3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsrl3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x42) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsrl3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 01000011 10100 qqqqq ppppp ooooo cpssrl3.h =crop,crqp,crpp (p0_1)
+(dni cpssrl3_h_P0_P1 "cpssrl3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpssrl3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x43) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpssrl3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 01000100 10100 qqqqq ppppp ooooo cpsrl3.w =crop,crqp,crpp (p0_1)
+(dni cpsrl3_w_P0_P1 "cpsrl3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsrl3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x44) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsrl3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 01000101 10100 qqqqq ppppp ooooo cpssrl3.w =crop,crqp,crpp (p0_1)
+(dni cpssrl3_w_P0_P1 "cpssrl3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpssrl3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x45) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpssrl3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 01000110 10100 qqqqq ppppp ooooo cdsrl3 =crop,crqp,crpp (p0_1)
+(dni cdsrl3_P0_P1 "cdsrl3 $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrl3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdsrl3 $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x46) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cdsrl3" pc crqp crpp)) )
+ ()
+ )
+
+; 01001000 10100 qqqqq ppppp ooooo cpsra3.b =crop,crqp,crpp (p0_1)
+(dni cpsra3_b_P0_P1 "cpsra3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpsra3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x48) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsra3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 01001001 10100 qqqqq ppppp ooooo cpssra3.b =crop,crqp,crpp (p0_1)
+(dni cpssra3_b_P0_P1 "cpssra3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpssra3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x49) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpssra3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 01001010 10100 qqqqq ppppp ooooo cpsra3.h =crop,crqp,crpp (p0_1)
+(dni cpsra3_h_P0_P1 "cpsra3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsra3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x4a) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsra3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 01001011 10100 qqqqq ppppp ooooo cpssra3.h =crop,crqp,crpp (p0_1)
+(dni cpssra3_h_P0_P1 "cpssra3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpssra3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x4b) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpssra3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 01001100 10100 qqqqq ppppp ooooo cpsra3.w =crop,crqp,crpp (p0_1)
+(dni cpsra3_w_P0_P1 "cpsra3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsra3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x4c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsra3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 01001101 10100 qqqqq ppppp ooooo cpssra3.w =crop,crqp,crpp (p0_1)
+(dni cpssra3_w_P0_P1 "cpssra3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpssra3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x4d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpssra3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 01001110 10100 qqqqq ppppp ooooo cdsra3 =crop,crqp,crpp (p0_1)
+(dni cdsra3_P0_P1 "cdsra3 $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsra3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdsra3 $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x4e) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cdsra3" pc crqp crpp)) )
+ ()
+ )
+
+; 01010000 10100 qqqqq ppppp ooooo cpsll3.b =crop,crqp,crpp (p0_1)
+(dni cpsll3_b_P0_P1 "cpsll3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpsll3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x50) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsll3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 01010001 10100 qqqqq ppppp ooooo cpssll3.b =crop,crqp,crpp (p0_1)
+(dni cpssll3_b_P0_P1 "cpssll3.b $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpssll3.b $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x51) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpssll3_b" pc crqp crpp)) )
+ ()
+ )
+
+; 01010010 10100 qqqqq ppppp ooooo cpsll3.h =crop,crqp,crpp (p0_1)
+(dni cpsll3_h_P0_P1 "cpsll3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsll3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x52) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsll3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 01010011 10100 qqqqq ppppp ooooo cpssll3.h =crop,crqp,crpp (p0_1)
+(dni cpssll3_h_P0_P1 "cpssll3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpssll3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x53) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpssll3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 01010100 10100 qqqqq ppppp ooooo cpsll3.w =crop,crqp,crpp (p0_1)
+(dni cpsll3_w_P0_P1 "cpsll3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsll3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x54) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsll3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 01010101 10100 qqqqq ppppp ooooo cpssll3.w =crop,crqp,crpp (p0_1)
+(dni cpssll3_w_P0_P1 "cpssll3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpssll3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x55) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpssll3_w" pc crqp crpp)) )
+ ()
+ )
+
+; 01010110 10100 qqqqq ppppp ooooo cdsll3 =crop,crqp,crpp (p0_1)
+(dni cdsll3_P0_P1 "cdsll3 $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsll3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdsll3 $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x56) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cdsll3" pc crqp crpp)) )
+ ()
+ )
+
+; 01011010 10100 qqqqq ppppp ooooo cpsla3.h =crop,crqp,crpp (p0_1)
+(dni cpsla3_h_P0_P1 "cpsla3.h $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsla3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsla3.h $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x5a) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsla3_h" pc crqp crpp)) )
+ ()
+ )
+
+; 01011100 10100 qqqqq ppppp ooooo cpsla3.w =crop,crqp,crpp (p0_1)
+(dni cpsla3_w_P0_P1 "cpsla3.w $crop,$crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsla3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsla3.w $crop,$crqp,$crpp"
+ (+ (f-ivc2-8u0 #x5c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsla3_w" pc crqp crpp)) )
+ ()
+ )
+
+; xxxxxiii 10101 qqqqq 00000 ooooo cpsrli3.b =crop,crqp,imm3p5 (p0_1)
+(dni cpsrli3_b_P0_P1 "cpsrli3.b $crop,$crqp,imm3p5 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpsrli3.b $crop,$crqp,$imm3p5"
+ (+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x0) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsrli3_b" pc crqp imm3p5)) )
+ ()
+ )
+
+; xxxxiiii 10101 qqqqq 00001 ooooo cpsrli3.h =crop,crqp,imm4p4 (p0_1)
+(dni cpsrli3_h_P0_P1 "cpsrli3.h $crop,$crqp,imm4p4 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsrli3.h $crop,$crqp,$imm4p4"
+ (+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsrli3_h" pc crqp imm4p4)) )
+ ()
+ )
+
+; xxxiiiii 10101 qqqqq 00010 ooooo cpsrli3.w =crop,crqp,imm5p3 (p0_1)
+(dni cpsrli3_w_P0_P1 "cpsrli3.w $crop,$crqp,imm5p3 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsrli3.w $crop,$crqp,$imm5p3"
+ (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsrli3_w" pc crqp imm5p3)) )
+ ()
+ )
+
+; xxiiiiii 10101 qqqqq 00011 ooooo cdsrli3 =crop,crqp,imm6p2 (p0_1)
+(dni cdsrli3_P0_P1 "cdsrli3 $crop,$crqp,imm6p2 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdsrli3 $crop,$crqp,$imm6p2"
+ (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cdsrli3" pc crqp imm6p2)) )
+ ()
+ )
+
+; xxxxxiii 10101 qqqqq 00100 ooooo cpsrai3.b =crop,crqp,imm3p5 (p0_1)
+(dni cpsrai3_b_P0_P1 "cpsrai3.b $crop,$crqp,imm3p5 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpsrai3.b $crop,$crqp,$imm3p5"
+ (+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsrai3_b" pc crqp imm3p5)) )
+ ()
+ )
+
+; xxxxiiii 10101 qqqqq 00101 ooooo cpsrai3.h =crop,crqp,imm4p4 (p0_1)
+(dni cpsrai3_h_P0_P1 "cpsrai3.h $crop,$crqp,imm4p4 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpsrai3.h $crop,$crqp,$imm4p4"
+ (+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsrai3_h" pc crqp imm4p4)) )
+ ()
+ )
+
+; xxxiiiii 10101 qqqqq 00110 ooooo cpsrai3.w =crop,crqp,imm5p3 (p0_1)
+(dni cpsrai3_w_P0_P1 "cpsrai3.w $crop,$crqp,imm5p3 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpsrai3.w $crop,$crqp,$imm5p3"
+ (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpsrai3_w" pc crqp imm5p3)) )
+ ()
+ )
+
+; xxiiiiii 10101 qqqqq 00111 ooooo cdsrai3 =crop,crqp,imm6p2 (p0_1)
+(dni cdsrai3_P0_P1 "cdsrai3 $crop,$crqp,imm6p2 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrai3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdsrai3 $crop,$crqp,$imm6p2"
+ (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cdsrai3" pc crqp imm6p2)) )
+ ()
+ )
+
+; xxxxxiii 10101 qqqqq 01000 ooooo cpslli3.b =crop,crqp,imm3p5 (p0_1)
+(dni cpslli3_b_P0_P1 "cpslli3.b $crop,$crqp,imm3p5 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpslli3.b $crop,$crqp,$imm3p5"
+ (+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpslli3_b" pc crqp imm3p5)) )
+ ()
+ )
+
+; xxxxiiii 10101 qqqqq 01001 ooooo cpslli3.h =crop,crqp,imm4p4 (p0_1)
+(dni cpslli3_h_P0_P1 "cpslli3.h $crop,$crqp,imm4p4 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpslli3.h $crop,$crqp,$imm4p4"
+ (+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpslli3_h" pc crqp imm4p4)) )
+ ()
+ )
+
+; xxxiiiii 10101 qqqqq 01010 ooooo cpslli3.w =crop,crqp,imm5p3 (p0_1)
+(dni cpslli3_w_P0_P1 "cpslli3.w $crop,$crqp,imm5p3 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpslli3.w $crop,$crqp,$imm5p3"
+ (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpslli3_w" pc crqp imm5p3)) )
+ ()
+ )
+
+; xxiiiiii 10101 qqqqq 01011 ooooo cdslli3 =crop,crqp,imm6p2 (p0_1)
+(dni cdslli3_P0_P1 "cdslli3 $crop,$crqp,imm6p2 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdslli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdslli3 $crop,$crqp,$imm6p2"
+ (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cdslli3" pc crqp imm6p2)) )
+ ()
+ )
+
+; xxxxiiii 10101 qqqqq 01101 ooooo cpslai3.h =crop,crqp,imm4p4 (p0_1)
+(dni cpslai3_h_P0_P1 "cpslai3.h $crop,$crqp,imm4p4 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslai3_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpslai3.h $crop,$crqp,$imm4p4"
+ (+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpslai3_h" pc crqp imm4p4)) )
+ ()
+ )
+
+; xxxiiiii 10101 qqqqq 01110 ooooo cpslai3.w =crop,crqp,imm5p3 (p0_1)
+(dni cpslai3_w_P0_P1 "cpslai3.w $crop,$crqp,imm5p3 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslai3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpslai3.w $crop,$crqp,$imm5p3"
+ (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpslai3_w" pc crqp imm5p3)) )
+ ()
+ )
+
+; xxxiiiii 10101 qqqqq 10000 ooooo cpclipiu3.w =crop,crqp,imm5p3 (p0_1)
+(dni cpclipiu3_w_P0_P1 "cpclipiu3.w $crop,$crqp,imm5p3 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpclipiu3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpclipiu3.w $crop,$crqp,$imm5p3"
+ (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x10) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpclipiu3_w" pc crqp imm5p3)) )
+ ()
+ )
+
+; xxxiiiii 10101 qqqqq 10001 ooooo cpclipi3.w =crop,crqp,imm5p3 (p0_1)
+(dni cpclipi3_w_P0_P1 "cpclipi3.w $crop,$crqp,imm5p3 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpclipi3_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpclipi3.w $crop,$crqp,$imm5p3"
+ (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x11) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpclipi3_w" pc crqp imm5p3)) )
+ ()
+ )
+
+; xxiiiiii 10101 qqqqq 10010 ooooo cdclipiu3 =crop,crqp,imm6p2 (p0_1)
+(dni cdclipiu3_P0_P1 "cdclipiu3 $crop,$crqp,imm6p2 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdclipiu3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdclipiu3 $crop,$crqp,$imm6p2"
+ (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x12) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cdclipiu3" pc crqp imm6p2)) )
+ ()
+ )
+
+; xxiiiiii 10101 qqqqq 10011 ooooo cdclipi3 =crop,crqp,imm6p2 (p0_1)
+(dni cdclipi3_P0_P1 "cdclipi3 $crop,$crqp,imm6p2 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdclipi3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdclipi3 $crop,$crqp,$imm6p2"
+ (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x13) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cdclipi3" pc crqp imm6p2)) )
+ ()
+ )
+
+; iiiiiiii 10110 qqqqq 01iii iiiii cpmovi.h =crqp,simm16p0 (p0_i)
+(dni cpmovi_h_P0_P1 "cpmovi.h $crqp,simm16p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmovi_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpmovi.h $crqp,$simm16p0"
+ (+ (f-ivc2-5u8 #x16) crqp (f-ivc2-2u18 #x1) simm16p0(f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqp (c-call DI "ivc2_cpmovi_h16" pc simm16p0)) )
+ ()
+ )
+
+; iiiiiiii 10111 qqqqq 00iii iiiii cpmoviu.w =crqp,imm16p0 (p0_i)
+(dni cpmoviu_w_P0_P1 "cpmoviu.w $crqp,imm16p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmoviu_w") (CPTYPE V2USI) (CRET FIRST))
+ "cpmoviu.w $crqp,$imm16p0"
+ (+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x0) imm16p0(f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqp (c-call DI "ivc2_cpmoviu_w16" pc imm16p0)) )
+ ()
+ )
+
+; iiiiiiii 10111 qqqqq 01iii iiiii cpmovi.w =crqp,simm16p0 (p0_i)
+(dni cpmovi_w_P0_P1 "cpmovi.w $crqp,simm16p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmovi_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovi.w $crqp,$simm16p0"
+ (+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x1) simm16p0(f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqp (c-call DI "ivc2_cpmovi_w16" pc simm16p0)) )
+ ()
+ )
+
+; iiiiiiii 10111 qqqqq 10iii iiiii cdmoviu =crqp,imm16p0 (p0_i)
+(dni cdmoviu_P0_P1 "cdmoviu $crqp,imm16p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdmoviu") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdmoviu $crqp,$imm16p0"
+ (+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x2) imm16p0(f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqp (c-call DI "ivc2_cdmoviu16" pc imm16p0)) )
+ ()
+ )
+
+; iiiiiiii 10111 qqqqq 11iii iiiii cdmovi =crqp,simm16p0 (p0_i)
+(dni cdmovi_P0_P1 "cdmovi $crqp,simm16p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdmovi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
+ "cdmovi $crqp,$simm16p0"
+ (+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x3) simm16p0(f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqp (c-call DI "ivc2_cdmovi16" pc simm16p0)) )
+ ()
+ )
+
+; 00000000 00000 00000 00000 00000 c1nop (p0_1)
+(dni c1nop_P1 "c1nop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "c1nop"))
+ "c1nop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x0) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x0) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call "ivc2_c1nop" pc) )
+ ()
+ )
+
+; 00000000 10110 qqqqq 00iii iiiii cpmovi.b =crqp,simm8p20 (p0_i)
+(dni cpmovi_b_P0S_P1 "cpmovi.b $crqp,simm8p20 Pn"
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovi_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpmovi.b $crqp,$simm8p20"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x16) crqp (f-ivc2-2u18 #x0) imm8p20(f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crqp (c-call DI "ivc2_cpmovi_b" pc simm8p20)) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 00000 cpadda1u.b crqp,crpp (p0_1)
+(dni cpadda1u_b_P1 "cpadda1u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1u_b") (CPTYPE V8UQI))
+ "cpadda1u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpadda1u_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 00001 cpadda1.b crqp,crpp (p0_1)
+(dni cpadda1_b_P1 "cpadda1.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1_b") (CPTYPE V8QI))
+ "cpadda1.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpadda1_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 00010 cpaddua1.h crqp,crpp (p0_1)
+(dni cpaddua1_h_P1 "cpaddua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddua1_h") (CPTYPE V4HI))
+ "cpaddua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpaddua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 00011 cpaddla1.h crqp,crpp (p0_1)
+(dni cpaddla1_h_P1 "cpaddla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddla1_h") (CPTYPE V4HI))
+ "cpaddla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpaddla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 00100 cpaddaca1u.b crqp,crpp (p0_1)
+(dni cpaddaca1u_b_P1 "cpaddaca1u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1u_b") (CPTYPE V8UQI))
+ "cpaddaca1u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpaddaca1u_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 00101 cpaddaca1.b crqp,crpp (p0_1)
+(dni cpaddaca1_b_P1 "cpaddaca1.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1_b") (CPTYPE V8QI))
+ "cpaddaca1.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpaddaca1_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 00110 cpaddacua1.h crqp,crpp (p0_1)
+(dni cpaddacua1_h_P1 "cpaddacua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacua1_h") (CPTYPE V4HI))
+ "cpaddacua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpaddacua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 00111 cpaddacla1.h crqp,crpp (p0_1)
+(dni cpaddacla1_h_P1 "cpaddacla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacla1_h") (CPTYPE V4HI))
+ "cpaddacla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpaddacla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 01000 cpsuba1u.b crqp,crpp (p0_1)
+(dni cpsuba1u_b_P1 "cpsuba1u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1u_b") (CPTYPE V8UQI))
+ "cpsuba1u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsuba1u_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 01001 cpsuba1.b crqp,crpp (p0_1)
+(dni cpsuba1_b_P1 "cpsuba1.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1_b") (CPTYPE V8QI))
+ "cpsuba1.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsuba1_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 01010 cpsubua1.h crqp,crpp (p0_1)
+(dni cpsubua1_h_P1 "cpsubua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubua1_h") (CPTYPE V4HI))
+ "cpsubua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsubua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 01011 cpsubla1.h crqp,crpp (p0_1)
+(dni cpsubla1_h_P1 "cpsubla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubla1_h") (CPTYPE V4HI))
+ "cpsubla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpsubla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 01100 cpsubaca1u.b crqp,crpp (p0_1)
+(dni cpsubaca1u_b_P1 "cpsubaca1u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1u_b") (CPTYPE V8UQI))
+ "cpsubaca1u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsubaca1u_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 01101 cpsubaca1.b crqp,crpp (p0_1)
+(dni cpsubaca1_b_P1 "cpsubaca1.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1_b") (CPTYPE V8QI))
+ "cpsubaca1.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsubaca1_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 01110 cpsubacua1.h crqp,crpp (p0_1)
+(dni cpsubacua1_h_P1 "cpsubacua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacua1_h") (CPTYPE V4HI))
+ "cpsubacua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsubacua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 01111 cpsubacla1.h crqp,crpp (p0_1)
+(dni cpsubacla1_h_P1 "cpsubacla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacla1_h") (CPTYPE V4HI))
+ "cpsubacla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsubacla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 10000 cpabsa1u.b crqp,crpp (p0_1)
+(dni cpabsa1u_b_P1 "cpabsa1u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1u_b") (CPTYPE V8UQI))
+ "cpabsa1u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpabsa1u_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 10001 cpabsa1.b crqp,crpp (p0_1)
+(dni cpabsa1_b_P1 "cpabsa1.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1_b") (CPTYPE V8QI))
+ "cpabsa1.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpabsa1_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 10010 cpabsua1.h crqp,crpp (p0_1)
+(dni cpabsua1_h_P1 "cpabsua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsua1_h") (CPTYPE V4HI))
+ "cpabsua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpabsua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 10011 cpabsla1.h crqp,crpp (p0_1)
+(dni cpabsla1_h_P1 "cpabsla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsla1_h") (CPTYPE V4HI))
+ "cpabsla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpabsla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 10100 cpsada1u.b crqp,crpp (p0_1)
+(dni cpsada1u_b_P1 "cpsada1u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1u_b") (CPTYPE V8UQI))
+ "cpsada1u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsada1u_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 10101 cpsada1.b crqp,crpp (p0_1)
+(dni cpsada1_b_P1 "cpsada1.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1_b") (CPTYPE V8QI))
+ "cpsada1.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsada1_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 10110 cpsadua1.h crqp,crpp (p0_1)
+(dni cpsadua1_h_P1 "cpsadua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadua1_h") (CPTYPE V4HI))
+ "cpsadua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsadua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 10111 cpsadla1.h crqp,crpp (p0_1)
+(dni cpsadla1_h_P1 "cpsadla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadla1_h") (CPTYPE V4HI))
+ "cpsadla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsadla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 11011 cpseta1.h crqp,crpp (p0_1)
+(dni cpseta1_h_P1 "cpseta1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpseta1_h") (CPTYPE V4HI))
+ "cpseta1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpseta1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 11100 cpsetua1.w crqp,crpp (p0_1)
+(dni cpsetua1_w_P1 "cpsetua1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetua1_w") (CPTYPE V2SI))
+ "cpsetua1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsetua1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11000 qqqqq ppppp 11101 cpsetla1.w crqp,crpp (p0_1)
+(dni cpsetla1_w_P1 "cpsetla1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetla1_w") (CPTYPE V2SI))
+ "cpsetla1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpsetla1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11001 00000 00001 ooooo cpmova1.b =crop (p0_1)
+(dni cpmova1_b_P1 "cpmova1.b $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmova1_b") (CPTYPE V8QI) (CRET FIRST))
+ "cpmova1.b $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmova1_b" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 00010 ooooo cpmovua1.h =crop (p0_1)
+(dni cpmovua1_h_P1 "cpmovua1.h $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovua1_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpmovua1.h $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovua1_h" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 00011 ooooo cpmovla1.h =crop (p0_1)
+(dni cpmovla1_h_P1 "cpmovla1.h $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovla1_h") (CPTYPE V4HI) (CRET FIRST))
+ "cpmovla1.h $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovla1_h" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 00100 ooooo cpmovuua1.w =crop (p0_1)
+(dni cpmovuua1_w_P1 "cpmovuua1.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovuua1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovuua1.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovuua1_w" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 00101 ooooo cpmovula1.w =crop (p0_1)
+(dni cpmovula1_w_P1 "cpmovula1.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovula1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovula1.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovula1_w" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 00110 ooooo cpmovlua1.w =crop (p0_1)
+(dni cpmovlua1_w_P1 "cpmovlua1.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovlua1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovlua1.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovlua1_w" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 00111 ooooo cpmovlla1.w =crop (p0_1)
+(dni cpmovlla1_w_P1 "cpmovlla1.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovlla1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovlla1.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovlla1_w" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 01000 ooooo cppacka1u.b =crop (p0_1)
+(dni cppacka1u_b_P1 "cppacka1u.b $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppacka1u_b") (CPTYPE V8UQI) (CRET FIRST))
+ "cppacka1u.b $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppacka1u_b" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 01001 ooooo cppacka1.b =crop (p0_1)
+(dni cppacka1_b_P1 "cppacka1.b $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppacka1_b") (CPTYPE V8QI) (CRET FIRST))
+ "cppacka1.b $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppacka1_b" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 01010 ooooo cppackua1.h =crop (p0_1)
+(dni cppackua1_h_P1 "cppackua1.h $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackua1_h") (CPTYPE V4HI) (CRET FIRST))
+ "cppackua1.h $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppackua1_h" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 01011 ooooo cppackla1.h =crop (p0_1)
+(dni cppackla1_h_P1 "cppackla1.h $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackla1_h") (CPTYPE V4HI) (CRET FIRST))
+ "cppackla1.h $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppackla1_h" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 01100 ooooo cppackua1.w =crop (p0_1)
+(dni cppackua1_w_P1 "cppackua1.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackua1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cppackua1.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xc) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppackua1_w" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 01101 ooooo cppackla1.w =crop (p0_1)
+(dni cppackla1_w_P1 "cppackla1.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackla1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cppackla1.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cppackla1_w" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 01110 ooooo cpmovhua1.w =crop (p0_1)
+(dni cpmovhua1_w_P1 "cpmovhua1.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovhua1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovhua1.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovhua1_w" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 01111 ooooo cpmovhla1.w =crop (p0_1)
+(dni cpmovhla1_w_P1 "cpmovhla1.w $crop Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovhla1_w") (CPTYPE V2SI) (CRET FIRST))
+ "cpmovhla1.w $crop"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crop (c-call DI "ivc2_cpmovhla1_w" pc)) )
+ ()
+ )
+
+; 00000000 11001 00000 10000 00000 cpacsuma1 (p0_1)
+(dni cpacsuma1_P1 "cpacsuma1 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpacsuma1"))
+ "cpacsuma1"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpacsuma1" pc) )
+ ()
+ )
+
+; 00000000 11001 00000 10001 00000 cpaccpa1 (p0_1)
+(dni cpaccpa1_P1 "cpaccpa1 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaccpa1"))
+ "cpaccpa1"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpaccpa1" pc) )
+ ()
+ )
+
+; 00000000 11001 00000 10010 00000 cpacswp (p0_1)
+(dni cpacswp_P1 "cpacswp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpacswp") VOLATILE)
+ "cpacswp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x12) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpacswp" pc) )
+ ()
+ )
+
+; 00000000 11001 qqqqq 11000 00000 cpsrla1 crqp (p0_1)
+(dni cpsrla1_P1 "cpsrla1 $crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsrla1"))
+ "cpsrla1 $crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x18) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsrla1" pc crqp) )
+ ()
+ )
+
+; 00000000 11001 qqqqq 11001 00000 cpsraa1 crqp (p0_1)
+(dni cpsraa1_P1 "cpsraa1 $crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsraa1"))
+ "cpsraa1 $crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x19) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsraa1" pc crqp) )
+ ()
+ )
+
+; 00000000 11001 qqqqq 11010 00000 cpslla1 crqp (p0_1)
+(dni cpslla1_P1 "cpslla1 $crqp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpslla1"))
+ "cpslla1 $crqp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x1a) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpslla1" pc crqp) )
+ ()
+ )
+
+; 00000000 11001 00000 11100 iiiii cpsrlia1 imm5p23 (p0_1)
+(dni cpsrlia1_1_p1 "cpsrlia1 imm5p23 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsrlia1"))
+ "cpsrlia1 $imm5p23"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1c) imm5p23 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsrlia1" pc imm5p23) )
+ ()
+ )
+
+; 00000000 11001 00000 11101 iiiii cpsraia1 imm5p23 (p0_1)
+(dni cpsraia1_1_p1 "cpsraia1 imm5p23 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsraia1"))
+ "cpsraia1 $imm5p23"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1d) imm5p23 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsraia1" pc imm5p23) )
+ ()
+ )
+
+; 00000000 11001 00000 11110 iiiii cpsllia1 imm5p23 (p0_1)
+(dni cpsllia1_1_p1 "cpsllia1 imm5p23 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsllia1"))
+ "cpsllia1 $imm5p23"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1e) imm5p23 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpsllia1" pc imm5p23) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 00000 cpfmulia1s0u.b crqp,crpp,simm8p0 (p0_1)
+(dni cpfmulia1s0u_b_P1 "cpfmulia1s0u.b $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0u_b") (CPTYPE V8UQI))
+ "cpfmulia1s0u.b $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpfmulia1s0u_b" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 00001 cpfmulia1s0.b crqp,crpp,simm8p0 (p0_1)
+(dni cpfmulia1s0_b_P1 "cpfmulia1s0.b $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0_b") (CPTYPE V8QI))
+ "cpfmulia1s0.b $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpfmulia1s0_b" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 00010 cpfmuliua1s0.h crqp,crpp,simm8p0 (p0_1)
+(dni cpfmuliua1s0_h_P1 "cpfmuliua1s0.h $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s0_h") (CPTYPE V4HI))
+ "cpfmuliua1s0.h $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpfmuliua1s0_h" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 00011 cpfmulila1s0.h crqp,crpp,simm8p0 (p0_1)
+(dni cpfmulila1s0_h_P1 "cpfmulila1s0.h $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s0_h") (CPTYPE V4HI))
+ "cpfmulila1s0.h $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpfmulila1s0_h" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 00100 cpfmadia1s0u.b crqp,crpp,simm8p0 (p0_1)
+(dni cpfmadia1s0u_b_P1 "cpfmadia1s0u.b $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0u_b") (CPTYPE V8UQI))
+ "cpfmadia1s0u.b $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpfmadia1s0u_b" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 00101 cpfmadia1s0.b crqp,crpp,simm8p0 (p0_1)
+(dni cpfmadia1s0_b_P1 "cpfmadia1s0.b $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0_b") (CPTYPE V8QI))
+ "cpfmadia1s0.b $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpfmadia1s0_b" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 00110 cpfmadiua1s0.h crqp,crpp,simm8p0 (p0_1)
+(dni cpfmadiua1s0_h_P1 "cpfmadiua1s0.h $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s0_h") (CPTYPE V4HI))
+ "cpfmadiua1s0.h $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpfmadiua1s0_h" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 00111 cpfmadila1s0.h crqp,crpp,simm8p0 (p0_1)
+(dni cpfmadila1s0_h_P1 "cpfmadila1s0.h $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s0_h") (CPTYPE V4HI))
+ "cpfmadila1s0.h $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpfmadila1s0_h" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 01000 cpfmulia1s1u.b crqp,crpp,simm8p0 (p0_1)
+(dni cpfmulia1s1u_b_P1 "cpfmulia1s1u.b $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1u_b") (CPTYPE V8UQI))
+ "cpfmulia1s1u.b $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpfmulia1s1u_b" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 01001 cpfmulia1s1.b crqp,crpp,simm8p0 (p0_1)
+(dni cpfmulia1s1_b_P1 "cpfmulia1s1.b $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1_b") (CPTYPE V8QI))
+ "cpfmulia1s1.b $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpfmulia1s1_b" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 01010 cpfmuliua1s1.h crqp,crpp,simm8p0 (p0_1)
+(dni cpfmuliua1s1_h_P1 "cpfmuliua1s1.h $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s1_h") (CPTYPE V4HI))
+ "cpfmuliua1s1.h $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpfmuliua1s1_h" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 01011 cpfmulila1s1.h crqp,crpp,simm8p0 (p0_1)
+(dni cpfmulila1s1_h_P1 "cpfmulila1s1.h $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s1_h") (CPTYPE V4HI))
+ "cpfmulila1s1.h $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpfmulila1s1_h" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 01100 cpfmadia1s1u.b crqp,crpp,simm8p0 (p0_1)
+(dni cpfmadia1s1u_b_P1 "cpfmadia1s1u.b $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1u_b") (CPTYPE V8UQI))
+ "cpfmadia1s1u.b $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpfmadia1s1u_b" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 01101 cpfmadia1s1.b crqp,crpp,simm8p0 (p0_1)
+(dni cpfmadia1s1_b_P1 "cpfmadia1s1.b $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1_b") (CPTYPE V8QI))
+ "cpfmadia1s1.b $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpfmadia1s1_b" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 01110 cpfmadiua1s1.h crqp,crpp,simm8p0 (p0_1)
+(dni cpfmadiua1s1_h_P1 "cpfmadiua1s1.h $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s1_h") (CPTYPE V4HI))
+ "cpfmadiua1s1.h $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpfmadiua1s1_h" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 01111 cpfmadila1s1.h crqp,crpp,simm8p0 (p0_1)
+(dni cpfmadila1s1_h_P1 "cpfmadila1s1.h $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s1_h") (CPTYPE V4HI))
+ "cpfmadila1s1.h $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpfmadila1s1_h" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 10000 cpamulia1u.b crqp,crpp,simm8p0 (p0_1)
+(dni cpamulia1u_b_P1 "cpamulia1u.b $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1u_b") (CPTYPE V8UQI))
+ "cpamulia1u.b $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpamulia1u_b" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 10001 cpamulia1.b crqp,crpp,simm8p0 (p0_1)
+(dni cpamulia1_b_P1 "cpamulia1.b $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1_b") (CPTYPE V8QI))
+ "cpamulia1.b $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpamulia1_b" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 10010 cpamuliua1.h crqp,crpp,simm8p0 (p0_1)
+(dni cpamuliua1_h_P1 "cpamuliua1.h $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamuliua1_h") (CPTYPE V4HI))
+ "cpamuliua1.h $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpamuliua1_h" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 10011 cpamulila1.h crqp,crpp,simm8p0 (p0_1)
+(dni cpamulila1_h_P1 "cpamulila1.h $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulila1_h") (CPTYPE V4HI))
+ "cpamulila1.h $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpamulila1_h" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 10100 cpamadia1u.b crqp,crpp,simm8p0 (p0_1)
+(dni cpamadia1u_b_P1 "cpamadia1u.b $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1u_b") (CPTYPE V8UQI))
+ "cpamadia1u.b $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpamadia1u_b" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 10101 cpamadia1.b crqp,crpp,simm8p0 (p0_1)
+(dni cpamadia1_b_P1 "cpamadia1.b $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1_b") (CPTYPE V8QI))
+ "cpamadia1.b $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpamadia1_b" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 10110 cpamadiua1.h crqp,crpp,simm8p0 (p0_1)
+(dni cpamadiua1_h_P1 "cpamadiua1.h $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadiua1_h") (CPTYPE V4HI))
+ "cpamadiua1.h $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpamadiua1_h" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11111 qqqqq ppppp 10111 cpamadila1.h crqp,crpp,simm8p0 (p0_1)
+(dni cpamadila1_h_P1 "cpamadila1.h $crqp,$crpp,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadila1_h") (CPTYPE V4HI))
+ "cpamadila1.h $crqp,$crpp,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpamadila1_h" pc crqp crpp simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11100 qqqqq ppppp 00 III cpfmulia1u.b crqp,crpp,imm3p25,simm8p0 (cpfm)
+(dni cpfmulia1u_b_P1 "cpfmulia1u.b $crqp,$crpp,imm3p25,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1u_b") (CPTYPE V8UQI))
+ "cpfmulia1u.b $crqp,$crpp,$imm3p25,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x0) imm3p25 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpfmulia1u_b" pc crqp crpp imm3p25 simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11100 qqqqq ppppp 01 III cpfmulia1.b crqp,crpp,imm3p25,simm8p0 (cpfm)
+(dni cpfmulia1_b_P1 "cpfmulia1.b $crqp,$crpp,imm3p25,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1_b") (CPTYPE V8QI))
+ "cpfmulia1.b $crqp,$crpp,$imm3p25,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x1) imm3p25 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpfmulia1_b" pc crqp crpp imm3p25 simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11100 qqqqq ppppp 10 III cpfmuliua1.h crqp,crpp,imm3p25,simm8p0 (cpfm)
+(dni cpfmuliua1_h_P1 "cpfmuliua1.h $crqp,$crpp,imm3p25,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1_h") (CPTYPE V4HI))
+ "cpfmuliua1.h $crqp,$crpp,$imm3p25,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x2) imm3p25 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpfmuliua1_h" pc crqp crpp imm3p25 simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11100 qqqqq ppppp 11 III cpfmulila1.h crqp,crpp,imm3p25,simm8p0 (cpfm)
+(dni cpfmulila1_h_P1 "cpfmulila1.h $crqp,$crpp,imm3p25,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1_h") (CPTYPE V4HI))
+ "cpfmulila1.h $crqp,$crpp,$imm3p25,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x3) imm3p25 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpfmulila1_h" pc crqp crpp imm3p25 simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11101 qqqqq ppppp 00 III cpfmadia1u.b crqp,crpp,imm3p25,simm8p0 (cpfm)
+(dni cpfmadia1u_b_P1 "cpfmadia1u.b $crqp,$crpp,imm3p25,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1u_b") (CPTYPE V8UQI))
+ "cpfmadia1u.b $crqp,$crpp,$imm3p25,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x0) imm3p25 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpfmadia1u_b" pc crqp crpp imm3p25 simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11101 qqqqq ppppp 01 III cpfmadia1.b crqp,crpp,imm3p25,simm8p0 (cpfm)
+(dni cpfmadia1_b_P1 "cpfmadia1.b $crqp,$crpp,imm3p25,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1_b") (CPTYPE V8QI))
+ "cpfmadia1.b $crqp,$crpp,$imm3p25,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x1) imm3p25 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpfmadia1_b" pc crqp crpp imm3p25 simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11101 qqqqq ppppp 10 III cpfmadiua1.h crqp,crpp,imm3p25,simm8p0 (cpfm)
+(dni cpfmadiua1_h_P1 "cpfmadiua1.h $crqp,$crpp,imm3p25,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1_h") (CPTYPE V4HI))
+ "cpfmadiua1.h $crqp,$crpp,$imm3p25,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x2) imm3p25 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpfmadiua1_h" pc crqp crpp imm3p25 simm8p0) )
+ ()
+ )
+
+; iiiiiiii 11101 qqqqq ppppp 11 III cpfmadila1.h crqp,crpp,imm3p25,simm8p0 (cpfm)
+(dni cpfmadila1_h_P1 "cpfmadila1.h $crqp,$crpp,imm3p25,simm8p0 Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1_h") (CPTYPE V4HI))
+ "cpfmadila1.h $crqp,$crpp,$imm3p25,$simm8p0"
+ (+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x3) imm3p25 (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpfmadila1_h" pc crqp crpp imm3p25 simm8p0) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 00000 cpssqa1u.b crqp,crpp (p0_1)
+(dni cpssqa1u_b_P1 "cpssqa1u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1u_b") (CPTYPE V8UQI))
+ "cpssqa1u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpssqa1u_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 00001 cpssqa1.b crqp,crpp (p0_1)
+(dni cpssqa1_b_P1 "cpssqa1.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1_b") (CPTYPE V8QI))
+ "cpssqa1.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpssqa1_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 00100 cpssda1u.b crqp,crpp (p0_1)
+(dni cpssda1u_b_P1 "cpssda1u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1u_b") (CPTYPE V8UQI))
+ "cpssda1u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpssda1u_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 00101 cpssda1.b crqp,crpp (p0_1)
+(dni cpssda1_b_P1 "cpssda1.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1_b") (CPTYPE V8QI))
+ "cpssda1.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpssda1_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 01000 cpmula1u.b crqp,crpp (p0_1)
+(dni cpmula1u_b_P1 "cpmula1u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1u_b") (CPTYPE V8UQI))
+ "cpmula1u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpmula1u_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 01001 cpmula1.b crqp,crpp (p0_1)
+(dni cpmula1_b_P1 "cpmula1.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1_b") (CPTYPE V8QI))
+ "cpmula1.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpmula1_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 01010 cpmulua1.h crqp,crpp (p0_1)
+(dni cpmulua1_h_P1 "cpmulua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_h") (CPTYPE V4HI))
+ "cpmulua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpmulua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 01011 cpmulla1.h crqp,crpp (p0_1)
+(dni cpmulla1_h_P1 "cpmulla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_h") (CPTYPE V4HI))
+ "cpmulla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpmulla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 01100 cpmulua1u.w crqp,crpp (p0_1)
+(dni cpmulua1u_w_P1 "cpmulua1u.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1u_w") (CPTYPE V2USI))
+ "cpmulua1u.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpmulua1u_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 01101 cpmulla1u.w crqp,crpp (p0_1)
+(dni cpmulla1u_w_P1 "cpmulla1u.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1u_w") (CPTYPE V2USI))
+ "cpmulla1u.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpmulla1u_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 01110 cpmulua1.w crqp,crpp (p0_1)
+(dni cpmulua1_w_P1 "cpmulua1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_w") (CPTYPE V2SI))
+ "cpmulua1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (c-call "ivc2_cpmulua1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 01111 cpmulla1.w crqp,crpp (p0_1)
+(dni cpmulla1_w_P1 "cpmulla1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_w") (CPTYPE V2SI))
+ "cpmulla1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (c-call "ivc2_cpmulla1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 10000 cpmada1u.b crqp,crpp (p0_1)
+(dni cpmada1u_b_P1 "cpmada1u.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1u_b") (CPTYPE V8UQI))
+ "cpmada1u.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmada1u_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 10001 cpmada1.b crqp,crpp (p0_1)
+(dni cpmada1_b_P1 "cpmada1.b $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1_b") (CPTYPE V8QI))
+ "cpmada1.b $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmada1_b" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 10010 cpmadua1.h crqp,crpp (p0_1)
+(dni cpmadua1_h_P1 "cpmadua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_h") (CPTYPE V4HI))
+ "cpmadua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmadua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 10011 cpmadla1.h crqp,crpp (p0_1)
+(dni cpmadla1_h_P1 "cpmadla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_h") (CPTYPE V4HI))
+ "cpmadla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmadla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 10100 cpmadua1u.w crqp,crpp (p0_1)
+(dni cpmadua1u_w_P1 "cpmadua1u.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1u_w") (CPTYPE V2USI))
+ "cpmadua1u.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmadua1u_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 10101 cpmadla1u.w crqp,crpp (p0_1)
+(dni cpmadla1u_w_P1 "cpmadla1u.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1u_w") (CPTYPE V2USI))
+ "cpmadla1u.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmadla1u_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 10110 cpmadua1.w crqp,crpp (p0_1)
+(dni cpmadua1_w_P1 "cpmadua1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_w") (CPTYPE V2SI))
+ "cpmadua1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmadua1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 10111 cpmadla1.w crqp,crpp (p0_1)
+(dni cpmadla1_w_P1 "cpmadla1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_w") (CPTYPE V2SI))
+ "cpmadla1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmadla1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 11010 cpmsbua1.h crqp,crpp (p0_1)
+(dni cpmsbua1_h_P1 "cpmsbua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_h") (CPTYPE V4HI))
+ "cpmsbua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmsbua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 11011 cpmsbla1.h crqp,crpp (p0_1)
+(dni cpmsbla1_h_P1 "cpmsbla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_h") (CPTYPE V4HI))
+ "cpmsbla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmsbla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 11100 cpmsbua1u.w crqp,crpp (p0_1)
+(dni cpmsbua1u_w_P1 "cpmsbua1u.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1u_w") (CPTYPE V2USI))
+ "cpmsbua1u.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmsbua1u_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 11101 cpmsbla1u.w crqp,crpp (p0_1)
+(dni cpmsbla1u_w_P1 "cpmsbla1u.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1u_w") (CPTYPE V2USI))
+ "cpmsbla1u.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmsbla1u_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 11110 cpmsbua1.w crqp,crpp (p0_1)
+(dni cpmsbua1_w_P1 "cpmsbua1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_w") (CPTYPE V2SI))
+ "cpmsbua1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmsbua1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000000 11110 qqqqq ppppp 11111 cpmsbla1.w crqp,crpp (p0_1)
+(dni cpmsbla1_w_P1 "cpmsbla1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_w") (CPTYPE V2SI))
+ "cpmsbla1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmsbla1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 11110 qqqqq ppppp 10010 cpsmadua1.h crqp,crpp (p0_1)
+(dni cpsmadua1_h_P1 "cpsmadua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_h") (CPTYPE V4HI))
+ "cpsmadua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 11110 qqqqq ppppp 10011 cpsmadla1.h crqp,crpp (p0_1)
+(dni cpsmadla1_h_P1 "cpsmadla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_h") (CPTYPE V4HI))
+ "cpsmadla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 11110 qqqqq ppppp 10110 cpsmadua1.w crqp,crpp (p0_1)
+(dni cpsmadua1_w_P1 "cpsmadua1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_w") (CPTYPE V2SI))
+ "cpsmadua1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadua1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 11110 qqqqq ppppp 10111 cpsmadla1.w crqp,crpp (p0_1)
+(dni cpsmadla1_w_P1 "cpsmadla1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_w") (CPTYPE V2SI))
+ "cpsmadla1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadla1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 11110 qqqqq ppppp 11010 cpsmsbua1.h crqp,crpp (p0_1)
+(dni cpsmsbua1_h_P1 "cpsmsbua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_h") (CPTYPE V4HI))
+ "cpsmsbua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 11110 qqqqq ppppp 11011 cpsmsbla1.h crqp,crpp (p0_1)
+(dni cpsmsbla1_h_P1 "cpsmsbla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_h") (CPTYPE V4HI))
+ "cpsmsbla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 11110 qqqqq ppppp 11110 cpsmsbua1.w crqp,crpp (p0_1)
+(dni cpsmsbua1_w_P1 "cpsmsbua1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_w") (CPTYPE V2SI))
+ "cpsmsbua1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbua1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000001 11110 qqqqq ppppp 11111 cpsmsbla1.w crqp,crpp (p0_1)
+(dni cpsmsbla1_w_P1 "cpsmsbla1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_w") (CPTYPE V2SI))
+ "cpsmsbla1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbla1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000010 11110 qqqqq ppppp 01010 cpmulslua1.h crqp,crpp (p0_1)
+(dni cpmulslua1_h_P1 "cpmulslua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_h") (CPTYPE V4HI))
+ "cpmulslua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmulslua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000010 11110 qqqqq ppppp 01011 cpmulslla1.h crqp,crpp (p0_1)
+(dni cpmulslla1_h_P1 "cpmulslla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_h") (CPTYPE V4HI))
+ "cpmulslla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmulslla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000010 11110 qqqqq ppppp 01110 cpmulslua1.w crqp,crpp (p0_1)
+(dni cpmulslua1_w_P1 "cpmulslua1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_w") (CPTYPE V2SI))
+ "cpmulslua1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmulslua1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000010 11110 qqqqq ppppp 01111 cpmulslla1.w crqp,crpp (p0_1)
+(dni cpmulslla1_w_P1 "cpmulslla1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_w") (CPTYPE V2SI))
+ "cpmulslla1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpmulslla1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000011 11110 qqqqq ppppp 10010 cpsmadslua1.h crqp,crpp (p0_1)
+(dni cpsmadslua1_h_P1 "cpsmadslua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_h") (CPTYPE V4HI))
+ "cpsmadslua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadslua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000011 11110 qqqqq ppppp 10011 cpsmadslla1.h crqp,crpp (p0_1)
+(dni cpsmadslla1_h_P1 "cpsmadslla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_h") (CPTYPE V4HI))
+ "cpsmadslla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadslla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000011 11110 qqqqq ppppp 10110 cpsmadslua1.w crqp,crpp (p0_1)
+(dni cpsmadslua1_w_P1 "cpsmadslua1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_w") (CPTYPE V2SI))
+ "cpsmadslua1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadslua1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000011 11110 qqqqq ppppp 10111 cpsmadslla1.w crqp,crpp (p0_1)
+(dni cpsmadslla1_w_P1 "cpsmadslla1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_w") (CPTYPE V2SI))
+ "cpsmadslla1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmadslla1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000011 11110 qqqqq ppppp 11010 cpsmsbslua1.h crqp,crpp (p0_1)
+(dni cpsmsbslua1_h_P1 "cpsmsbslua1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_h") (CPTYPE V4HI))
+ "cpsmsbslua1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbslua1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000011 11110 qqqqq ppppp 11011 cpsmsbslla1.h crqp,crpp (p0_1)
+(dni cpsmsbslla1_h_P1 "cpsmsbslla1.h $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_h") (CPTYPE V4HI))
+ "cpsmsbslla1.h $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbslla1_h" pc crqp crpp) )
+ ()
+ )
+
+; 00000011 11110 qqqqq ppppp 11110 cpsmsbslua1.w crqp,crpp (p0_1)
+(dni cpsmsbslua1_w_P1 "cpsmsbslua1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_w") (CPTYPE V2SI))
+ "cpsmsbslua1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbslua1_w" pc crqp crpp) )
+ ()
+ )
+
+; 00000011 11110 qqqqq ppppp 11111 cpsmsbslla1.w crqp,crpp (p0_1)
+(dni cpsmsbslla1_w_P1 "cpsmsbslla1.w $crqp,$crpp Pn"
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_w") (CPTYPE V2SI))
+ "cpsmsbslla1.w $crqp,$crpp"
+ (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0))
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
+ (c-call "ivc2_cpsmsbslla1_w" pc crqp crpp) )
+ ()
+ )
+
--- /dev/null
+/* libgcc routines for Toshiba Media Processor.
+ Copyright (C) 2001, 2002, 2005, 2009 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 3 of the License, or (at your
+option) any later version.
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+<http://www.gnu.org/licenses/>. */
+
+#define SAVEALL \
+ add3 $sp, $sp, -16*4 ; \
+ sw $0, ($sp) ; \
+ sw $1, 4($sp) ; \
+ sw $2, 8($sp) ; \
+ sw $3, 12($sp) ; \
+ sw $4, 16($sp) ; \
+ sw $5, 20($sp) ; \
+ sw $6, 24($sp) ; \
+ sw $7, 28($sp) ; \
+ sw $8, 32($sp) ; \
+ sw $9, 36($sp) ; \
+ sw $10, 40($sp) ; \
+ sw $11, 44($sp) ; \
+ sw $12, 48($sp) ; \
+ sw $13, 52($sp) ; \
+ sw $14, 56($sp) ; \
+ ldc $5, $lp ; \
+ add $5, 3 ; \
+ mov $6, -4 ; \
+ and $5, $6
+
+#define RESTOREALL \
+ stc $5, $lp ; \
+ lw $14, 56($sp) ; \
+ lw $13, 52($sp) ; \
+ lw $12, 48($sp) ; \
+ lw $11, 44($sp) ; \
+ lw $10, 40($sp) ; \
+ lw $9, 36($sp) ; \
+ lw $8, 32($sp) ; \
+ lw $7, 28($sp) ; \
+ lw $6, 24($sp) ; \
+ lw $5, 20($sp) ; \
+ lw $4, 16($sp) ; \
+ lw $3, 12($sp) ; \
+ lw $2, 8($sp) ; \
+ lw $1, 4($sp) ; \
+ lw $0, ($sp) ; \
+ add3 $sp, $sp, 16*4 ; \
+ ret
+
+#ifdef L_mep_profile
+ .text
+ .global __mep_mcount
+__mep_mcount:
+ SAVEALL
+ ldc $1, $lp
+ mov $2, $0
+ bsr __mep_mcount_2
+ RESTOREALL
+#endif
+
+#ifdef L_mep_bb_init_trace
+ .text
+ .global __mep_bb_init_trace_func
+__mep_bb_init_trace_func:
+ SAVEALL
+ lw $1, ($5)
+ lw $2, 4($5)
+ add $5, 8
+ bsr __bb_init_trace_func
+ RESTOREALL
+#endif
+
+#ifdef L_mep_bb_init
+ .text
+ .global __mep_bb_init_func
+__mep_bb_init_func:
+ SAVEALL
+ lw $1, ($5)
+ add $5, 4
+ bsr __bb_init_func
+ RESTOREALL
+#endif
+
+#ifdef L_mep_bb_trace
+ .text
+ .global __mep_bb_trace_func
+__mep_bb_trace_func:
+ SAVEALL
+ movu $3, __bb
+ lw $1, ($5)
+ sw $1, ($3)
+ lw $2, 4($5)
+ sw $2, 4($3)
+ add $5, 8
+ bsr __bb_trace_func
+ RESTOREALL
+#endif
+
+#ifdef L_mep_bb_increment
+ .text
+ .global __mep_bb_increment_func
+__mep_bb_increment_func:
+ SAVEALL
+ lw $1, ($5)
+ lw $0, ($1)
+ add $0, 1
+ sw $0, ($1)
+ add $5, 4
+ RESTOREALL
+#endif
--- /dev/null
+/* libgcc routines for MeP.
+ Copyright 2001, 2002, 2009 Free Software Foundation, Inc
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 3 of the License, or (at your
+option) any later version.
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+<http://www.gnu.org/licenses/>. */
+
+typedef int SItype __attribute__ ((mode (SI)));
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+
+typedef int word_type __attribute__ ((mode (__word__)));
+
+USItype
+__mulsi3 (USItype a, USItype b)
+{
+ USItype c = 0;
+
+ while (a != 0)
+ {
+ if (a & 1)
+ c += b;
+ a >>= 1;
+ b <<= 1;
+ }
+
+ return c;
+}
+
+
+
+USItype
+udivmodsi4(USItype num, USItype den, word_type modwanted)
+{
+ USItype bit = 1;
+ USItype res = 0;
+
+ while (den < num && bit && !(den & (1L<<31)))
+ {
+ den <<=1;
+ bit <<=1;
+ }
+ while (bit)
+ {
+ if (num >= den)
+ {
+ num -= den;
+ res |= bit;
+ }
+ bit >>=1;
+ den >>=1;
+ }
+ if (modwanted) return num;
+ return res;
+}
+
+
+
+SItype
+__divsi3 (SItype a, SItype b)
+{
+ word_type neg = 0;
+ SItype res;
+
+ if (a < 0)
+ {
+ a = -a;
+ neg = !neg;
+ }
+
+ if (b < 0)
+ {
+ b = -b;
+ neg = !neg;
+ }
+
+ res = udivmodsi4 (a, b, 0);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
+
+
+
+SItype
+__modsi3 (SItype a, SItype b)
+{
+ word_type neg = 0;
+ SItype res;
+
+ if (a < 0)
+ {
+ a = -a;
+ neg = 1;
+ }
+
+ if (b < 0)
+ b = -b;
+
+ res = udivmodsi4 (a, b, 1);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
+
+
+
+
+SItype
+__udivsi3 (SItype a, SItype b)
+{
+ return udivmodsi4 (a, b, 0);
+}
+
+
+
+SItype
+__umodsi3 (SItype a, SItype b)
+{
+ return udivmodsi4 (a, b, 1);
+}
--- /dev/null
+/* Definitions of Toshiba Media Processor
+ Copyright (C) 2001, 2002, 2003, 2005, 2006, 2007, 2009 Free
+ Software Foundation, Inc. Contributed by Red Hat, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#include <stdio.h>
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "rtl.h"
+#include "toplev.h"
+#include "c-pragma.h"
+#include "cpplib.h"
+#include "hard-reg-set.h"
+#include "output.h"
+#include "mep-protos.h"
+#include "function.h"
+#define MAX_RECOG_OPERANDS 10
+#include "reload.h"
+#include "target.h"
+
+enum cw_which { CW_AVAILABLE, CW_CALL_SAVED };
+
+static enum cpp_ttype
+mep_pragma_lex (tree *valp)
+{
+ enum cpp_ttype t = pragma_lex (valp);
+ if (t == CPP_EOF)
+ t = CPP_PRAGMA_EOL;
+ return t;
+}
+
+static void
+mep_pragma_io_volatile (cpp_reader *reader ATTRIBUTE_UNUSED)
+{
+ /* On off. */
+ tree val;
+ enum cpp_ttype type;
+ const char * str;
+
+ type = mep_pragma_lex (&val);
+ if (type == CPP_NAME)
+ {
+ str = IDENTIFIER_POINTER (val);
+
+ type = mep_pragma_lex (&val);
+ if (type != CPP_PRAGMA_EOL)
+ warning (0, "junk at end of #pragma io_volatile");
+
+ if (strcmp (str, "on") == 0)
+ {
+ target_flags |= MASK_IO_VOLATILE;
+ return;
+ }
+ if (strcmp (str, "off") == 0)
+ {
+ target_flags &= ~ MASK_IO_VOLATILE;
+ return;
+ }
+ }
+
+ error ("#pragma io_volatile takes only on or off");
+}
+
+static unsigned int
+parse_cr_reg (const char * str)
+{
+ unsigned int regno;
+
+ regno = decode_reg_name (str);
+ if (regno >= FIRST_PSEUDO_REGISTER)
+ return INVALID_REGNUM;
+
+ /* Verify that the regno is in CR_REGS. */
+ if (! TEST_HARD_REG_BIT (reg_class_contents[CR_REGS], regno))
+ return INVALID_REGNUM;
+ return regno;
+}
+
+static bool
+parse_cr_set (HARD_REG_SET * set)
+{
+ tree val;
+ enum cpp_ttype type;
+ unsigned int last_regno = INVALID_REGNUM;
+ bool do_range = false;
+
+ CLEAR_HARD_REG_SET (*set);
+
+ while ((type = mep_pragma_lex (&val)) != CPP_PRAGMA_EOL)
+ {
+ if (type == CPP_COMMA)
+ {
+ last_regno = INVALID_REGNUM;
+ do_range = false;
+ }
+ else if (type == CPP_ELLIPSIS)
+ {
+ if (last_regno == INVALID_REGNUM)
+ {
+ error ("invalid coprocessor register range");
+ return false;
+ }
+ do_range = true;
+ }
+ else if (type == CPP_NAME || type == CPP_STRING)
+ {
+ const char *str;
+ unsigned int regno, i;
+
+ if (TREE_CODE (val) == IDENTIFIER_NODE)
+ str = IDENTIFIER_POINTER (val);
+ else if (TREE_CODE (val) == STRING_CST)
+ str = TREE_STRING_POINTER (val);
+ else
+ gcc_unreachable ();
+
+ regno = parse_cr_reg (str);
+ if (regno == INVALID_REGNUM)
+ {
+ error ("invalid coprocessor register %qE", val);
+ return false;
+ }
+
+ if (do_range)
+ {
+ if (last_regno > regno)
+ i = regno, regno = last_regno;
+ else
+ i = last_regno;
+ do_range = false;
+ }
+ else
+ last_regno = i = regno;
+
+ while (i <= regno)
+ {
+ SET_HARD_REG_BIT (*set, i);
+ i++;
+ }
+ }
+ else
+ {
+ error ("malformed coprocessor register");
+ return false;
+ }
+ }
+ return true;
+}
+
+static void
+mep_pragma_coprocessor_which (enum cw_which cw_which)
+{
+ HARD_REG_SET set;
+
+ /* Process the balance of the pragma and turn it into a hard reg set. */
+ if (! parse_cr_set (&set))
+ return;
+
+ /* Process the collected hard reg set. */
+ switch (cw_which)
+ {
+ case CW_AVAILABLE:
+ {
+ int i;
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
+ if (TEST_HARD_REG_BIT (set, i))
+ fixed_regs[i] = 0;
+ }
+ break;
+
+ case CW_CALL_SAVED:
+ {
+ int i;
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
+ if (TEST_HARD_REG_BIT (set, i))
+ fixed_regs[i] = call_used_regs[i] = 0;
+ }
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+
+ /* Fix up register class hierarchy. */
+ save_register_info ();
+ reinit_regs ();
+
+ if (cfun == 0)
+ {
+ init_dummy_function_start ();
+ init_caller_save ();
+ expand_dummy_function_end ();
+ }
+ else
+ {
+ init_caller_save ();
+ }
+}
+
+static void
+mep_pragma_coprocessor_width (void)
+{
+ tree val;
+ enum cpp_ttype type;
+ HOST_WIDE_INT i;
+
+ type = mep_pragma_lex (&val);
+ switch (type)
+ {
+ case CPP_NUMBER:
+ if (! host_integerp (val, 1))
+ break;
+ i = tree_low_cst (val, 1);
+ /* This pragma no longer has any effect. */
+#if 0
+ if (i == 32)
+ target_flags &= ~MASK_64BIT_CR_REGS;
+ else if (i == 64)
+ target_flags |= MASK_64BIT_CR_REGS;
+ else
+ break;
+ targetm.init_builtins ();
+#else
+ if (i != 32 && i != 64)
+ break;
+#endif
+
+ type = mep_pragma_lex (&val);
+ if (type != CPP_PRAGMA_EOL)
+ warning (0, "junk at end of #pragma GCC coprocessor width");
+ return;
+
+ default:
+ break;
+ }
+
+ error ("#pragma GCC coprocessor width takes only 32 or 64");
+}
+
+static void
+mep_pragma_coprocessor_subclass (void)
+{
+ tree val;
+ enum cpp_ttype type;
+ HARD_REG_SET set;
+ int class_letter;
+ enum reg_class class;
+
+ type = mep_pragma_lex (&val);
+ if (type != CPP_CHAR)
+ goto syntax_error;
+ class_letter = tree_low_cst (val, 1);
+ if (class_letter >= 'A' && class_letter <= 'D')
+ class = class_letter - 'A' + USER0_REGS;
+ else
+ {
+ error ("#pragma GCC coprocessor subclass letter must be in [ABCD]");
+ return;
+ }
+ if (reg_class_size[class] > 0)
+ {
+ error ("#pragma GCC coprocessor subclass '%c' already defined",
+ class_letter);
+ return;
+ }
+
+ type = mep_pragma_lex (&val);
+ if (type != CPP_EQ)
+ goto syntax_error;
+
+ if (! parse_cr_set (&set))
+ return;
+
+ /* Fix up register class hierarchy. */
+ COPY_HARD_REG_SET (reg_class_contents[class], set);
+ init_regs ();
+ return;
+
+ syntax_error:
+ error ("malformed #pragma GCC coprocessor subclass");
+}
+
+static void
+mep_pragma_disinterrupt (cpp_reader *reader ATTRIBUTE_UNUSED)
+{
+ tree val;
+ enum cpp_ttype type;
+ int saw_one = 0;
+
+ for (;;)
+ {
+ type = mep_pragma_lex (&val);
+ if (type == CPP_COMMA)
+ continue;
+ if (type != CPP_NAME)
+ break;
+ mep_note_pragma_disinterrupt (IDENTIFIER_POINTER (val));
+ saw_one = 1;
+ }
+ if (!saw_one || type != CPP_PRAGMA_EOL)
+ {
+ error ("malformed #pragma disinterrupt");
+ return;
+ }
+}
+
+static void
+mep_pragma_coprocessor (cpp_reader *reader ATTRIBUTE_UNUSED)
+{
+ tree val;
+ enum cpp_ttype type;
+
+ type = mep_pragma_lex (&val);
+ if (type != CPP_NAME)
+ {
+ error ("malformed #pragma GCC coprocessor");
+ return;
+ }
+
+ if (!TARGET_COP)
+ error ("coprocessor not enabled");
+
+ if (strcmp (IDENTIFIER_POINTER (val), "available") == 0)
+ mep_pragma_coprocessor_which (CW_AVAILABLE);
+ else if (strcmp (IDENTIFIER_POINTER (val), "call_saved") == 0)
+ mep_pragma_coprocessor_which (CW_CALL_SAVED);
+ else if (strcmp (IDENTIFIER_POINTER (val), "width") == 0)
+ mep_pragma_coprocessor_width ();
+ else if (strcmp (IDENTIFIER_POINTER (val), "subclass") == 0)
+ mep_pragma_coprocessor_subclass ();
+ else
+ error ("unknown #pragma GCC coprocessor %E", val);
+}
+
+static void
+mep_pragma_call (cpp_reader *reader ATTRIBUTE_UNUSED)
+{
+ tree val;
+ enum cpp_ttype type;
+ int saw_one = 0;
+
+ for (;;)
+ {
+ type = mep_pragma_lex (&val);
+ if (type == CPP_COMMA)
+ continue;
+ if (type != CPP_NAME)
+ break;
+ mep_note_pragma_call (IDENTIFIER_POINTER (val));
+ saw_one = 1;
+ }
+ if (!saw_one || type != CPP_PRAGMA_EOL)
+ {
+ error ("malformed #pragma call");
+ return;
+ }
+}
+
+void
+mep_register_pragmas (void)
+{
+ c_register_pragma ("custom", "io_volatile", mep_pragma_io_volatile);
+ c_register_pragma ("GCC", "coprocessor", mep_pragma_coprocessor);
+ c_register_pragma (0, "disinterrupt", mep_pragma_disinterrupt);
+ c_register_pragma (0, "call", mep_pragma_call);
+}
--- /dev/null
+/* Prototypes for exported functions defined in mep.c
+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009 Free
+ Software Foundation, Inc.
+ Contributed by Red Hat Inc (dj@redhat.com)
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+extern void mep_conditional_register_usage (char *, char *);
+extern void mep_optimization_options (void);
+extern void mep_override_options (void);
+extern int mep_regno_reg_class (int);
+extern int mep_reg_class_from_constraint (int, const char *);
+extern bool mep_const_ok_for_letter_p (HOST_WIDE_INT, int);
+extern bool mep_extra_constraint (rtx, int);
+extern rtx mep_mulr_source (rtx, rtx, rtx, rtx);
+extern bool mep_reuse_lo_p (rtx, rtx, rtx, bool);
+extern bool mep_use_post_modify_p (rtx, rtx, rtx);
+extern bool mep_allow_clip (rtx, rtx, int);
+extern bool mep_bit_position_p (rtx, bool);
+extern bool mep_split_mov (rtx *, int);
+extern bool mep_vliw_mode_match (rtx);
+extern bool mep_multi_slot (rtx);
+extern bool mep_legitimate_address (enum machine_mode, rtx, int);
+extern int mep_legitimize_address (rtx *, rtx, enum machine_mode);
+#ifdef MAX_RELOADS
+extern int mep_legitimize_reload_address (rtx *, enum machine_mode, int, enum reload_type, int);
+#endif
+extern int mep_core_address_length (rtx, int);
+extern int mep_cop_address_length (rtx, int);
+extern bool mep_expand_mov (rtx *, enum machine_mode);
+extern bool mep_mov_ok (rtx *, enum machine_mode);
+extern void mep_split_wide_move (rtx *, enum machine_mode);
+#ifdef RTX_CODE
+extern bool mep_expand_setcc (rtx *);
+extern rtx mep_expand_cbranch (rtx *);
+#endif
+extern const char *mep_emit_cbranch (rtx *, int);
+extern void mep_expand_call (rtx *, int);
+extern rtx mep_find_base_term (rtx);
+extern int mep_secondary_input_reload_class (enum reg_class, enum machine_mode, rtx);
+extern int mep_secondary_output_reload_class (enum reg_class, enum machine_mode, rtx);
+extern bool mep_secondary_memory_needed (enum reg_class, enum reg_class,
+ enum machine_mode);
+extern void mep_expand_reload (rtx *, enum machine_mode);
+extern enum reg_class mep_preferred_reload_class (rtx, enum reg_class);
+extern int mep_register_move_cost (enum machine_mode, enum reg_class, enum reg_class);
+extern void mep_init_expanders (void);
+extern rtx mep_return_addr_rtx (int);
+extern bool mep_epilogue_uses (int);
+extern int mep_elimination_offset (int, int);
+extern void mep_expand_prologue (void);
+extern void mep_expand_epilogue (void);
+extern void mep_expand_eh_return (rtx *);
+extern void mep_emit_eh_epilogue (rtx *);
+extern void mep_expand_sibcall_epilogue (void);
+extern rtx mep_return_stackadj_rtx (void);
+extern rtx mep_return_handler_rtx (void);
+extern void mep_function_profiler (FILE *);
+extern const char *mep_emit_bb_trace_ret (void);
+extern void mep_print_operand_address (FILE *, rtx);
+extern void mep_print_operand (FILE *, rtx, int);
+extern void mep_final_prescan_insn (rtx, rtx *, int);
+extern void mep_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
+extern rtx mep_function_arg (CUMULATIVE_ARGS, enum machine_mode, tree, int);
+extern void mep_arg_advance (CUMULATIVE_ARGS *, enum machine_mode, tree, int);
+extern bool mep_return_in_memory (const_tree, const_tree);
+extern rtx mep_function_value (tree, tree);
+extern rtx mep_libcall_value (enum machine_mode);
+extern void mep_asm_output_opcode (FILE *, const char *);
+extern void mep_note_pragma_disinterrupt (const char *);
+extern void mep_note_pragma_call (const char *);
+extern void mep_file_cleanups (void);
+extern const char *mep_strip_name_encoding (const char *);
+extern void mep_output_aligned_common (FILE *, tree, const char *,
+ int, int, int);
+extern void mep_init_trampoline (rtx, rtx, rtx);
+extern void mep_emit_doloop (rtx *, int);
+extern bool mep_vliw_function_p (tree);
+extern bool mep_store_data_bypass_p (rtx, rtx);
+extern bool mep_mul_hilo_bypass_p (rtx, rtx);
+extern bool mep_ipipe_ldc_p (rtx);
+extern bool mep_emit_intrinsic (int, const rtx *);
+extern bool mep_expand_unary_intrinsic (int, rtx *);
+extern bool mep_expand_binary_intrinsic (int, int, int, int, rtx *);
+extern int mep_intrinsic_length (int);
+
+extern void mep_register_pragmas (void);
+extern int mep_section_tag (rtx);
+extern bool mep_lookup_pragma_call (const char *);
+extern bool mep_have_core_copro_moves_p;
+extern bool mep_have_copro_copro_moves_p;
+
+extern bool mep_cannot_change_mode_class (enum machine_mode, enum machine_mode,
+ enum reg_class);
+
+extern int cgen_h_uint_6a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_7a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_8a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_6a2_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_22a4_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_2a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_24a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_6a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_5a4_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_2a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_16a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_3a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_5a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_16a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_8a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_7a2_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_6a4_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_5a8_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_4a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_10a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_12a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_20a1_immediate (rtx, enum machine_mode);
--- /dev/null
+/* Trampoline support for MeP
+ Copyright (C) 2004, 2007 Free Software Foundation, Inc.
+ Contributed by Red Hat Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 3 of the License, or (at your
+option) any later version.
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+<http://www.gnu.org/licenses/>. */
+
+/*
+ 7a0a ldc $10,$pc
+ c0ae000a lw $0,10($10)
+ caae000e lw $10,14($10)
+ 10ae jmp $10
+ 00000000 static chain
+ 00000000 function address
+*/
+
+static inline int
+cache_config_register(void) {
+ int rv;
+ asm ("ldc\t%0, $ccfg" : "=r" (rv));
+ return rv;
+}
+
+#define ICACHE_SIZE ((cache_config_register() >> 16) & 0x7f)
+#define DCACHE_SIZE (cache_config_register() & 0x7f)
+
+#define ICACHE_DATA_BASE 0x00300000
+#define ICACHE_TAG_BASE 0x00310000
+#define DCACHE_DATA_BASE 0x00320000
+#define DCACHE_TAG_BASE 0x00330000
+
+static inline void
+flush_dcache (int addr)
+{
+ asm volatile ("cache\t0, (%0)" : : "r" (addr));
+}
+
+void
+__mep_trampoline_helper (unsigned long *tramp,
+ int function_address,
+ int static_chain);
+
+void
+__mep_trampoline_helper (unsigned long *tramp,
+ int function_address,
+ int static_chain)
+{
+ int dsize, isize;
+
+#ifdef __LITTLE_ENDIAN__
+ tramp[0] = 0xc0ae7a0a;
+ tramp[1] = 0xcaae000a;
+ tramp[2] = 0x10ae000e;
+#else
+ tramp[0] = 0x7a0ac0ae;
+ tramp[1] = 0x000acaae;
+ tramp[2] = 0x000e10ae;
+#endif
+ tramp[3] = static_chain;
+ tramp[4] = function_address;
+
+ dsize = DCACHE_SIZE;
+ isize = ICACHE_SIZE;
+
+ if (dsize)
+ {
+ flush_dcache ((int)tramp);
+ flush_dcache ((int)tramp+16);
+ }
+
+ if (isize)
+ {
+ int imask = (isize * 1024) - 1;
+ int tmask = ~imask;
+ unsigned int i;
+ volatile unsigned int *tags;
+
+ imask &= 0xffe0;
+
+ for (i=(unsigned int)tramp; i<(unsigned int)tramp+20; i+=16)
+ {
+ tags = (unsigned int *)(ICACHE_TAG_BASE + (i & imask));
+ if ((*tags & tmask) == (i & tmask))
+ *tags &= ~1;
+ }
+ }
+}
--- /dev/null
+/* Definitions for Toshiba Media Processor
+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+ Free Software Foundation, Inc.
+ Contributed by Red Hat, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "rtl.h"
+#include "tree.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "flags.h"
+#include "recog.h"
+#include "obstack.h"
+#include "tree.h"
+#include "expr.h"
+#include "except.h"
+#include "function.h"
+#include "optabs.h"
+#include "reload.h"
+#include "tm_p.h"
+#include "ggc.h"
+#include "toplev.h"
+#include "integrate.h"
+#include "target.h"
+#include "target-def.h"
+#include "langhooks.h"
+#include "df.h"
+
+/* Structure of this file:
+
+ + Command Line Option Support
+ + Pattern support - constraints, predicates, expanders
+ + Reload Support
+ + Costs
+ + Functions to save and restore machine-specific function data.
+ + Frame/Epilog/Prolog Related
+ + Operand Printing
+ + Function args in registers
+ + Handle pipeline hazards
+ + Handle attributes
+ + Trampolines
+ + Machine-dependent Reorg
+ + Builtins. */
+
+/* Symbol encodings:
+
+ Symbols are encoded as @ <char> . <name> where <char> is one of these:
+
+ b - based
+ t - tiny
+ n - near
+ f - far
+ i - io, near
+ I - io, far
+ c - cb (control bus) */
+
+struct GTY(()) machine_function
+{
+ int mep_frame_pointer_needed;
+
+ /* For varargs. */
+ int arg_regs_to_save;
+ int regsave_filler;
+ int frame_filler;
+
+ /* Records __builtin_return address. */
+ rtx eh_stack_adjust;
+
+ int reg_save_size;
+ int reg_save_slot[FIRST_PSEUDO_REGISTER];
+ unsigned char reg_saved[FIRST_PSEUDO_REGISTER];
+
+ /* 2 if the current function has an interrupt attribute, 1 if not, 0
+ if unknown. This is here because resource.c uses EPILOGUE_USES
+ which needs it. */
+ int interrupt_handler;
+
+ /* Likewise, for disinterrupt attribute. */
+ int disable_interrupts;
+
+ /* Number of doloop tags used so far. */
+ int doloop_tags;
+
+ /* True if the last tag was allocated to a doloop_end. */
+ bool doloop_tag_from_end;
+
+ /* True if reload changes $TP. */
+ bool reload_changes_tp;
+
+ /* 2 if there are asm()s without operands, 1 if not, 0 if unknown.
+ We only set this if the function is an interrupt handler. */
+ int asms_without_operands;
+};
+
+#define MEP_CONTROL_REG(x) \
+ (GET_CODE (x) == REG && ANY_CONTROL_REGNO_P (REGNO (x)))
+
+static const struct attribute_spec mep_attribute_table[11];
+
+static GTY(()) section * based_section;
+static GTY(()) section * tinybss_section;
+static GTY(()) section * far_section;
+static GTY(()) section * farbss_section;
+static GTY(()) section * frodata_section;
+static GTY(()) section * srodata_section;
+
+static void mep_set_leaf_registers (int);
+static bool symbol_p (rtx);
+static bool symbolref_p (rtx);
+static void encode_pattern_1 (rtx);
+static void encode_pattern (rtx);
+static bool const_in_range (rtx, int, int);
+static void mep_rewrite_mult (rtx, rtx);
+static void mep_rewrite_mulsi3 (rtx, rtx, rtx, rtx);
+static void mep_rewrite_maddsi3 (rtx, rtx, rtx, rtx, rtx);
+static bool mep_reuse_lo_p_1 (rtx, rtx, rtx, bool);
+static bool move_needs_splitting (rtx, rtx, enum machine_mode);
+static bool mep_expand_setcc_1 (enum rtx_code, rtx, rtx, rtx);
+static bool mep_nongeneral_reg (rtx);
+static bool mep_general_copro_reg (rtx);
+static bool mep_nonregister (rtx);
+static struct machine_function* mep_init_machine_status (void);
+static rtx mep_tp_rtx (void);
+static rtx mep_gp_rtx (void);
+static bool mep_interrupt_p (void);
+static bool mep_disinterrupt_p (void);
+static bool mep_reg_set_p (rtx, rtx);
+static bool mep_reg_set_in_function (int);
+static bool mep_interrupt_saved_reg (int);
+static bool mep_call_saves_register (int);
+static rtx F (rtx);
+static void add_constant (int, int, int, int);
+static bool mep_function_uses_sp (void);
+static rtx maybe_dead_move (rtx, rtx, bool);
+static void mep_reload_pointer (int, const char *);
+static void mep_start_function (FILE *, HOST_WIDE_INT);
+static bool mep_function_ok_for_sibcall (tree, tree);
+static int unique_bit_in (HOST_WIDE_INT);
+static int bit_size_for_clip (HOST_WIDE_INT);
+static int bytesize (const_tree, enum machine_mode);
+static tree mep_validate_based_tiny (tree *, tree, tree, int, bool *);
+static tree mep_validate_near_far (tree *, tree, tree, int, bool *);
+static tree mep_validate_disinterrupt (tree *, tree, tree, int, bool *);
+static tree mep_validate_interrupt (tree *, tree, tree, int, bool *);
+static tree mep_validate_io_cb (tree *, tree, tree, int, bool *);
+static tree mep_validate_vliw (tree *, tree, tree, int, bool *);
+static bool mep_function_attribute_inlinable_p (const_tree);
+static bool mep_lookup_pragma_disinterrupt (const char *);
+static int mep_multiple_address_regions (tree, bool);
+static int mep_attrlist_to_encoding (tree, tree);
+static void mep_insert_attributes (tree, tree *);
+static void mep_encode_section_info (tree, rtx, int);
+static section * mep_select_section (tree, int, unsigned HOST_WIDE_INT);
+static void mep_unique_section (tree, int);
+static unsigned int mep_section_type_flags (tree, const char *, int);
+static void mep_asm_named_section (const char *, unsigned int, tree);
+static bool mep_mentioned_p (rtx, rtx, int);
+static void mep_reorg_regmove (rtx);
+static rtx mep_insert_repeat_label_last (rtx, rtx, bool, bool);
+static void mep_reorg_repeat (rtx);
+static bool mep_invertable_branch_p (rtx);
+static void mep_invert_branch (rtx, rtx);
+static void mep_reorg_erepeat (rtx);
+static void mep_jmp_return_reorg (rtx);
+static void mep_reorg_addcombine (rtx);
+static void mep_reorg (void);
+static void mep_init_intrinsics (void);
+static void mep_init_builtins (void);
+static void mep_intrinsic_unavailable (int);
+static bool mep_get_intrinsic_insn (int, const struct cgen_insn **);
+static bool mep_get_move_insn (int, const struct cgen_insn **);
+static rtx mep_convert_arg (enum machine_mode, rtx);
+static rtx mep_convert_regnum (const struct cgen_regnum_operand *, rtx);
+static rtx mep_legitimize_arg (const struct insn_operand_data *, rtx, int);
+static void mep_incompatible_arg (const struct insn_operand_data *, rtx, int, tree);
+static rtx mep_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
+static int mep_adjust_cost (rtx, rtx, rtx, int);
+static int mep_issue_rate (void);
+static rtx mep_find_ready_insn (rtx *, int, enum attr_slot, int);
+static void mep_move_ready_insn (rtx *, int, rtx);
+static int mep_sched_reorder (FILE *, int, rtx *, int *, int);
+static rtx mep_make_bundle (rtx, rtx);
+static void mep_bundle_insns (rtx);
+static bool mep_rtx_cost (rtx, int, int, int *, bool);
+static int mep_address_cost (rtx, bool);
+static void mep_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
+ tree, int *, int);
+static bool mep_pass_by_reference (CUMULATIVE_ARGS * cum, enum machine_mode,
+ const_tree, bool);
+static bool mep_vector_mode_supported_p (enum machine_mode);
+static bool mep_handle_option (size_t, const char *, int);
+static rtx mep_allocate_initial_value (rtx);
+static void mep_asm_init_sections (void);
+static int mep_comp_type_attributes (const_tree, const_tree);
+static bool mep_narrow_volatile_bitfield (void);
+static rtx mep_expand_builtin_saveregs (void);
+static tree mep_build_builtin_va_list (void);
+static void mep_expand_va_start (tree, rtx);
+static tree mep_gimplify_va_arg_expr (tree, tree, tree *, tree *);
+\f
+/* Initialize the GCC target structure. */
+
+#undef TARGET_ASM_FUNCTION_PROLOGUE
+#define TARGET_ASM_FUNCTION_PROLOGUE mep_start_function
+#undef TARGET_ATTRIBUTE_TABLE
+#define TARGET_ATTRIBUTE_TABLE mep_attribute_table
+#undef TARGET_COMP_TYPE_ATTRIBUTES
+#define TARGET_COMP_TYPE_ATTRIBUTES mep_comp_type_attributes
+#undef TARGET_INSERT_ATTRIBUTES
+#define TARGET_INSERT_ATTRIBUTES mep_insert_attributes
+#undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
+#define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P mep_function_attribute_inlinable_p
+#undef TARGET_SECTION_TYPE_FLAGS
+#define TARGET_SECTION_TYPE_FLAGS mep_section_type_flags
+#undef TARGET_ASM_NAMED_SECTION
+#define TARGET_ASM_NAMED_SECTION mep_asm_named_section
+#undef TARGET_INIT_BUILTINS
+#define TARGET_INIT_BUILTINS mep_init_builtins
+#undef TARGET_EXPAND_BUILTIN
+#define TARGET_EXPAND_BUILTIN mep_expand_builtin
+#undef TARGET_SCHED_ADJUST_COST
+#define TARGET_SCHED_ADJUST_COST mep_adjust_cost
+#undef TARGET_SCHED_ISSUE_RATE
+#define TARGET_SCHED_ISSUE_RATE mep_issue_rate
+#undef TARGET_SCHED_REORDER
+#define TARGET_SCHED_REORDER mep_sched_reorder
+#undef TARGET_STRIP_NAME_ENCODING
+#define TARGET_STRIP_NAME_ENCODING mep_strip_name_encoding
+#undef TARGET_ASM_SELECT_SECTION
+#define TARGET_ASM_SELECT_SECTION mep_select_section
+#undef TARGET_ASM_UNIQUE_SECTION
+#define TARGET_ASM_UNIQUE_SECTION mep_unique_section
+#undef TARGET_ENCODE_SECTION_INFO
+#define TARGET_ENCODE_SECTION_INFO mep_encode_section_info
+#undef TARGET_FUNCTION_OK_FOR_SIBCALL
+#define TARGET_FUNCTION_OK_FOR_SIBCALL mep_function_ok_for_sibcall
+#undef TARGET_RTX_COSTS
+#define TARGET_RTX_COSTS mep_rtx_cost
+#undef TARGET_ADDRESS_COST
+#define TARGET_ADDRESS_COST mep_address_cost
+#undef TARGET_MACHINE_DEPENDENT_REORG
+#define TARGET_MACHINE_DEPENDENT_REORG mep_reorg
+#undef TARGET_SETUP_INCOMING_VARARGS
+#define TARGET_SETUP_INCOMING_VARARGS mep_setup_incoming_varargs
+#undef TARGET_PASS_BY_REFERENCE
+#define TARGET_PASS_BY_REFERENCE mep_pass_by_reference
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
+#define TARGET_VECTOR_MODE_SUPPORTED_P mep_vector_mode_supported_p
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION mep_handle_option
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
+#undef TARGET_ALLOCATE_INITIAL_VALUE
+#define TARGET_ALLOCATE_INITIAL_VALUE mep_allocate_initial_value
+#undef TARGET_ASM_INIT_SECTIONS
+#define TARGET_ASM_INIT_SECTIONS mep_asm_init_sections
+#undef TARGET_RETURN_IN_MEMORY
+#define TARGET_RETURN_IN_MEMORY mep_return_in_memory
+#undef TARGET_NARROW_VOLATILE_BITFIELD
+#define TARGET_NARROW_VOLATILE_BITFIELD mep_narrow_volatile_bitfield
+#undef TARGET_EXPAND_BUILTIN_SAVEREGS
+#define TARGET_EXPAND_BUILTIN_SAVEREGS mep_expand_builtin_saveregs
+#undef TARGET_BUILD_BUILTIN_VA_LIST
+#define TARGET_BUILD_BUILTIN_VA_LIST mep_build_builtin_va_list
+#undef TARGET_EXPAND_BUILTIN_VA_START
+#define TARGET_EXPAND_BUILTIN_VA_START mep_expand_va_start
+#undef TARGET_GIMPLIFY_VA_ARG_EXPR
+#define TARGET_GIMPLIFY_VA_ARG_EXPR mep_gimplify_va_arg_expr
+
+struct gcc_target targetm = TARGET_INITIALIZER;
+\f
+#define WANT_GCC_DEFINITIONS
+#include "mep-intrin.h"
+#undef WANT_GCC_DEFINITIONS
+
+\f
+/* Command Line Option Support. */
+
+char mep_leaf_registers [FIRST_PSEUDO_REGISTER];
+
+/* True if we can use cmov instructions to move values back and forth
+ between core and coprocessor registers. */
+bool mep_have_core_copro_moves_p;
+
+/* True if we can use cmov instructions (or a work-alike) to move
+ values between coprocessor registers. */
+bool mep_have_copro_copro_moves_p;
+
+/* A table of all coprocessor instructions that can act like
+ a coprocessor-to-coprocessor cmov. */
+static const int mep_cmov_insns[] = {
+ mep_cmov,
+ mep_cpmov,
+ mep_fmovs,
+ mep_caddi3,
+ mep_csubi3,
+ mep_candi3,
+ mep_cori3,
+ mep_cxori3,
+ mep_cand3,
+ mep_cor3
+};
+
+static int option_mtiny_specified = 0;
+
+\f
+static void
+mep_set_leaf_registers (int enable)
+{
+ int i;
+
+ if (mep_leaf_registers[0] != enable)
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+ mep_leaf_registers[i] = enable;
+}
+
+void
+mep_conditional_register_usage (char *fixed_regs, char *call_used_regs)
+{
+ int i;
+
+ if (!TARGET_OPT_MULT && !TARGET_OPT_DIV)
+ {
+ fixed_regs[HI_REGNO] = 1;
+ fixed_regs[LO_REGNO] = 1;
+ call_used_regs[HI_REGNO] = 1;
+ call_used_regs[LO_REGNO] = 1;
+ }
+
+ for (i = FIRST_SHADOW_REGISTER; i <= LAST_SHADOW_REGISTER; i++)
+ global_regs[i] = 1;
+}
+
+void
+mep_optimization_options (void)
+{
+ /* The first scheduling pass often increases register pressure and tends
+ to result in more spill code. Only run it when specifically asked. */
+ flag_schedule_insns = 0;
+
+ /* Using $fp doesn't gain us much, even when debugging is important. */
+ flag_omit_frame_pointer = 1;
+}
+
+void
+mep_override_options (void)
+{
+ if (flag_pic == 1)
+ warning (OPT_fpic, "-fpic is not supported");
+ if (flag_pic == 2)
+ warning (OPT_fPIC, "-fPIC is not supported");
+ if (TARGET_S && TARGET_M)
+ error ("only one of -ms and -mm may be given");
+ if (TARGET_S && TARGET_L)
+ error ("only one of -ms and -ml may be given");
+ if (TARGET_M && TARGET_L)
+ error ("only one of -mm and -ml may be given");
+ if (TARGET_S && option_mtiny_specified)
+ error ("only one of -ms and -mtiny= may be given");
+ if (TARGET_M && option_mtiny_specified)
+ error ("only one of -mm and -mtiny= may be given");
+ if (TARGET_OPT_CLIP && ! TARGET_OPT_MINMAX)
+ warning (0, "-mclip currently has no effect without -mminmax");
+
+ if (mep_const_section)
+ {
+ if (strcmp (mep_const_section, "tiny") != 0
+ && strcmp (mep_const_section, "near") != 0
+ && strcmp (mep_const_section, "far") != 0)
+ error ("-mc= must be -mc=tiny, -mc=near, or -mc=far");
+ }
+
+ if (TARGET_S)
+ mep_tiny_cutoff = 65536;
+ if (TARGET_M)
+ mep_tiny_cutoff = 0;
+ if (TARGET_L && ! option_mtiny_specified)
+ mep_tiny_cutoff = 0;
+
+ if (TARGET_64BIT_CR_REGS)
+ flag_split_wide_types = 0;
+
+ init_machine_status = mep_init_machine_status;
+ mep_init_intrinsics ();
+}
+
+/* Pattern Support - constraints, predicates, expanders. */
+
+/* MEP has very few instructions that can refer to the span of
+ addresses used by symbols, so it's common to check for them. */
+
+static bool
+symbol_p (rtx x)
+{
+ int c = GET_CODE (x);
+
+ return (c == CONST_INT
+ || c == CONST
+ || c == SYMBOL_REF);
+}
+
+static bool
+symbolref_p (rtx x)
+{
+ int c;
+
+ if (GET_CODE (x) != MEM)
+ return false;
+
+ c = GET_CODE (XEXP (x, 0));
+ return (c == CONST_INT
+ || c == CONST
+ || c == SYMBOL_REF);
+}
+
+/* static const char *reg_class_names[] = REG_CLASS_NAMES; */
+
+#define GEN_REG(R, STRICT) \
+ (GR_REGNO_P (R) \
+ || (!STRICT \
+ && ((R) == ARG_POINTER_REGNUM \
+ || (R) >= FIRST_PSEUDO_REGISTER)))
+
+static char pattern[12], *patternp;
+static GTY(()) rtx patternr[12];
+#define RTX_IS(x) (strcmp (pattern, x) == 0)
+
+static void
+encode_pattern_1 (rtx x)
+{
+ int i;
+
+ if (patternp == pattern + sizeof (pattern) - 2)
+ {
+ patternp[-1] = '?';
+ return;
+ }
+
+ patternr[patternp-pattern] = x;
+
+ switch (GET_CODE (x))
+ {
+ case REG:
+ *patternp++ = 'r';
+ break;
+ case MEM:
+ *patternp++ = 'm';
+ case CONST:
+ encode_pattern_1 (XEXP(x, 0));
+ break;
+ case PLUS:
+ *patternp++ = '+';
+ encode_pattern_1 (XEXP(x, 0));
+ encode_pattern_1 (XEXP(x, 1));
+ break;
+ case LO_SUM:
+ *patternp++ = 'L';
+ encode_pattern_1 (XEXP(x, 0));
+ encode_pattern_1 (XEXP(x, 1));
+ break;
+ case HIGH:
+ *patternp++ = 'H';
+ encode_pattern_1 (XEXP(x, 0));
+ break;
+ case SYMBOL_REF:
+ *patternp++ = 's';
+ break;
+ case LABEL_REF:
+ *patternp++ = 'l';
+ break;
+ case CONST_INT:
+ case CONST_DOUBLE:
+ *patternp++ = 'i';
+ break;
+ case UNSPEC:
+ *patternp++ = 'u';
+ *patternp++ = '0' + XCINT(x, 1, UNSPEC);
+ for (i=0; i<XVECLEN (x, 0); i++)
+ encode_pattern_1 (XVECEXP (x, 0, i));
+ break;
+ case USE:
+ *patternp++ = 'U';
+ break;
+ default:
+ *patternp++ = '?';
+#if 0
+ fprintf (stderr, "can't encode pattern %s\n", GET_RTX_NAME(GET_CODE(x)));
+ debug_rtx (x);
+ gcc_unreachable ();
+#endif
+ break;
+ }
+}
+
+static void
+encode_pattern (rtx x)
+{
+ patternp = pattern;
+ encode_pattern_1 (x);
+ *patternp = 0;
+}
+
+int
+mep_section_tag (rtx x)
+{
+ const char *name;
+
+ while (1)
+ {
+ switch (GET_CODE (x))
+ {
+ case MEM:
+ case CONST:
+ x = XEXP (x, 0);
+ break;
+ case UNSPEC:
+ x = XVECEXP (x, 0, 0);
+ break;
+ case PLUS:
+ if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+ return 0;
+ x = XEXP (x, 0);
+ break;
+ default:
+ goto done;
+ }
+ }
+ done:
+ if (GET_CODE (x) != SYMBOL_REF)
+ return 0;
+ name = XSTR (x, 0);
+ if (name[0] == '@' && name[2] == '.')
+ {
+ if (name[1] == 'i' || name[1] == 'I')
+ {
+ if (name[1] == 'I')
+ return 'f'; /* near */
+ return 'n'; /* far */
+ }
+ return name[1];
+ }
+ return 0;
+}
+
+int
+mep_regno_reg_class (int regno)
+{
+ switch (regno)
+ {
+ case SP_REGNO: return SP_REGS;
+ case TP_REGNO: return TP_REGS;
+ case GP_REGNO: return GP_REGS;
+ case 0: return R0_REGS;
+ case HI_REGNO: return HI_REGS;
+ case LO_REGNO: return LO_REGS;
+ case ARG_POINTER_REGNUM: return GENERAL_REGS;
+ }
+
+ if (GR_REGNO_P (regno))
+ return regno < FIRST_GR_REGNO + 8 ? TPREL_REGS : GENERAL_REGS;
+ if (CONTROL_REGNO_P (regno))
+ return CONTROL_REGS;
+
+ if (CR_REGNO_P (regno))
+ {
+ int i, j;
+
+ /* Search for the register amongst user-defined subclasses of
+ the coprocessor registers. */
+ for (i = USER0_REGS; i <= USER3_REGS; ++i)
+ {
+ if (! TEST_HARD_REG_BIT (reg_class_contents[i], regno))
+ continue;
+ for (j = 0; j < N_REG_CLASSES; ++j)
+ {
+ enum reg_class sub = reg_class_subclasses[i][j];
+
+ if (sub == LIM_REG_CLASSES)
+ return i;
+ if (TEST_HARD_REG_BIT (reg_class_contents[sub], regno))
+ break;
+ }
+ }
+
+ return LOADABLE_CR_REGNO_P (regno) ? LOADABLE_CR_REGS : CR_REGS;
+ }
+
+ if (CCR_REGNO_P (regno))
+ return CCR_REGS;
+
+ gcc_assert (regno >= FIRST_SHADOW_REGISTER && regno <= LAST_SHADOW_REGISTER);
+ return NO_REGS;
+}
+
+#if 0
+int
+mep_reg_class_from_constraint (int c, const char *str)
+{
+ switch (c)
+ {
+ case 'a':
+ return SP_REGS;
+ case 'b':
+ return TP_REGS;
+ case 'c':
+ return CONTROL_REGS;
+ case 'd':
+ return HILO_REGS;
+ case 'e':
+ {
+ switch (str[1])
+ {
+ case 'm':
+ return LOADABLE_CR_REGS;
+ case 'x':
+ return mep_have_copro_copro_moves_p ? CR_REGS : NO_REGS;
+ case 'r':
+ return mep_have_core_copro_moves_p ? CR_REGS : NO_REGS;
+ default:
+ return NO_REGS;
+ }
+ }
+ case 'h':
+ return HI_REGS;
+ case 'j':
+ return RPC_REGS;
+ case 'l':
+ return LO_REGS;
+ case 't':
+ return TPREL_REGS;
+ case 'v':
+ return GP_REGS;
+ case 'x':
+ return CR_REGS;
+ case 'y':
+ return CCR_REGS;
+ case 'z':
+ return R0_REGS;
+
+ case 'A':
+ case 'B':
+ case 'C':
+ case 'D':
+ {
+ enum reg_class which = c - 'A' + USER0_REGS;
+ return (reg_class_size[which] > 0 ? which : NO_REGS);
+ }
+
+ default:
+ return NO_REGS;
+ }
+}
+
+bool
+mep_const_ok_for_letter_p (HOST_WIDE_INT value, int c)
+{
+ switch (c)
+ {
+ case 'I': return value >= -32768 && value < 32768;
+ case 'J': return value >= 0 && value < 65536;
+ case 'K': return value >= 0 && value < 0x01000000;
+ case 'L': return value >= -32 && value < 32;
+ case 'M': return value >= 0 && value < 32;
+ case 'N': return value >= 0 && value < 16;
+ case 'O':
+ if (value & 0xffff)
+ return false;
+ return value >= -2147483647-1 && value <= 2147483647;
+ default:
+ gcc_unreachable ();
+ }
+}
+
+bool
+mep_extra_constraint (rtx value, int c)
+{
+ encode_pattern (value);
+
+ switch (c)
+ {
+ case 'R':
+ /* For near symbols, like what call uses. */
+ if (GET_CODE (value) == REG)
+ return 0;
+ return mep_call_address_operand (value, GET_MODE (value));
+
+ case 'S':
+ /* For signed 8-bit immediates. */
+ return (GET_CODE (value) == CONST_INT
+ && INTVAL (value) >= -128
+ && INTVAL (value) <= 127);
+
+ case 'T':
+ /* For tp/gp relative symbol values. */
+ return (RTX_IS ("u3s") || RTX_IS ("u2s")
+ || RTX_IS ("+u3si") || RTX_IS ("+u2si"));
+
+ case 'U':
+ /* Non-absolute memories. */
+ return GET_CODE (value) == MEM && ! CONSTANT_P (XEXP (value, 0));
+
+ case 'W':
+ /* %hi(sym) */
+ return RTX_IS ("Hs");
+
+ case 'Y':
+ /* Register indirect. */
+ return RTX_IS ("mr");
+
+ case 'Z':
+ return mep_section_tag (value) == 'c' && RTX_IS ("ms");
+ }
+
+ return false;
+}
+#endif
+
+#undef PASS
+#undef FAIL
+
+static bool
+const_in_range (rtx x, int minv, int maxv)
+{
+ return (GET_CODE (x) == CONST_INT
+ && INTVAL (x) >= minv
+ && INTVAL (x) <= maxv);
+}
+
+/* Given three integer registers DEST, SRC1 and SRC2, return an rtx X
+ such that "mulr DEST,X" will calculate DEST = SRC1 * SRC2. If a move
+ is needed, emit it before INSN if INSN is nonnull, otherwise emit it
+ at the end of the insn stream. */
+
+rtx
+mep_mulr_source (rtx insn, rtx dest, rtx src1, rtx src2)
+{
+ if (rtx_equal_p (dest, src1))
+ return src2;
+ else if (rtx_equal_p (dest, src2))
+ return src1;
+ else
+ {
+ if (insn == 0)
+ emit_insn (gen_movsi (copy_rtx (dest), src1));
+ else
+ emit_insn_before (gen_movsi (copy_rtx (dest), src1), insn);
+ return src2;
+ }
+}
+
+/* Replace INSN's pattern with PATTERN, a multiplication PARALLEL.
+ Change the last element of PATTERN from (clobber (scratch:SI))
+ to (clobber (reg:SI HI_REGNO)). */
+
+static void
+mep_rewrite_mult (rtx insn, rtx pattern)
+{
+ rtx hi_clobber;
+
+ hi_clobber = XVECEXP (pattern, 0, XVECLEN (pattern, 0) - 1);
+ XEXP (hi_clobber, 0) = gen_rtx_REG (SImode, HI_REGNO);
+ PATTERN (insn) = pattern;
+ INSN_CODE (insn) = -1;
+}
+
+/* Subroutine of mep_reuse_lo_p. Rewrite instruction INSN so that it
+ calculates SRC1 * SRC2 and stores the result in $lo. Also make it
+ store the result in DEST if nonnull. */
+
+static void
+mep_rewrite_mulsi3 (rtx insn, rtx dest, rtx src1, rtx src2)
+{
+ rtx lo, pattern;
+
+ lo = gen_rtx_REG (SImode, LO_REGNO);
+ if (dest)
+ pattern = gen_mulsi3r (lo, dest, copy_rtx (dest),
+ mep_mulr_source (insn, dest, src1, src2));
+ else
+ pattern = gen_mulsi3_lo (lo, src1, src2);
+ mep_rewrite_mult (insn, pattern);
+}
+
+/* Like mep_rewrite_mulsi3, but calculate SRC1 * SRC2 + SRC3. First copy
+ SRC3 into $lo, then use either madd or maddr. The move into $lo will
+ be deleted by a peephole2 if SRC3 is already in $lo. */
+
+static void
+mep_rewrite_maddsi3 (rtx insn, rtx dest, rtx src1, rtx src2, rtx src3)
+{
+ rtx lo, pattern;
+
+ lo = gen_rtx_REG (SImode, LO_REGNO);
+ emit_insn_before (gen_movsi (copy_rtx (lo), src3), insn);
+ if (dest)
+ pattern = gen_maddsi3r (lo, dest, copy_rtx (dest),
+ mep_mulr_source (insn, dest, src1, src2),
+ copy_rtx (lo));
+ else
+ pattern = gen_maddsi3_lo (lo, src1, src2, copy_rtx (lo));
+ mep_rewrite_mult (insn, pattern);
+}
+
+/* Return true if $lo has the same value as integer register GPR when
+ instruction INSN is reached. If necessary, rewrite the instruction
+ that sets $lo so that it uses a proper SET, not a CLOBBER. LO is an
+ rtx for (reg:SI LO_REGNO).
+
+ This function is intended to be used by the peephole2 pass. Since
+ that pass goes from the end of a basic block to the beginning, and
+ propagates liveness information on the way, there is no need to
+ update register notes here.
+
+ If GPR_DEAD_P is true on entry, and this function returns true,
+ then the caller will replace _every_ use of GPR in and after INSN
+ with LO. This means that if the instruction that sets $lo is a
+ mulr- or maddr-type instruction, we can rewrite it to use mul or
+ madd instead. In combination with the copy progagation pass,
+ this allows us to replace sequences like:
+
+ mov GPR,R1
+ mulr GPR,R2
+
+ with:
+
+ mul R1,R2
+
+ if GPR is no longer used. */
+
+static bool
+mep_reuse_lo_p_1 (rtx lo, rtx gpr, rtx insn, bool gpr_dead_p)
+{
+ do
+ {
+ insn = PREV_INSN (insn);
+ if (INSN_P (insn))
+ switch (recog_memoized (insn))
+ {
+ case CODE_FOR_mulsi3_1:
+ extract_insn (insn);
+ if (rtx_equal_p (recog_data.operand[0], gpr))
+ {
+ mep_rewrite_mulsi3 (insn,
+ gpr_dead_p ? NULL : recog_data.operand[0],
+ recog_data.operand[1],
+ recog_data.operand[2]);
+ return true;
+ }
+ return false;
+
+ case CODE_FOR_maddsi3:
+ extract_insn (insn);
+ if (rtx_equal_p (recog_data.operand[0], gpr))
+ {
+ mep_rewrite_maddsi3 (insn,
+ gpr_dead_p ? NULL : recog_data.operand[0],
+ recog_data.operand[1],
+ recog_data.operand[2],
+ recog_data.operand[3]);
+ return true;
+ }
+ return false;
+
+ case CODE_FOR_mulsi3r:
+ case CODE_FOR_maddsi3r:
+ extract_insn (insn);
+ return rtx_equal_p (recog_data.operand[1], gpr);
+
+ default:
+ if (reg_set_p (lo, insn)
+ || reg_set_p (gpr, insn)
+ || volatile_insn_p (PATTERN (insn)))
+ return false;
+
+ if (gpr_dead_p && reg_referenced_p (gpr, PATTERN (insn)))
+ gpr_dead_p = false;
+ break;
+ }
+ }
+ while (!NOTE_INSN_BASIC_BLOCK_P (insn));
+ return false;
+}
+
+/* A wrapper around mep_reuse_lo_p_1 that preserves recog_data. */
+
+bool
+mep_reuse_lo_p (rtx lo, rtx gpr, rtx insn, bool gpr_dead_p)
+{
+ bool result = mep_reuse_lo_p_1 (lo, gpr, insn, gpr_dead_p);
+ extract_insn (insn);
+ return result;
+}
+
+/* Return true if SET can be turned into a post-modify load or store
+ that adds OFFSET to GPR. In other words, return true if SET can be
+ changed into:
+
+ (parallel [SET (set GPR (plus:SI GPR OFFSET))]).
+
+ It's OK to change SET to an equivalent operation in order to
+ make it match. */
+
+static bool
+mep_use_post_modify_for_set_p (rtx set, rtx gpr, rtx offset)
+{
+ rtx *reg, *mem;
+ unsigned int reg_bytes, mem_bytes;
+ enum machine_mode reg_mode, mem_mode;
+
+ /* Only simple SETs can be converted. */
+ if (GET_CODE (set) != SET)
+ return false;
+
+ /* Point REG to what we hope will be the register side of the set and
+ MEM to what we hope will be the memory side. */
+ if (GET_CODE (SET_DEST (set)) == MEM)
+ {
+ mem = &SET_DEST (set);
+ reg = &SET_SRC (set);
+ }
+ else
+ {
+ reg = &SET_DEST (set);
+ mem = &SET_SRC (set);
+ if (GET_CODE (*mem) == SIGN_EXTEND)
+ mem = &XEXP (*mem, 0);
+ }
+
+ /* Check that *REG is a suitable coprocessor register. */
+ if (GET_CODE (*reg) != REG || !LOADABLE_CR_REGNO_P (REGNO (*reg)))
+ return false;
+
+ /* Check that *MEM is a suitable memory reference. */
+ if (GET_CODE (*mem) != MEM || !rtx_equal_p (XEXP (*mem, 0), gpr))
+ return false;
+
+ /* Get the number of bytes in each operand. */
+ mem_bytes = GET_MODE_SIZE (GET_MODE (*mem));
+ reg_bytes = GET_MODE_SIZE (GET_MODE (*reg));
+
+ /* Check that OFFSET is suitably aligned. */
+ if (INTVAL (offset) & (mem_bytes - 1))
+ return false;
+
+ /* Convert *MEM to a normal integer mode. */
+ mem_mode = mode_for_size (mem_bytes * BITS_PER_UNIT, MODE_INT, 0);
+ *mem = change_address (*mem, mem_mode, NULL);
+
+ /* Adjust *REG as well. */
+ *reg = shallow_copy_rtx (*reg);
+ if (reg == &SET_DEST (set) && reg_bytes < UNITS_PER_WORD)
+ {
+ /* SET is a subword load. Convert it to an explicit extension. */
+ PUT_MODE (*reg, SImode);
+ *mem = gen_rtx_SIGN_EXTEND (SImode, *mem);
+ }
+ else
+ {
+ reg_mode = mode_for_size (reg_bytes * BITS_PER_UNIT, MODE_INT, 0);
+ PUT_MODE (*reg, reg_mode);
+ }
+ return true;
+}
+
+/* Return the effect of frame-related instruction INSN. */
+
+static rtx
+mep_frame_expr (rtx insn)
+{
+ rtx note, expr;
+
+ note = find_reg_note (insn, REG_FRAME_RELATED_EXPR, 0);
+ expr = (note != 0 ? XEXP (note, 0) : copy_rtx (PATTERN (insn)));
+ RTX_FRAME_RELATED_P (expr) = 1;
+ return expr;
+}
+
+/* Merge instructions INSN1 and INSN2 using a PARALLEL. Store the
+ new pattern in INSN1; INSN2 will be deleted by the caller. */
+
+static void
+mep_make_parallel (rtx insn1, rtx insn2)
+{
+ rtx expr;
+
+ if (RTX_FRAME_RELATED_P (insn2))
+ {
+ expr = mep_frame_expr (insn2);
+ if (RTX_FRAME_RELATED_P (insn1))
+ expr = gen_rtx_SEQUENCE (VOIDmode,
+ gen_rtvec (2, mep_frame_expr (insn1), expr));
+ set_unique_reg_note (insn1, REG_FRAME_RELATED_EXPR, expr);
+ RTX_FRAME_RELATED_P (insn1) = 1;
+ }
+
+ PATTERN (insn1) = gen_rtx_PARALLEL (VOIDmode,
+ gen_rtvec (2, PATTERN (insn1),
+ PATTERN (insn2)));
+ INSN_CODE (insn1) = -1;
+}
+
+/* SET_INSN is an instruction that adds OFFSET to REG. Go back through
+ the basic block to see if any previous load or store instruction can
+ be persuaded to do SET_INSN as a side-effect. Return true if so. */
+
+static bool
+mep_use_post_modify_p_1 (rtx set_insn, rtx reg, rtx offset)
+{
+ rtx insn;
+
+ insn = set_insn;
+ do
+ {
+ insn = PREV_INSN (insn);
+ if (INSN_P (insn))
+ {
+ if (mep_use_post_modify_for_set_p (PATTERN (insn), reg, offset))
+ {
+ mep_make_parallel (insn, set_insn);
+ return true;
+ }
+
+ if (reg_set_p (reg, insn)
+ || reg_referenced_p (reg, PATTERN (insn))
+ || volatile_insn_p (PATTERN (insn)))
+ return false;
+ }
+ }
+ while (!NOTE_INSN_BASIC_BLOCK_P (insn));
+ return false;
+}
+
+/* A wrapper around mep_use_post_modify_p_1 that preserves recog_data. */
+
+bool
+mep_use_post_modify_p (rtx insn, rtx reg, rtx offset)
+{
+ bool result = mep_use_post_modify_p_1 (insn, reg, offset);
+ extract_insn (insn);
+ return result;
+}
+
+bool
+mep_allow_clip (rtx ux, rtx lx, int s)
+{
+ HOST_WIDE_INT u = INTVAL (ux);
+ HOST_WIDE_INT l = INTVAL (lx);
+ int i;
+
+ if (!TARGET_OPT_CLIP)
+ return false;
+
+ if (s)
+ {
+ for (i = 0; i < 30; i ++)
+ if ((u == ((HOST_WIDE_INT) 1 << i) - 1)
+ && (l == - ((HOST_WIDE_INT) 1 << i)))
+ return true;
+ }
+ else
+ {
+ if (l != 0)
+ return false;
+
+ for (i = 0; i < 30; i ++)
+ if ((u == ((HOST_WIDE_INT) 1 << i) - 1))
+ return true;
+ }
+ return false;
+}
+
+bool
+mep_bit_position_p (rtx x, bool looking_for)
+{
+ if (GET_CODE (x) != CONST_INT)
+ return false;
+ switch ((int) INTVAL(x) & 0xff)
+ {
+ case 0x01: case 0x02: case 0x04: case 0x08:
+ case 0x10: case 0x20: case 0x40: case 0x80:
+ return looking_for;
+ case 0xfe: case 0xfd: case 0xfb: case 0xf7:
+ case 0xef: case 0xdf: case 0xbf: case 0x7f:
+ return !looking_for;
+ }
+ return false;
+}
+
+static bool
+move_needs_splitting (rtx dest, rtx src,
+ enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ int s = mep_section_tag (src);
+
+ while (1)
+ {
+ if (GET_CODE (src) == CONST
+ || GET_CODE (src) == MEM)
+ src = XEXP (src, 0);
+ else if (GET_CODE (src) == SYMBOL_REF
+ || GET_CODE (src) == LABEL_REF
+ || GET_CODE (src) == PLUS)
+ break;
+ else
+ return false;
+ }
+ if (s == 'f'
+ || (GET_CODE (src) == PLUS
+ && GET_CODE (XEXP (src, 1)) == CONST_INT
+ && (INTVAL (XEXP (src, 1)) < -65536
+ || INTVAL (XEXP (src, 1)) > 0xffffff))
+ || (GET_CODE (dest) == REG
+ && REGNO (dest) > 7 && REGNO (dest) < FIRST_PSEUDO_REGISTER))
+ return true;
+ return false;
+}
+
+bool
+mep_split_mov (rtx *operands, int symbolic)
+{
+ if (symbolic)
+ {
+ if (move_needs_splitting (operands[0], operands[1], SImode))
+ return true;
+ return false;
+ }
+
+ if (GET_CODE (operands[1]) != CONST_INT)
+ return false;
+
+ if (constraint_satisfied_p (operands[1], CONSTRAINT_I)
+ || constraint_satisfied_p (operands[1], CONSTRAINT_J)
+ || constraint_satisfied_p (operands[1], CONSTRAINT_O))
+ return false;
+
+ if (((!reload_completed && !reload_in_progress)
+ || (REG_P (operands[0]) && REGNO (operands[0]) < 8))
+ && constraint_satisfied_p (operands[1], CONSTRAINT_K))
+ return false;
+
+ return true;
+}
+
+/* Irritatingly, the "jsrv" insn *toggles* PSW.OM rather than set
+ it to one specific value. So the insn chosen depends on whether
+ the source and destination modes match. */
+
+bool
+mep_vliw_mode_match (rtx tgt)
+{
+ bool src_vliw = mep_vliw_function_p (cfun->decl);
+ bool tgt_vliw = INTVAL (tgt);
+
+ return src_vliw == tgt_vliw;
+}
+
+bool
+mep_multi_slot (rtx x)
+{
+ return get_attr_slot (x) == SLOT_MULTI;
+}
+
+
+/* Be careful not to use macros that need to be compiled one way for
+ strict, and another way for not-strict, like REG_OK_FOR_BASE_P. */
+
+bool
+mep_legitimate_address (enum machine_mode mode, rtx x, int strict)
+{
+ int the_tag;
+
+#define DEBUG_LEGIT 0
+#if DEBUG_LEGIT
+ fprintf (stderr, "legit: mode %s strict %d ", mode_name[mode], strict);
+ debug_rtx (x);
+#endif
+
+ if (GET_CODE (x) == LO_SUM
+ && GET_CODE (XEXP (x, 0)) == REG
+ && GEN_REG (REGNO (XEXP (x, 0)), strict)
+ && CONSTANT_P (XEXP (x, 1)))
+ {
+ if (GET_MODE_SIZE (mode) > 4)
+ {
+ /* We will end up splitting this, and lo_sums are not
+ offsettable for us. */
+#if DEBUG_LEGIT
+ fprintf(stderr, " - nope, %%lo(sym)[reg] not splittable\n");
+#endif
+ return false;
+ }
+#if DEBUG_LEGIT
+ fprintf (stderr, " - yup, %%lo(sym)[reg]\n");
+#endif
+ return true;
+ }
+
+ if (GET_CODE (x) == REG
+ && GEN_REG (REGNO (x), strict))
+ {
+#if DEBUG_LEGIT
+ fprintf (stderr, " - yup, [reg]\n");
+#endif
+ return true;
+ }
+
+ if (GET_CODE (x) == PLUS
+ && GET_CODE (XEXP (x, 0)) == REG
+ && GEN_REG (REGNO (XEXP (x, 0)), strict)
+ && const_in_range (XEXP (x, 1), -32768, 32767))
+ {
+#if DEBUG_LEGIT
+ fprintf (stderr, " - yup, [reg+const]\n");
+#endif
+ return true;
+ }
+
+ if (GET_CODE (x) == PLUS
+ && GET_CODE (XEXP (x, 0)) == REG
+ && GEN_REG (REGNO (XEXP (x, 0)), strict)
+ && GET_CODE (XEXP (x, 1)) == CONST
+ && (GET_CODE (XEXP (XEXP (x, 1), 0)) == UNSPEC
+ || (GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == UNSPEC
+ && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == CONST_INT)))
+ {
+#if DEBUG_LEGIT
+ fprintf (stderr, " - yup, [reg+unspec]\n");
+#endif
+ return true;
+ }
+
+ the_tag = mep_section_tag (x);
+
+ if (the_tag == 'f')
+ {
+#if DEBUG_LEGIT
+ fprintf (stderr, " - nope, [far]\n");
+#endif
+ return false;
+ }
+
+ if (mode == VOIDmode
+ && GET_CODE (x) == SYMBOL_REF)
+ {
+#if DEBUG_LEGIT
+ fprintf (stderr, " - yup, call [symbol]\n");
+#endif
+ return true;
+ }
+
+ if ((mode == SImode || mode == SFmode)
+ && CONSTANT_P (x)
+ && LEGITIMATE_CONSTANT_P (x)
+ && the_tag != 't' && the_tag != 'b')
+ {
+ if (GET_CODE (x) != CONST_INT
+ || (INTVAL (x) <= 0xfffff
+ && INTVAL (x) >= 0
+ && (INTVAL (x) % 4) == 0))
+ {
+#if DEBUG_LEGIT
+ fprintf (stderr, " - yup, [const]\n");
+#endif
+ return true;
+ }
+ }
+
+#if DEBUG_LEGIT
+ fprintf (stderr, " - nope.\n");
+#endif
+ return false;
+}
+
+int
+mep_legitimize_reload_address (rtx *x, enum machine_mode mode, int opnum,
+ enum reload_type type,
+ int ind_levels ATTRIBUTE_UNUSED)
+{
+ if (GET_CODE (*x) == PLUS
+ && GET_CODE (XEXP (*x, 0)) == MEM
+ && GET_CODE (XEXP (*x, 1)) == REG)
+ {
+ /* GCC will by default copy the MEM into a REG, which results in
+ an invalid address. For us, the best thing to do is move the
+ whole expression to a REG. */
+ push_reload (*x, NULL_RTX, x, NULL,
+ GENERAL_REGS, mode, VOIDmode,
+ 0, 0, opnum, type);
+ return 1;
+ }
+
+ if (GET_CODE (*x) == PLUS
+ && GET_CODE (XEXP (*x, 0)) == SYMBOL_REF
+ && GET_CODE (XEXP (*x, 1)) == CONST_INT)
+ {
+ char e = mep_section_tag (XEXP (*x, 0));
+
+ if (e != 't' && e != 'b')
+ {
+ /* GCC thinks that (sym+const) is a valid address. Well,
+ sometimes it is, this time it isn't. The best thing to
+ do is reload the symbol to a register, since reg+int
+ tends to work, and we can't just add the symbol and
+ constant anyway. */
+ push_reload (XEXP (*x, 0), NULL_RTX, &(XEXP(*x, 0)), NULL,
+ GENERAL_REGS, mode, VOIDmode,
+ 0, 0, opnum, type);
+ return 1;
+ }
+ }
+ return 0;
+}
+
+int
+mep_core_address_length (rtx insn, int opn)
+{
+ rtx set = single_set (insn);
+ rtx mem = XEXP (set, opn);
+ rtx other = XEXP (set, 1-opn);
+ rtx addr = XEXP (mem, 0);
+
+ if (register_operand (addr, Pmode))
+ return 2;
+ if (GET_CODE (addr) == PLUS)
+ {
+ rtx addend = XEXP (addr, 1);
+
+ gcc_assert (REG_P (XEXP (addr, 0)));
+
+ switch (REGNO (XEXP (addr, 0)))
+ {
+ case STACK_POINTER_REGNUM:
+ if (GET_MODE_SIZE (GET_MODE (mem)) == 4
+ && mep_imm7a4_operand (addend, VOIDmode))
+ return 2;
+ break;
+
+ case 13: /* TP */
+ gcc_assert (REG_P (other));
+
+ if (REGNO (other) >= 8)
+ break;
+
+ if (GET_CODE (addend) == CONST
+ && GET_CODE (XEXP (addend, 0)) == UNSPEC
+ && XINT (XEXP (addend, 0), 1) == UNS_TPREL)
+ return 2;
+
+ if (GET_CODE (addend) == CONST_INT
+ && INTVAL (addend) >= 0
+ && INTVAL (addend) <= 127
+ && INTVAL (addend) % GET_MODE_SIZE (GET_MODE (mem)) == 0)
+ return 2;
+ break;
+ }
+ }
+
+ return 4;
+}
+
+int
+mep_cop_address_length (rtx insn, int opn)
+{
+ rtx set = single_set (insn);
+ rtx mem = XEXP (set, opn);
+ rtx addr = XEXP (mem, 0);
+
+ if (GET_CODE (mem) != MEM)
+ return 2;
+ if (register_operand (addr, Pmode))
+ return 2;
+ if (GET_CODE (addr) == POST_INC)
+ return 2;
+
+ return 4;
+}
+
+#define DEBUG_EXPAND_MOV 0
+bool
+mep_expand_mov (rtx *operands, enum machine_mode mode)
+{
+ int i, t;
+ int tag[2];
+ rtx tpsym, tpoffs;
+ int post_reload = 0;
+
+ tag[0] = mep_section_tag (operands[0]);
+ tag[1] = mep_section_tag (operands[1]);
+
+ if (!reload_in_progress
+ && !reload_completed
+ && GET_CODE (operands[0]) != REG
+ && GET_CODE (operands[0]) != SUBREG
+ && GET_CODE (operands[1]) != REG
+ && GET_CODE (operands[1]) != SUBREG)
+ operands[1] = copy_to_mode_reg (mode, operands[1]);
+
+#if DEBUG_EXPAND_MOV
+ fprintf(stderr, "expand move %s %d\n", mode_name[mode],
+ reload_in_progress || reload_completed);
+ debug_rtx (operands[0]);
+ debug_rtx (operands[1]);
+#endif
+
+ if (mode == DImode || mode == DFmode)
+ return false;
+
+ if (reload_in_progress || reload_completed)
+ {
+ rtx r;
+
+ if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == TP_REGNO)
+ cfun->machine->reload_changes_tp = true;
+
+ if (tag[0] == 't' || tag[1] == 't')
+ {
+ r = has_hard_reg_initial_val (Pmode, GP_REGNO);
+ if (!r || GET_CODE (r) != REG || REGNO (r) != GP_REGNO)
+ post_reload = 1;
+ }
+ if (tag[0] == 'b' || tag[1] == 'b')
+ {
+ r = has_hard_reg_initial_val (Pmode, TP_REGNO);
+ if (!r || GET_CODE (r) != REG || REGNO (r) != TP_REGNO)
+ post_reload = 1;
+ }
+ if (cfun->machine->reload_changes_tp == true)
+ post_reload = 1;
+ }
+
+ if (!post_reload)
+ {
+ rtx n;
+ if (symbol_p (operands[1]))
+ {
+ t = mep_section_tag (operands[1]);
+ if (t == 'b' || t == 't')
+ {
+
+ if (GET_CODE (operands[1]) == SYMBOL_REF)
+ {
+ tpsym = operands[1];
+ n = gen_rtx_UNSPEC (mode,
+ gen_rtvec (1, operands[1]),
+ t == 'b' ? UNS_TPREL : UNS_GPREL);
+ n = gen_rtx_CONST (mode, n);
+ }
+ else if (GET_CODE (operands[1]) == CONST
+ && GET_CODE (XEXP (operands[1], 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF
+ && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
+ {
+ tpsym = XEXP (XEXP (operands[1], 0), 0);
+ tpoffs = XEXP (XEXP (operands[1], 0), 1);
+ n = gen_rtx_UNSPEC (mode,
+ gen_rtvec (1, tpsym),
+ t == 'b' ? UNS_TPREL : UNS_GPREL);
+ n = gen_rtx_PLUS (mode, n, tpoffs);
+ n = gen_rtx_CONST (mode, n);
+ }
+ else if (GET_CODE (operands[1]) == CONST
+ && GET_CODE (XEXP (operands[1], 0)) == UNSPEC)
+ return false;
+ else
+ {
+ error ("unusual TP-relative address");
+ return false;
+ }
+
+ n = gen_rtx_PLUS (mode, (t == 'b' ? mep_tp_rtx ()
+ : mep_gp_rtx ()), n);
+ n = emit_insn (gen_rtx_SET (mode, operands[0], n));
+#if DEBUG_EXPAND_MOV
+ fprintf(stderr, "mep_expand_mov emitting ");
+ debug_rtx(n);
+#endif
+ return true;
+ }
+ }
+
+ for (i=0; i < 2; i++)
+ {
+ t = mep_section_tag (operands[i]);
+ if (GET_CODE (operands[i]) == MEM && (t == 'b' || t == 't'))
+ {
+ rtx sym, n, r;
+ int u;
+
+ sym = XEXP (operands[i], 0);
+ if (GET_CODE (sym) == CONST
+ && GET_CODE (XEXP (sym, 0)) == UNSPEC)
+ sym = XVECEXP (XEXP (sym, 0), 0, 0);
+
+ if (t == 'b')
+ {
+ r = mep_tp_rtx ();
+ u = UNS_TPREL;
+ }
+ else
+ {
+ r = mep_gp_rtx ();
+ u = UNS_GPREL;
+ }
+
+ n = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), u);
+ n = gen_rtx_CONST (Pmode, n);
+ n = gen_rtx_PLUS (Pmode, r, n);
+ operands[i] = replace_equiv_address (operands[i], n);
+ }
+ }
+ }
+
+ if ((GET_CODE (operands[1]) != REG
+ && MEP_CONTROL_REG (operands[0]))
+ || (GET_CODE (operands[0]) != REG
+ && MEP_CONTROL_REG (operands[1])))
+ {
+ rtx temp;
+#if DEBUG_EXPAND_MOV
+ fprintf (stderr, "cr-mem, forcing op1 to reg\n");
+#endif
+ temp = gen_reg_rtx (mode);
+ emit_move_insn (temp, operands[1]);
+ operands[1] = temp;
+ }
+
+ if (symbolref_p (operands[0])
+ && (mep_section_tag (XEXP (operands[0], 0)) == 'f'
+ || (GET_MODE_SIZE (mode) != 4)))
+ {
+ rtx temp;
+
+ gcc_assert (!reload_in_progress && !reload_completed);
+
+ temp = force_reg (Pmode, XEXP (operands[0], 0));
+ operands[0] = replace_equiv_address (operands[0], temp);
+ emit_move_insn (operands[0], operands[1]);
+ return true;
+ }
+
+ if (!post_reload && (tag[1] == 't' || tag[1] == 'b'))
+ tag[1] = 0;
+
+ if (symbol_p (operands[1])
+ && (tag[1] == 'f' || tag[1] == 't' || tag[1] == 'b'))
+ {
+ emit_insn (gen_movsi_topsym_s (operands[0], operands[1]));
+ emit_insn (gen_movsi_botsym_s (operands[0], operands[0], operands[1]));
+ return true;
+ }
+
+ if (symbolref_p (operands[1])
+ && (tag[1] == 'f' || tag[1] == 't' || tag[1] == 'b'))
+ {
+ rtx temp;
+
+ if (reload_in_progress || reload_completed)
+ temp = operands[0];
+ else
+ temp = gen_reg_rtx (Pmode);
+
+ emit_insn (gen_movsi_topsym_s (temp, operands[1]));
+ emit_insn (gen_movsi_botsym_s (temp, temp, operands[1]));
+ emit_move_insn (operands[0], replace_equiv_address (operands[1], temp));
+ return true;
+ }
+
+ return false;
+}
+
+/* Cases where the pattern can't be made to use at all. */
+
+bool
+mep_mov_ok (rtx *operands, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ int i;
+
+#define DEBUG_MOV_OK 0
+#if DEBUG_MOV_OK
+ fprintf (stderr, "mep_mov_ok %s %c=%c\n", mode_name[mode], mep_section_tag (operands[0]),
+ mep_section_tag (operands[1]));
+ debug_rtx (operands[0]);
+ debug_rtx (operands[1]);
+#endif
+
+ /* We want the movh patterns to get these. */
+ if (GET_CODE (operands[1]) == HIGH)
+ return false;
+
+ /* We can't store a register to a far variable without using a
+ scratch register to hold the address. Using far variables should
+ be split by mep_emit_mov anyway. */
+ if (mep_section_tag (operands[0]) == 'f'
+ || mep_section_tag (operands[1]) == 'f')
+ {
+#if DEBUG_MOV_OK
+ fprintf (stderr, " - no, f\n");
+#endif
+ return false;
+ }
+ i = mep_section_tag (operands[1]);
+ if ((i == 'b' || i == 't') && !reload_completed && !reload_in_progress)
+ /* These are supposed to be generated with adds of the appropriate
+ register. During and after reload, however, we allow them to
+ be accessed as normal symbols because adding a dependency on
+ the base register now might cause problems. */
+ {
+#if DEBUG_MOV_OK
+ fprintf (stderr, " - no, bt\n");
+#endif
+ return false;
+ }
+
+ /* The only moves we can allow involve at least one general
+ register, so require it. */
+ for (i = 0; i < 2; i ++)
+ {
+ /* Allow subregs too, before reload. */
+ rtx x = operands[i];
+
+ if (GET_CODE (x) == SUBREG)
+ x = XEXP (x, 0);
+ if (GET_CODE (x) == REG
+ && ! MEP_CONTROL_REG (x))
+ {
+#if DEBUG_MOV_OK
+ fprintf (stderr, " - ok\n");
+#endif
+ return true;
+ }
+ }
+#if DEBUG_MOV_OK
+ fprintf (stderr, " - no, no gen reg\n");
+#endif
+ return false;
+}
+
+#define DEBUG_SPLIT_WIDE_MOVE 0
+void
+mep_split_wide_move (rtx *operands, enum machine_mode mode)
+{
+ int i;
+
+#if DEBUG_SPLIT_WIDE_MOVE
+ fprintf (stderr, "\n\033[34mmep_split_wide_move\033[0m mode %s\n", mode_name[mode]);
+ debug_rtx (operands[0]);
+ debug_rtx (operands[1]);
+#endif
+
+ for (i = 0; i <= 1; i++)
+ {
+ rtx op = operands[i], hi, lo;
+
+ switch (GET_CODE (op))
+ {
+ case REG:
+ {
+ unsigned int regno = REGNO (op);
+
+ if (TARGET_64BIT_CR_REGS && CR_REGNO_P (regno))
+ {
+ rtx i32;
+
+ lo = gen_rtx_REG (SImode, regno);
+ i32 = GEN_INT (32);
+ hi = gen_rtx_ZERO_EXTRACT (SImode,
+ gen_rtx_REG (DImode, regno),
+ i32, i32);
+ }
+ else
+ {
+ hi = gen_rtx_REG (SImode, regno + TARGET_LITTLE_ENDIAN);
+ lo = gen_rtx_REG (SImode, regno + TARGET_BIG_ENDIAN);
+ }
+ }
+ break;
+
+ case CONST_INT:
+ case CONST_DOUBLE:
+ case MEM:
+ hi = operand_subword (op, TARGET_LITTLE_ENDIAN, 0, mode);
+ lo = operand_subword (op, TARGET_BIG_ENDIAN, 0, mode);
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+
+ /* The high part of CR <- GPR moves must be done after the low part. */
+ operands [i + 4] = lo;
+ operands [i + 2] = hi;
+ }
+
+ if (reg_mentioned_p (operands[2], operands[5])
+ || GET_CODE (operands[2]) == ZERO_EXTRACT
+ || GET_CODE (operands[4]) == ZERO_EXTRACT)
+ {
+ rtx tmp;
+
+ /* Overlapping register pairs -- make sure we don't
+ early-clobber ourselves. */
+ tmp = operands[2];
+ operands[2] = operands[4];
+ operands[4] = tmp;
+ tmp = operands[3];
+ operands[3] = operands[5];
+ operands[5] = tmp;
+ }
+
+#if DEBUG_SPLIT_WIDE_MOVE
+ fprintf(stderr, "\033[34m");
+ debug_rtx (operands[2]);
+ debug_rtx (operands[3]);
+ debug_rtx (operands[4]);
+ debug_rtx (operands[5]);
+ fprintf(stderr, "\033[0m");
+#endif
+}
+
+/* Emit a setcc instruction in its entirity. */
+
+static bool
+mep_expand_setcc_1 (enum rtx_code code, rtx dest, rtx op1, rtx op2)
+{
+ rtx tmp;
+
+ switch (code)
+ {
+ case GT:
+ case GTU:
+ tmp = op1, op1 = op2, op2 = tmp;
+ code = swap_condition (code);
+ /* FALLTHRU */
+
+ case LT:
+ case LTU:
+ op1 = force_reg (SImode, op1);
+ emit_insn (gen_rtx_SET (VOIDmode, dest,
+ gen_rtx_fmt_ee (code, SImode, op1, op2)));
+ return true;
+
+ case EQ:
+ if (op2 != const0_rtx)
+ op1 = expand_binop (SImode, sub_optab, op1, op2, NULL, 1, OPTAB_WIDEN);
+ mep_expand_setcc_1 (LTU, dest, op1, const1_rtx);
+ return true;
+
+ case NE:
+ /* Branchful sequence:
+ mov dest, 0 16-bit
+ beq op1, op2, Lover 16-bit (op2 < 16), 32-bit otherwise
+ mov dest, 1 16-bit
+
+ Branchless sequence:
+ add3 tmp, op1, -op2 32-bit (or mov + sub)
+ sltu3 tmp, tmp, 1 16-bit
+ xor3 dest, tmp, 1 32-bit
+ */
+ if (optimize_size && op2 != const0_rtx)
+ return false;
+
+ if (op2 != const0_rtx)
+ op1 = expand_binop (SImode, sub_optab, op1, op2, NULL, 1, OPTAB_WIDEN);
+
+ op2 = gen_reg_rtx (SImode);
+ mep_expand_setcc_1 (LTU, op2, op1, const1_rtx);
+
+ emit_insn (gen_rtx_SET (VOIDmode, dest,
+ gen_rtx_XOR (SImode, op2, const1_rtx)));
+ return true;
+
+ case LE:
+ if (GET_CODE (op2) != CONST_INT
+ || INTVAL (op2) == 0x7ffffff)
+ return false;
+ op2 = GEN_INT (INTVAL (op2) + 1);
+ return mep_expand_setcc_1 (LT, dest, op1, op2);
+
+ case LEU:
+ if (GET_CODE (op2) != CONST_INT
+ || INTVAL (op2) == -1)
+ return false;
+ op2 = GEN_INT (trunc_int_for_mode (INTVAL (op2) + 1, SImode));
+ return mep_expand_setcc_1 (LTU, dest, op1, op2);
+
+ case GE:
+ if (GET_CODE (op2) != CONST_INT
+ || INTVAL (op2) == trunc_int_for_mode (0x80000000, SImode))
+ return false;
+ op2 = GEN_INT (INTVAL (op2) - 1);
+ return mep_expand_setcc_1 (GT, dest, op1, op2);
+
+ case GEU:
+ if (GET_CODE (op2) != CONST_INT
+ || op2 == const0_rtx)
+ return false;
+ op2 = GEN_INT (trunc_int_for_mode (INTVAL (op2) - 1, SImode));
+ return mep_expand_setcc_1 (GTU, dest, op1, op2);
+
+ default:
+ gcc_unreachable ();
+ }
+}
+
+bool
+mep_expand_setcc (rtx *operands)
+{
+ rtx dest = operands[0];
+ enum rtx_code code = GET_CODE (operands[1]);
+ rtx op0 = operands[2];
+ rtx op1 = operands[3];
+
+ return mep_expand_setcc_1 (code, dest, op0, op1);
+}
+
+rtx
+mep_expand_cbranch (rtx *operands)
+{
+ enum rtx_code code = GET_CODE (operands[0]);
+ rtx op0 = operands[1];
+ rtx op1 = operands[2];
+ rtx tmp;
+
+ restart:
+ switch (code)
+ {
+ case LT:
+ if (mep_imm4_operand (op1, SImode))
+ break;
+
+ tmp = gen_reg_rtx (SImode);
+ gcc_assert (mep_expand_setcc_1 (LT, tmp, op0, op1));
+ code = NE;
+ op0 = tmp;
+ op1 = const0_rtx;
+ break;
+
+ case GE:
+ if (mep_imm4_operand (op1, SImode))
+ break;
+
+ tmp = gen_reg_rtx (SImode);
+ gcc_assert (mep_expand_setcc_1 (LT, tmp, op0, op1));
+
+ code = EQ;
+ op0 = tmp;
+ op1 = const0_rtx;
+ break;
+
+ case EQ:
+ case NE:
+ if (! mep_reg_or_imm4_operand (op1, SImode))
+ op1 = force_reg (SImode, op1);
+ break;
+
+ case LE:
+ case GT:
+ if (GET_CODE (op1) == CONST_INT
+ && INTVAL (op1) != 0x7fffffff)
+ {
+ op1 = GEN_INT (INTVAL (op1) + 1);
+ code = (code == LE ? LT : GE);
+ goto restart;
+ }
+
+ tmp = gen_reg_rtx (SImode);
+ gcc_assert (mep_expand_setcc_1 (LT, tmp, op1, op0));
+
+ code = (code == LE ? EQ : NE);
+ op0 = tmp;
+ op1 = const0_rtx;
+ break;
+
+ case LTU:
+ if (op1 == const1_rtx)
+ {
+ code = EQ;
+ op1 = const0_rtx;
+ break;
+ }
+
+ tmp = gen_reg_rtx (SImode);
+ gcc_assert (mep_expand_setcc_1 (LTU, tmp, op0, op1));
+ code = NE;
+ op0 = tmp;
+ op1 = const0_rtx;
+ break;
+
+ case LEU:
+ tmp = gen_reg_rtx (SImode);
+ if (mep_expand_setcc_1 (LEU, tmp, op0, op1))
+ code = NE;
+ else if (mep_expand_setcc_1 (LTU, tmp, op1, op0))
+ code = EQ;
+ else
+ gcc_unreachable ();
+ op0 = tmp;
+ op1 = const0_rtx;
+ break;
+
+ case GTU:
+ tmp = gen_reg_rtx (SImode);
+ gcc_assert (mep_expand_setcc_1 (GTU, tmp, op0, op1)
+ || mep_expand_setcc_1 (LTU, tmp, op1, op0));
+ code = NE;
+ op0 = tmp;
+ op1 = const0_rtx;
+ break;
+
+ case GEU:
+ tmp = gen_reg_rtx (SImode);
+ if (mep_expand_setcc_1 (GEU, tmp, op0, op1))
+ code = NE;
+ else if (mep_expand_setcc_1 (LTU, tmp, op0, op1))
+ code = EQ;
+ else
+ gcc_unreachable ();
+ op0 = tmp;
+ op1 = const0_rtx;
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+
+ return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
+}
+
+const char *
+mep_emit_cbranch (rtx *operands, int ne)
+{
+ if (GET_CODE (operands[1]) == REG)
+ return ne ? "bne\t%0, %1, %l2" : "beq\t%0, %1, %l2";
+ else if (INTVAL (operands[1]) == 0)
+ return ne ? "bnez\t%0, %l2" : "beqz\t%0, %l2";
+ else
+ return ne ? "bnei\t%0, %1, %l2" : "beqi\t%0, %1, %l2";
+}
+
+void
+mep_expand_call (rtx *operands, int returns_value)
+{
+ rtx addr = operands[returns_value];
+ rtx tp = mep_tp_rtx ();
+ rtx gp = mep_gp_rtx ();
+
+ gcc_assert (GET_CODE (addr) == MEM);
+
+ addr = XEXP (addr, 0);
+
+ if (! mep_call_address_operand (addr, VOIDmode))
+ addr = force_reg (SImode, addr);
+
+ if (! operands[returns_value+2])
+ operands[returns_value+2] = const0_rtx;
+
+ if (returns_value)
+ emit_call_insn (gen_call_value_internal (operands[0], addr, operands[2],
+ operands[3], tp, gp));
+ else
+ emit_call_insn (gen_call_internal (addr, operands[1],
+ operands[2], tp, gp));
+}
+\f
+/* Aliasing Support. */
+
+/* If X is a machine specific address (i.e. a symbol or label being
+ referenced as a displacement from the GOT implemented using an
+ UNSPEC), then return the base term. Otherwise return X. */
+
+rtx
+mep_find_base_term (rtx x)
+{
+ rtx base, term;
+ int unspec;
+
+ if (GET_CODE (x) != PLUS)
+ return x;
+ base = XEXP (x, 0);
+ term = XEXP (x, 1);
+
+ if (has_hard_reg_initial_val(Pmode, TP_REGNO)
+ && base == mep_tp_rtx ())
+ unspec = UNS_TPREL;
+ else if (has_hard_reg_initial_val(Pmode, GP_REGNO)
+ && base == mep_gp_rtx ())
+ unspec = UNS_GPREL;
+ else
+ return x;
+
+ if (GET_CODE (term) != CONST)
+ return x;
+ term = XEXP (term, 0);
+
+ if (GET_CODE (term) != UNSPEC
+ || XINT (term, 1) != unspec)
+ return x;
+
+ return XVECEXP (term, 0, 0);
+}
+\f
+/* Reload Support. */
+
+/* Return true if the registers in CLASS cannot represent the change from
+ modes FROM to TO. */
+
+bool
+mep_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
+ enum reg_class regclass)
+{
+ if (from == to)
+ return false;
+
+ /* 64-bit COP regs must remain 64-bit COP regs. */
+ if (TARGET_64BIT_CR_REGS
+ && (regclass == CR_REGS
+ || regclass == LOADABLE_CR_REGS)
+ && (GET_MODE_SIZE (to) < 8
+ || GET_MODE_SIZE (from) < 8))
+ return true;
+
+ return false;
+}
+
+#define MEP_NONGENERAL_CLASS(C) (!reg_class_subset_p (C, GENERAL_REGS))
+
+static bool
+mep_general_reg (rtx x)
+{
+ while (GET_CODE (x) == SUBREG)
+ x = XEXP (x, 0);
+ return GET_CODE (x) == REG && GR_REGNO_P (REGNO (x));
+}
+
+static bool
+mep_nongeneral_reg (rtx x)
+{
+ while (GET_CODE (x) == SUBREG)
+ x = XEXP (x, 0);
+ return (GET_CODE (x) == REG
+ && !GR_REGNO_P (REGNO (x)) && REGNO (x) < FIRST_PSEUDO_REGISTER);
+}
+
+static bool
+mep_general_copro_reg (rtx x)
+{
+ while (GET_CODE (x) == SUBREG)
+ x = XEXP (x, 0);
+ return (GET_CODE (x) == REG && CR_REGNO_P (REGNO (x)));
+}
+
+static bool
+mep_nonregister (rtx x)
+{
+ while (GET_CODE (x) == SUBREG)
+ x = XEXP (x, 0);
+ return (GET_CODE (x) != REG || REGNO (x) >= FIRST_PSEUDO_REGISTER);
+}
+
+#define DEBUG_RELOAD 0
+
+/* Return the secondary reload class needed for moving value X to or
+ from a register in coprocessor register class CLASS. */
+
+static enum reg_class
+mep_secondary_copro_reload_class (enum reg_class rclass, rtx x)
+{
+ if (mep_general_reg (x))
+ /* We can do the move directly if mep_have_core_copro_moves_p,
+ otherwise we need to go through memory. Either way, no secondary
+ register is needed. */
+ return NO_REGS;
+
+ if (mep_general_copro_reg (x))
+ {
+ /* We can do the move directly if mep_have_copro_copro_moves_p. */
+ if (mep_have_copro_copro_moves_p)
+ return NO_REGS;
+
+ /* Otherwise we can use a temporary if mep_have_core_copro_moves_p. */
+ if (mep_have_core_copro_moves_p)
+ return GENERAL_REGS;
+
+ /* Otherwise we need to do it through memory. No secondary
+ register is needed. */
+ return NO_REGS;
+ }
+
+ if (reg_class_subset_p (rclass, LOADABLE_CR_REGS)
+ && constraint_satisfied_p (x, CONSTRAINT_U))
+ /* X is a memory value that we can access directly. */
+ return NO_REGS;
+
+ /* We have to move X into a GPR first and then copy it to
+ the coprocessor register. The move from the GPR to the
+ coprocessor might be done directly or through memory,
+ depending on mep_have_core_copro_moves_p. */
+ return GENERAL_REGS;
+}
+
+/* Copying X to register in RCLASS. */
+
+int
+mep_secondary_input_reload_class (enum reg_class rclass,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ rtx x)
+{
+ int rv = NO_REGS;
+
+#if DEBUG_RELOAD
+ fprintf (stderr, "secondary input reload copy to %s %s from ", reg_class_names[rclass], mode_name[mode]);
+ debug_rtx (x);
+#endif
+
+ if (reg_class_subset_p (rclass, CR_REGS))
+ rv = mep_secondary_copro_reload_class (rclass, x);
+ else if (MEP_NONGENERAL_CLASS (rclass)
+ && (mep_nonregister (x) || mep_nongeneral_reg (x)))
+ rv = GENERAL_REGS;
+
+#if DEBUG_RELOAD
+ fprintf (stderr, " - requires %s\n", reg_class_names[rv]);
+#endif
+ return rv;
+}
+
+/* Copying register in RCLASS to X. */
+
+int
+mep_secondary_output_reload_class (enum reg_class rclass,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ rtx x)
+{
+ int rv = NO_REGS;
+
+#if DEBUG_RELOAD
+ fprintf (stderr, "secondary output reload copy from %s %s to ", reg_class_names[rclass], mode_name[mode]);
+ debug_rtx (x);
+#endif
+
+ if (reg_class_subset_p (rclass, CR_REGS))
+ rv = mep_secondary_copro_reload_class (rclass, x);
+ else if (MEP_NONGENERAL_CLASS (rclass)
+ && (mep_nonregister (x) || mep_nongeneral_reg (x)))
+ rv = GENERAL_REGS;
+
+#if DEBUG_RELOAD
+ fprintf (stderr, " - requires %s\n", reg_class_names[rv]);
+#endif
+
+ return rv;
+}
+
+/* Implement SECONDARY_MEMORY_NEEDED. */
+
+bool
+mep_secondary_memory_needed (enum reg_class rclass1, enum reg_class rclass2,
+ enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ if (!mep_have_core_copro_moves_p)
+ {
+ if (reg_classes_intersect_p (rclass1, CR_REGS)
+ && reg_classes_intersect_p (rclass2, GENERAL_REGS))
+ return true;
+ if (reg_classes_intersect_p (rclass2, CR_REGS)
+ && reg_classes_intersect_p (rclass1, GENERAL_REGS))
+ return true;
+ if (!mep_have_copro_copro_moves_p
+ && reg_classes_intersect_p (rclass1, CR_REGS)
+ && reg_classes_intersect_p (rclass2, CR_REGS))
+ return true;
+ }
+ return false;
+}
+
+void
+mep_expand_reload (rtx *operands, enum machine_mode mode)
+{
+ /* There are three cases for each direction:
+ register, farsym
+ control, farsym
+ control, nearsym */
+
+ int s0 = mep_section_tag (operands[0]) == 'f';
+ int s1 = mep_section_tag (operands[1]) == 'f';
+ int c0 = mep_nongeneral_reg (operands[0]);
+ int c1 = mep_nongeneral_reg (operands[1]);
+ int which = (s0 ? 20:0) + (c0 ? 10:0) + (s1 ? 2:0) + (c1 ? 1:0);
+
+#if DEBUG_RELOAD
+ fprintf (stderr, "expand_reload %s\n", mode_name[mode]);
+ debug_rtx (operands[0]);
+ debug_rtx (operands[1]);
+#endif
+
+ switch (which)
+ {
+ case 00: /* Don't know why this gets here. */
+ case 02: /* general = far */
+ emit_move_insn (operands[0], operands[1]);
+ return;
+
+ case 10: /* cr = mem */
+ case 11: /* cr = cr */
+ case 01: /* mem = cr */
+ case 12: /* cr = far */
+ emit_move_insn (operands[2], operands[1]);
+ emit_move_insn (operands[0], operands[2]);
+ return;
+
+ case 20: /* far = general */
+ emit_move_insn (operands[2], XEXP (operands[1], 0));
+ emit_move_insn (operands[0], gen_rtx_MEM (mode, operands[2]));
+ return;
+
+ case 21: /* far = cr */
+ case 22: /* far = far */
+ default:
+ fprintf (stderr, "unsupported expand reload case %02d for mode %s\n",
+ which, mode_name[mode]);
+ debug_rtx (operands[0]);
+ debug_rtx (operands[1]);
+ gcc_unreachable ();
+ }
+}
+
+/* Implement PREFERRED_RELOAD_CLASS. See whether X is a constant that
+ can be moved directly into registers 0 to 7, but not into the rest.
+ If so, and if the required class includes registers 0 to 7, restrict
+ it to those registers. */
+
+enum reg_class
+mep_preferred_reload_class (rtx x, enum reg_class rclass)
+{
+ switch (GET_CODE (x))
+ {
+ case CONST_INT:
+ if (INTVAL (x) >= 0x10000
+ && INTVAL (x) < 0x01000000
+ && (INTVAL (x) & 0xffff) != 0
+ && reg_class_subset_p (TPREL_REGS, rclass))
+ rclass = TPREL_REGS;
+ break;
+
+ case CONST:
+ case SYMBOL_REF:
+ case LABEL_REF:
+ if (mep_section_tag (x) != 'f'
+ && reg_class_subset_p (TPREL_REGS, rclass))
+ rclass = TPREL_REGS;
+ break;
+
+ default:
+ break;
+ }
+ return rclass;
+}
+\f
+/* Implement REGISTER_MOVE_COST. Return 2 for direct single-register
+ moves, 4 for direct double-register moves, and 1000 for anything
+ that requires a temporary register or temporary stack slot. */
+
+int
+mep_register_move_cost (enum machine_mode mode, enum reg_class from, enum reg_class to)
+{
+ if (mep_have_copro_copro_moves_p
+ && reg_class_subset_p (from, CR_REGS)
+ && reg_class_subset_p (to, CR_REGS))
+ {
+ if (TARGET_32BIT_CR_REGS && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+ return 4;
+ return 2;
+ }
+ if (reg_class_subset_p (from, CR_REGS)
+ && reg_class_subset_p (to, CR_REGS))
+ {
+ if (TARGET_32BIT_CR_REGS && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+ return 8;
+ return 4;
+ }
+ if (reg_class_subset_p (from, CR_REGS)
+ || reg_class_subset_p (to, CR_REGS))
+ {
+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+ return 4;
+ return 2;
+ }
+ if (mep_secondary_memory_needed (from, to, mode))
+ return 1000;
+ if (MEP_NONGENERAL_CLASS (from) && MEP_NONGENERAL_CLASS (to))
+ return 1000;
+
+ if (GET_MODE_SIZE (mode) > 4)
+ return 4;
+
+ return 2;
+}
+
+\f
+/* Functions to save and restore machine-specific function data. */
+
+static struct machine_function *
+mep_init_machine_status (void)
+{
+ struct machine_function *f;
+
+ f = (struct machine_function *) ggc_alloc_cleared (sizeof (struct machine_function));
+
+ return f;
+}
+
+static rtx
+mep_allocate_initial_value (rtx reg)
+{
+ int rss;
+
+ if (GET_CODE (reg) != REG)
+ return NULL_RTX;
+
+ if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
+ return NULL_RTX;
+
+ /* In interrupt functions, the "initial" values of $gp and $tp are
+ provided by the prologue. They are not necessarily the same as
+ the values that the caller was using. */
+ if (REGNO (reg) == TP_REGNO || REGNO (reg) == GP_REGNO)
+ if (mep_interrupt_p ())
+ return NULL_RTX;
+
+ if (! cfun->machine->reg_save_slot[REGNO(reg)])
+ {
+ cfun->machine->reg_save_size += 4;
+ cfun->machine->reg_save_slot[REGNO(reg)] = cfun->machine->reg_save_size;
+ }
+
+ rss = cfun->machine->reg_save_slot[REGNO(reg)];
+ return gen_rtx_MEM (SImode, plus_constant (arg_pointer_rtx, -rss));
+}
+
+rtx
+mep_return_addr_rtx (int count)
+{
+ if (count != 0)
+ return const0_rtx;
+
+ return get_hard_reg_initial_val (Pmode, LP_REGNO);
+}
+
+static rtx
+mep_tp_rtx (void)
+{
+ return get_hard_reg_initial_val (Pmode, TP_REGNO);
+}
+
+static rtx
+mep_gp_rtx (void)
+{
+ return get_hard_reg_initial_val (Pmode, GP_REGNO);
+}
+
+static bool
+mep_interrupt_p (void)
+{
+ if (cfun->machine->interrupt_handler == 0)
+ {
+ int interrupt_handler
+ = (lookup_attribute ("interrupt",
+ DECL_ATTRIBUTES (current_function_decl))
+ != NULL_TREE);
+ cfun->machine->interrupt_handler = interrupt_handler ? 2 : 1;
+ }
+ return cfun->machine->interrupt_handler == 2;
+}
+
+static bool
+mep_disinterrupt_p (void)
+{
+ if (cfun->machine->disable_interrupts == 0)
+ {
+ int disable_interrupts
+ = (lookup_attribute ("disinterrupt",
+ DECL_ATTRIBUTES (current_function_decl))
+ != NULL_TREE);
+ cfun->machine->disable_interrupts = disable_interrupts ? 2 : 1;
+ }
+ return cfun->machine->disable_interrupts == 2;
+}
+
+\f
+/* Frame/Epilog/Prolog Related. */
+
+static bool
+mep_reg_set_p (rtx reg, rtx insn)
+{
+ /* Similar to reg_set_p in rtlanal.c, but we ignore calls */
+ if (INSN_P (insn))
+ {
+ if (FIND_REG_INC_NOTE (insn, reg))
+ return true;
+ insn = PATTERN (insn);
+ }
+
+ if (GET_CODE (insn) == SET
+ && GET_CODE (XEXP (insn, 0)) == REG
+ && GET_CODE (XEXP (insn, 1)) == REG
+ && REGNO (XEXP (insn, 0)) == REGNO (XEXP (insn, 1)))
+ return false;
+
+ return set_of (reg, insn) != NULL_RTX;
+}
+
+
+#define MEP_SAVES_UNKNOWN 0
+#define MEP_SAVES_YES 1
+#define MEP_SAVES_MAYBE 2
+#define MEP_SAVES_NO 3
+
+static bool
+mep_reg_set_in_function (int regno)
+{
+ rtx reg, insn;
+
+ if (mep_interrupt_p () && df_regs_ever_live_p(regno))
+ return true;
+
+ if (regno == LP_REGNO && (profile_arc_flag > 0 || profile_flag > 0))
+ return true;
+
+ push_topmost_sequence ();
+ insn = get_insns ();
+ pop_topmost_sequence ();
+
+ if (!insn)
+ return false;
+
+ reg = gen_rtx_REG (SImode, regno);
+
+ for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn))
+ if (INSN_P (insn) && mep_reg_set_p (reg, insn))
+ return true;
+ return false;
+}
+
+static bool
+mep_asm_without_operands_p (void)
+{
+ if (cfun->machine->asms_without_operands == 0)
+ {
+ rtx insn;
+
+ push_topmost_sequence ();
+ insn = get_insns ();
+ pop_topmost_sequence ();
+
+ cfun->machine->asms_without_operands = 1;
+ while (insn)
+ {
+ if (INSN_P (insn)
+ && GET_CODE (PATTERN (insn)) == ASM_INPUT)
+ {
+ cfun->machine->asms_without_operands = 2;
+ break;
+ }
+ insn = NEXT_INSN (insn);
+ }
+
+ }
+ return cfun->machine->asms_without_operands == 2;
+}
+
+/* Interrupt functions save/restore every call-preserved register, and
+ any call-used register it uses (or all if it calls any function,
+ since they may get clobbered there too). Here we check to see
+ which call-used registers need saving. */
+
+static bool
+mep_interrupt_saved_reg (int r)
+{
+ if (!mep_interrupt_p ())
+ return false;
+ if (r == REGSAVE_CONTROL_TEMP
+ || (TARGET_64BIT_CR_REGS && TARGET_COP && r == REGSAVE_CONTROL_TEMP+1))
+ return true;
+ if (mep_asm_without_operands_p ()
+ && (!fixed_regs[r]
+ || (r == RPB_REGNO || r == RPE_REGNO || r == RPC_REGNO || r == LP_REGNO)))
+ return true;
+ if (!current_function_is_leaf)
+ /* Function calls mean we need to save $lp. */
+ if (r == LP_REGNO)
+ return true;
+ if (!current_function_is_leaf || cfun->machine->doloop_tags > 0)
+ /* The interrupt handler might use these registers for repeat blocks,
+ or it might call a function that does so. */
+ if (r == RPB_REGNO || r == RPE_REGNO || r == RPC_REGNO)
+ return true;
+ if (current_function_is_leaf && call_used_regs[r] && !df_regs_ever_live_p(r))
+ return false;
+ /* Functions we call might clobber these. */
+ if (call_used_regs[r] && !fixed_regs[r])
+ return true;
+ return false;
+}
+
+static bool
+mep_call_saves_register (int r)
+{
+ /* if (cfun->machine->reg_saved[r] == MEP_SAVES_UNKNOWN)*/
+ {
+ int rv = MEP_SAVES_NO;
+
+ if (cfun->machine->reg_save_slot[r])
+ rv = MEP_SAVES_YES;
+ else if (r == LP_REGNO && (profile_arc_flag > 0 || profile_flag > 0))
+ rv = MEP_SAVES_YES;
+ else if (r == FRAME_POINTER_REGNUM && frame_pointer_needed)
+ rv = MEP_SAVES_YES;
+ else if ((!call_used_regs[r] || r == LP_REGNO) && df_regs_ever_live_p(r))
+ rv = MEP_SAVES_YES;
+ else if (crtl->calls_eh_return && (r == 10 || r == 11))
+ /* We need these to have stack slots so that they can be set during
+ unwinding. */
+ rv = MEP_SAVES_YES;
+ else if (mep_interrupt_saved_reg (r))
+ rv = MEP_SAVES_YES;
+ cfun->machine->reg_saved[r] = rv;
+ }
+ return cfun->machine->reg_saved[r] == MEP_SAVES_YES;
+}
+
+/* Return true if epilogue uses register REGNO. */
+
+bool
+mep_epilogue_uses (int regno)
+{
+ /* Since $lp is a call-saved register, the generic code will normally
+ mark it used in the epilogue if it needs to be saved and restored.
+ However, when profiling is enabled, the profiling code will implicitly
+ clobber $11. This case has to be handled specially both here and in
+ mep_call_saves_register. */
+ if (regno == LP_REGNO && (profile_arc_flag > 0 || profile_flag > 0))
+ return true;
+ /* Interrupt functions save/restore pretty much everything. */
+ return (reload_completed && mep_interrupt_saved_reg (regno));
+}
+
+static int
+mep_reg_size (int regno)
+{
+ if (CR_REGNO_P (regno) && TARGET_64BIT_CR_REGS)
+ return 8;
+ return 4;
+}
+
+int
+mep_elimination_offset (int from, int to)
+{
+ int reg_save_size;
+ int i;
+ int frame_size = get_frame_size () + crtl->outgoing_args_size;
+ int total_size;
+
+ memset (cfun->machine->reg_saved, 0, sizeof (cfun->machine->reg_saved));
+
+ /* We don't count arg_regs_to_save in the arg pointer offset, because
+ gcc thinks the arg pointer has moved along with the saved regs.
+ However, we do count it when we adjust $sp in the prologue. */
+ reg_save_size = 0;
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+ if (mep_call_saves_register (i))
+ reg_save_size += mep_reg_size (i);
+
+ if (reg_save_size % 8)
+ cfun->machine->regsave_filler = 8 - (reg_save_size % 8);
+ else
+ cfun->machine->regsave_filler = 0;
+
+ /* This is what our total stack adjustment looks like. */
+ total_size = (reg_save_size + frame_size + cfun->machine->regsave_filler);
+
+ if (total_size % 8)
+ cfun->machine->frame_filler = 8 - (total_size % 8);
+ else
+ cfun->machine->frame_filler = 0;
+
+
+ if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
+ return reg_save_size + cfun->machine->regsave_filler;
+
+ if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+ return cfun->machine->frame_filler + frame_size;
+
+ if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+ return reg_save_size + cfun->machine->regsave_filler + cfun->machine->frame_filler + frame_size;
+
+ gcc_unreachable ();
+}
+
+static rtx
+F (rtx x)
+{
+ RTX_FRAME_RELATED_P (x) = 1;
+ return x;
+}
+
+/* Since the prologue/epilogue code is generated after optimization,
+ we can't rely on gcc to split constants for us. So, this code
+ captures all the ways to add a constant to a register in one logic
+ chunk, including optimizing away insns we just don't need. This
+ makes the prolog/epilog code easier to follow. */
+static void
+add_constant (int dest, int src, int value, int mark_frame)
+{
+ rtx insn;
+ int hi, lo;
+
+ if (src == dest && value == 0)
+ return;
+
+ if (value == 0)
+ {
+ insn = emit_move_insn (gen_rtx_REG (SImode, dest),
+ gen_rtx_REG (SImode, src));
+ if (mark_frame)
+ RTX_FRAME_RELATED_P(insn) = 1;
+ return;
+ }
+
+ if (value >= -32768 && value <= 32767)
+ {
+ insn = emit_insn (gen_addsi3 (gen_rtx_REG (SImode, dest),
+ gen_rtx_REG (SImode, src),
+ GEN_INT (value)));
+ if (mark_frame)
+ RTX_FRAME_RELATED_P(insn) = 1;
+ return;
+ }
+
+ /* Big constant, need to use a temp register. We use
+ REGSAVE_CONTROL_TEMP because it's call clobberable (the reg save
+ area is always small enough to directly add to). */
+
+ hi = trunc_int_for_mode (value & 0xffff0000, SImode);
+ lo = value & 0xffff;
+
+ insn = emit_move_insn (gen_rtx_REG (SImode, REGSAVE_CONTROL_TEMP),
+ GEN_INT (hi));
+
+ if (lo)
+ {
+ insn = emit_insn (gen_iorsi3 (gen_rtx_REG (SImode, REGSAVE_CONTROL_TEMP),
+ gen_rtx_REG (SImode, REGSAVE_CONTROL_TEMP),
+ GEN_INT (lo)));
+ }
+
+ insn = emit_insn (gen_addsi3 (gen_rtx_REG (SImode, dest),
+ gen_rtx_REG (SImode, src),
+ gen_rtx_REG (SImode, REGSAVE_CONTROL_TEMP)));
+ if (mark_frame)
+ {
+ RTX_FRAME_RELATED_P(insn) = 1;
+ add_reg_note (insn, REG_FRAME_RELATED_EXPR,
+ gen_rtx_SET (SImode,
+ gen_rtx_REG (SImode, dest),
+ gen_rtx_PLUS (SImode,
+ gen_rtx_REG (SImode, dest),
+ GEN_INT (value))));
+ }
+}
+
+static bool
+mep_function_uses_sp (void)
+{
+ rtx insn;
+ struct sequence_stack *seq;
+ rtx sp = gen_rtx_REG (SImode, SP_REGNO);
+
+ insn = get_insns ();
+ for (seq = crtl->emit.sequence_stack;
+ seq;
+ insn = seq->first, seq = seq->next);
+
+ while (insn)
+ {
+ if (mep_mentioned_p (insn, sp, 0))
+ return true;
+ insn = NEXT_INSN (insn);
+ }
+ return false;
+}
+
+/* Move SRC to DEST. Mark the move as being potentially dead if
+ MAYBE_DEAD_P. */
+
+static rtx
+maybe_dead_move (rtx dest, rtx src, bool ATTRIBUTE_UNUSED maybe_dead_p)
+{
+ rtx insn = emit_move_insn (dest, src);
+#if 0
+ if (maybe_dead_p)
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, NULL);
+#endif
+ return insn;
+}
+
+/* Used for interrupt functions, which can't assume that $tp and $gp
+ contain the correct pointers. */
+
+static void
+mep_reload_pointer (int regno, const char *symbol)
+{
+ rtx reg, sym;
+
+ if (!df_regs_ever_live_p(regno) && current_function_is_leaf)
+ return;
+
+ reg = gen_rtx_REG (SImode, regno);
+ sym = gen_rtx_SYMBOL_REF (SImode, symbol);
+ emit_insn (gen_movsi_topsym_s (reg, sym));
+ emit_insn (gen_movsi_botsym_s (reg, reg, sym));
+}
+
+void
+mep_expand_prologue (void)
+{
+ int i, rss, sp_offset = 0;
+ int reg_save_size;
+ int frame_size;
+ int really_need_stack_frame = frame_size;
+ int di_ofs = 0;
+
+ /* We must not allow register renaming in interrupt functions,
+ because that invalidates the correctness of the set of call-used
+ registers we're going to save/restore. */
+ mep_set_leaf_registers (mep_interrupt_p () ? 0 : 1);
+
+ if (mep_disinterrupt_p ())
+ emit_insn (gen_mep_disable_int ());
+
+ cfun->machine->mep_frame_pointer_needed = frame_pointer_needed;
+
+ reg_save_size = mep_elimination_offset (ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM);
+ frame_size = mep_elimination_offset (FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM);
+
+ /* Assign save slots for any register not already saved. DImode
+ registers go at the end of the reg save area; the rest go at the
+ beginning. This is for alignment purposes. */
+ for (i=0; i<FIRST_PSEUDO_REGISTER; i++)
+ if (mep_call_saves_register(i))
+ {
+ int regsize = mep_reg_size (i);
+
+ if ((i != TP_REGNO && i != GP_REGNO && i != LP_REGNO)
+ || mep_reg_set_in_function (i))
+ really_need_stack_frame = 1;
+
+ if (cfun->machine->reg_save_slot[i])
+ continue;
+
+ if (regsize < 8)
+ {
+ cfun->machine->reg_save_size += regsize;
+ cfun->machine->reg_save_slot[i] = cfun->machine->reg_save_size;
+ }
+ else
+ {
+ cfun->machine->reg_save_slot[i] = reg_save_size - di_ofs;
+ di_ofs += 8;
+ }
+ }
+
+ sp_offset = reg_save_size;
+ if (sp_offset + frame_size < 128)
+ sp_offset += frame_size ;
+
+ add_constant (SP_REGNO, SP_REGNO, -sp_offset, 1);
+
+ for (i=0; i<FIRST_PSEUDO_REGISTER; i++)
+ if (mep_call_saves_register(i))
+ {
+ rtx mem;
+ bool maybe_dead_p;
+ enum machine_mode rmode;
+
+ rss = cfun->machine->reg_save_slot[i];
+
+ if ((i == TP_REGNO || i == GP_REGNO || i == LP_REGNO)
+ && (!mep_reg_set_in_function (i)
+ && !mep_interrupt_p ()))
+ continue;
+
+ if (mep_reg_size (i) == 8)
+ rmode = DImode;
+ else
+ rmode = SImode;
+
+ /* If there is a pseudo associated with this register's initial value,
+ reload might have already spilt it to the stack slot suggested by
+ ALLOCATE_INITIAL_VALUE. The moves emitted here can then be safely
+ deleted as dead. */
+ mem = gen_rtx_MEM (rmode,
+ plus_constant (stack_pointer_rtx, sp_offset - rss));
+ maybe_dead_p = rtx_equal_p (mem, has_hard_reg_initial_val (rmode, i));
+
+ if (GR_REGNO_P (i) || LOADABLE_CR_REGNO_P (i))
+ F(maybe_dead_move (mem, gen_rtx_REG (rmode, i), maybe_dead_p));
+ else if (rmode == DImode)
+ {
+ rtx insn;
+ int be = TARGET_BIG_ENDIAN ? 4 : 0;
+
+ mem = gen_rtx_MEM (SImode,
+ plus_constant (stack_pointer_rtx, sp_offset - rss + be));
+
+ maybe_dead_move (gen_rtx_REG (SImode, REGSAVE_CONTROL_TEMP),
+ gen_rtx_REG (SImode, i),
+ maybe_dead_p);
+ maybe_dead_move (gen_rtx_REG (SImode, REGSAVE_CONTROL_TEMP+1),
+ gen_rtx_ZERO_EXTRACT (SImode,
+ gen_rtx_REG (DImode, i),
+ GEN_INT (32),
+ GEN_INT (32)),
+ maybe_dead_p);
+ insn = maybe_dead_move (mem,
+ gen_rtx_REG (SImode, REGSAVE_CONTROL_TEMP),
+ maybe_dead_p);
+ RTX_FRAME_RELATED_P (insn) = 1;
+
+ add_reg_note (insn, REG_FRAME_RELATED_EXPR,
+ gen_rtx_SET (VOIDmode,
+ copy_rtx (mem),
+ gen_rtx_REG (rmode, i)));
+ mem = gen_rtx_MEM (SImode,
+ plus_constant (stack_pointer_rtx, sp_offset - rss + (4-be)));
+ insn = maybe_dead_move (mem,
+ gen_rtx_REG (SImode, REGSAVE_CONTROL_TEMP+1),
+ maybe_dead_p);
+ }
+ else
+ {
+ rtx insn;
+ maybe_dead_move (gen_rtx_REG (rmode, REGSAVE_CONTROL_TEMP),
+ gen_rtx_REG (rmode, i),
+ maybe_dead_p);
+ insn = maybe_dead_move (mem,
+ gen_rtx_REG (rmode, REGSAVE_CONTROL_TEMP),
+ maybe_dead_p);
+ RTX_FRAME_RELATED_P (insn) = 1;
+
+ add_reg_note (insn, REG_FRAME_RELATED_EXPR,
+ gen_rtx_SET (VOIDmode,
+ copy_rtx (mem),
+ gen_rtx_REG (rmode, i)));
+ }
+ }
+
+ if (frame_pointer_needed)
+ add_constant (FP_REGNO, SP_REGNO, sp_offset - frame_size, 1);
+
+ add_constant (SP_REGNO, SP_REGNO, sp_offset-(reg_save_size+frame_size), 1);
+
+ if (mep_interrupt_p ())
+ {
+ mep_reload_pointer(GP_REGNO, "__sdabase");
+ mep_reload_pointer(TP_REGNO, "__tpbase");
+ }
+}
+
+static void
+mep_start_function (FILE *file, HOST_WIDE_INT hwi_local)
+{
+ int local = hwi_local;
+ int frame_size = local + crtl->outgoing_args_size;
+ int reg_save_size;
+ int ffill;
+ int i, sp, skip;
+ int sp_offset;
+ int slot_map[FIRST_PSEUDO_REGISTER], si, sj;
+
+ reg_save_size = mep_elimination_offset (ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM);
+ frame_size = mep_elimination_offset (FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM);
+ sp_offset = reg_save_size + frame_size;
+
+ ffill = cfun->machine->frame_filler;
+
+ if (cfun->machine->mep_frame_pointer_needed)
+ reg_names[FP_REGNO] = "$fp";
+ else
+ reg_names[FP_REGNO] = "$8";
+
+ if (sp_offset == 0)
+ return;
+
+ if (debug_info_level == DINFO_LEVEL_NONE)
+ {
+ fprintf (file, "\t# frame: %d", sp_offset);
+ if (reg_save_size)
+ fprintf (file, " %d regs", reg_save_size);
+ if (local)
+ fprintf (file, " %d locals", local);
+ if (crtl->outgoing_args_size)
+ fprintf (file, " %d args", crtl->outgoing_args_size);
+ fprintf (file, "\n");
+ return;
+ }
+
+ fprintf (file, "\t#\n");
+ fprintf (file, "\t# Initial Frame Information:\n");
+ if (sp_offset || !frame_pointer_needed)
+ fprintf (file, "\t# Entry ---------- 0\n");
+
+ /* Sort registers by save slots, so they're printed in the order
+ they appear in memory, not the order they're saved in. */
+ for (si=0; si<FIRST_PSEUDO_REGISTER; si++)
+ slot_map[si] = si;
+ for (si=0; si<FIRST_PSEUDO_REGISTER-1; si++)
+ for (sj=si+1; sj<FIRST_PSEUDO_REGISTER; sj++)
+ if (cfun->machine->reg_save_slot[slot_map[si]]
+ > cfun->machine->reg_save_slot[slot_map[sj]])
+ {
+ int t = slot_map[si];
+ slot_map[si] = slot_map[sj];
+ slot_map[sj] = t;
+ }
+
+ sp = 0;
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+ {
+ int rsize;
+ int r = slot_map[i];
+ int rss = cfun->machine->reg_save_slot[r];
+
+ if (!rss)
+ continue;
+
+ rsize = mep_reg_size(r);
+ skip = rss - (sp+rsize);
+ if (skip)
+ fprintf (file, "\t# %3d bytes for alignment\n", skip);
+ fprintf (file, "\t# %3d bytes for saved %-3s %3d($sp)\n",
+ rsize, reg_names[r], sp_offset - rss);
+ sp = rss;
+ }
+
+ skip = reg_save_size - sp;
+ if (skip)
+ fprintf (file, "\t# %3d bytes for alignment\n", skip);
+
+ if (frame_pointer_needed)
+ fprintf (file, "\t# FP ---> ---------- %d (sp-%d)\n", reg_save_size, sp_offset-reg_save_size);
+ if (local)
+ fprintf (file, "\t# %3d bytes for local vars\n", local);
+ if (ffill)
+ fprintf (file, "\t# %3d bytes for alignment\n", ffill);
+ if (crtl->outgoing_args_size)
+ fprintf (file, "\t# %3d bytes for outgoing args\n",
+ crtl->outgoing_args_size);
+ fprintf (file, "\t# SP ---> ---------- %d\n", sp_offset);
+ fprintf (file, "\t#\n");
+}
+
+
+static int mep_prevent_lp_restore = 0;
+static int mep_sibcall_epilogue = 0;
+
+void
+mep_expand_epilogue (void)
+{
+ int i, sp_offset = 0;
+ int reg_save_size = 0;
+ int frame_size;
+ int lp_temp = LP_REGNO, lp_slot = -1;
+ int really_need_stack_frame = get_frame_size() + crtl->outgoing_args_size;
+ int interrupt_handler = mep_interrupt_p ();
+
+ if (profile_arc_flag == 2)
+ emit_insn (gen_mep_bb_trace_ret ());
+
+ reg_save_size = mep_elimination_offset (ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM);
+ frame_size = mep_elimination_offset (FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM);
+
+ /* All save slots are set by mep_expand_prologue. */
+ for (i=0; i<FIRST_PSEUDO_REGISTER; i++)
+ if (mep_call_saves_register(i))
+ {
+ if ((i != TP_REGNO && i != GP_REGNO && i != LP_REGNO)
+ || mep_reg_set_in_function (i))
+ really_need_stack_frame = 1;
+ }
+
+ if (frame_pointer_needed)
+ {
+ /* If we have a frame pointer, we won't have a reliable stack
+ pointer (alloca, you know), so rebase SP from FP */
+ emit_move_insn (gen_rtx_REG (SImode, SP_REGNO),
+ gen_rtx_REG (SImode, FP_REGNO));
+ sp_offset = reg_save_size;
+ }
+ else
+ {
+ /* SP is right under our local variable space. Adjust it if
+ needed. */
+ sp_offset = reg_save_size + frame_size;
+ if (sp_offset >= 128)
+ {
+ add_constant (SP_REGNO, SP_REGNO, frame_size, 0);
+ sp_offset -= frame_size;
+ }
+ }
+
+ /* This is backwards so that we restore the control and coprocessor
+ registers before the temporary registers we use to restore
+ them. */
+ for (i=FIRST_PSEUDO_REGISTER-1; i>=1; i--)
+ if (mep_call_saves_register (i))
+ {
+ enum machine_mode rmode;
+ int rss = cfun->machine->reg_save_slot[i];
+
+ if (mep_reg_size (i) == 8)
+ rmode = DImode;
+ else
+ rmode = SImode;
+
+ if ((i == TP_REGNO || i == GP_REGNO || i == LP_REGNO)
+ && !(mep_reg_set_in_function (i) || interrupt_handler))
+ continue;
+ if (mep_prevent_lp_restore && i == LP_REGNO)
+ continue;
+ if (!mep_prevent_lp_restore
+ && !interrupt_handler
+ && (i == 10 || i == 11))
+ continue;
+
+ if (GR_REGNO_P (i) || LOADABLE_CR_REGNO_P (i))
+ emit_move_insn (gen_rtx_REG (rmode, i),
+ gen_rtx_MEM (rmode,
+ plus_constant (stack_pointer_rtx,
+ sp_offset-rss)));
+ else
+ {
+ if (i == LP_REGNO && !mep_sibcall_epilogue && !interrupt_handler)
+ /* Defer this one so we can jump indirect rather than
+ copying the RA to $lp and "ret". EH epilogues
+ automatically skip this anyway. */
+ lp_slot = sp_offset-rss;
+ else
+ {
+ emit_move_insn (gen_rtx_REG (rmode, REGSAVE_CONTROL_TEMP),
+ gen_rtx_MEM (rmode,
+ plus_constant (stack_pointer_rtx,
+ sp_offset-rss)));
+ emit_move_insn (gen_rtx_REG (rmode, i),
+ gen_rtx_REG (rmode, REGSAVE_CONTROL_TEMP));
+ }
+ }
+ }
+ if (lp_slot != -1)
+ {
+ /* Restore this one last so we know it will be in the temp
+ register when we return by jumping indirectly via the temp. */
+ emit_move_insn (gen_rtx_REG (SImode, REGSAVE_CONTROL_TEMP),
+ gen_rtx_MEM (SImode,
+ plus_constant (stack_pointer_rtx,
+ lp_slot)));
+ lp_temp = REGSAVE_CONTROL_TEMP;
+ }
+
+
+ add_constant (SP_REGNO, SP_REGNO, sp_offset, 0);
+
+ if (crtl->calls_eh_return && mep_prevent_lp_restore)
+ emit_insn (gen_addsi3 (gen_rtx_REG (SImode, SP_REGNO),
+ gen_rtx_REG (SImode, SP_REGNO),
+ cfun->machine->eh_stack_adjust));
+
+ if (mep_sibcall_epilogue)
+ return;
+
+ if (mep_disinterrupt_p ())
+ emit_insn (gen_mep_enable_int ());
+
+ if (mep_prevent_lp_restore)
+ {
+ emit_jump_insn (gen_eh_return_internal ());
+ emit_barrier ();
+ }
+ else if (interrupt_handler)
+ emit_jump_insn (gen_mep_reti ());
+ else
+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, lp_temp)));
+}
+
+void
+mep_expand_eh_return (rtx *operands)
+{
+ if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != LP_REGNO)
+ {
+ rtx ra = gen_rtx_REG (Pmode, LP_REGNO);
+ emit_move_insn (ra, operands[0]);
+ operands[0] = ra;
+ }
+
+ emit_insn (gen_eh_epilogue (operands[0]));
+}
+
+void
+mep_emit_eh_epilogue (rtx *operands ATTRIBUTE_UNUSED)
+{
+ cfun->machine->eh_stack_adjust = gen_rtx_REG (Pmode, 0);
+ mep_prevent_lp_restore = 1;
+ mep_expand_epilogue ();
+ mep_prevent_lp_restore = 0;
+}
+
+void
+mep_expand_sibcall_epilogue (void)
+{
+ mep_sibcall_epilogue = 1;
+ mep_expand_epilogue ();
+ mep_sibcall_epilogue = 0;
+}
+
+static bool
+mep_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
+{
+ if (decl == NULL)
+ return false;
+
+ if (mep_section_tag (DECL_RTL (decl)) == 'f')
+ return false;
+
+ /* Can't call to a sibcall from an interrupt or disinterrupt function. */
+ if (mep_interrupt_p () || mep_disinterrupt_p ())
+ return false;
+
+ return true;
+}
+
+rtx
+mep_return_stackadj_rtx (void)
+{
+ return gen_rtx_REG (SImode, 10);
+}
+
+rtx
+mep_return_handler_rtx (void)
+{
+ return gen_rtx_REG (SImode, LP_REGNO);
+}
+
+void
+mep_function_profiler (FILE *file)
+{
+ /* Always right at the beginning of the function. */
+ fprintf (file, "\t# mep function profiler\n");
+ fprintf (file, "\tadd\t$sp, -8\n");
+ fprintf (file, "\tsw\t$0, ($sp)\n");
+ fprintf (file, "\tldc\t$0, $lp\n");
+ fprintf (file, "\tsw\t$0, 4($sp)\n");
+ fprintf (file, "\tbsr\t__mep_mcount\n");
+ fprintf (file, "\tlw\t$0, 4($sp)\n");
+ fprintf (file, "\tstc\t$0, $lp\n");
+ fprintf (file, "\tlw\t$0, ($sp)\n");
+ fprintf (file, "\tadd\t$sp, 8\n\n");
+}
+
+const char *
+mep_emit_bb_trace_ret (void)
+{
+ fprintf (asm_out_file, "\t# end of block profiling\n");
+ fprintf (asm_out_file, "\tadd\t$sp, -8\n");
+ fprintf (asm_out_file, "\tsw\t$0, ($sp)\n");
+ fprintf (asm_out_file, "\tldc\t$0, $lp\n");
+ fprintf (asm_out_file, "\tsw\t$0, 4($sp)\n");
+ fprintf (asm_out_file, "\tbsr\t__bb_trace_ret\n");
+ fprintf (asm_out_file, "\tlw\t$0, 4($sp)\n");
+ fprintf (asm_out_file, "\tstc\t$0, $lp\n");
+ fprintf (asm_out_file, "\tlw\t$0, ($sp)\n");
+ fprintf (asm_out_file, "\tadd\t$sp, 8\n\n");
+ return "";
+}
+
+#undef SAVE
+#undef RESTORE
+\f
+/* Operand Printing. */
+
+void
+mep_print_operand_address (FILE *stream, rtx address)
+{
+ if (GET_CODE (address) == MEM)
+ address = XEXP (address, 0);
+ else
+ /* cf: gcc.dg/asm-4.c. */
+ gcc_assert (GET_CODE (address) == REG);
+
+ mep_print_operand (stream, address, 0);
+}
+
+static struct
+{
+ char code;
+ const char *pattern;
+ const char *format;
+}
+const conversions[] =
+{
+ { 0, "r", "0" },
+ { 0, "m+ri", "3(2)" },
+ { 0, "mr", "(1)" },
+ { 0, "ms", "(1)" },
+ { 0, "mLrs", "%lo(3)(2)" },
+ { 0, "mLr+si", "%lo(4+5)(2)" },
+ { 0, "m+ru2s", "%tpoff(5)(2)" },
+ { 0, "m+ru3s", "%sdaoff(5)(2)" },
+ { 0, "m+r+u2si", "%tpoff(6+7)(2)" },
+ { 0, "m+ru2+si", "%tpoff(6+7)(2)" },
+ { 0, "m+r+u3si", "%sdaoff(6+7)(2)" },
+ { 0, "m+ru3+si", "%sdaoff(6+7)(2)" },
+ { 0, "mi", "(1)" },
+ { 0, "m+si", "(2+3)" },
+ { 0, "m+li", "(2+3)" },
+ { 0, "i", "0" },
+ { 0, "s", "0" },
+ { 0, "+si", "1+2" },
+ { 0, "+u2si", "%tpoff(3+4)" },
+ { 0, "+u3si", "%sdaoff(3+4)" },
+ { 0, "l", "0" },
+ { 'b', "i", "0" },
+ { 'B', "i", "0" },
+ { 'U', "i", "0" },
+ { 'h', "i", "0" },
+ { 'h', "Hs", "%hi(1)" },
+ { 'I', "i", "0" },
+ { 'I', "u2s", "%tpoff(2)" },
+ { 'I', "u3s", "%sdaoff(2)" },
+ { 'I', "+u2si", "%tpoff(3+4)" },
+ { 'I', "+u3si", "%sdaoff(3+4)" },
+ { 'J', "i", "0" },
+ { 'P', "mr", "(1\\+),\\0" },
+ { 'x', "i", "0" },
+ { 0, 0, 0 }
+};
+
+static int
+unique_bit_in (HOST_WIDE_INT i)
+{
+ switch (i & 0xff)
+ {
+ case 0x01: case 0xfe: return 0;
+ case 0x02: case 0xfd: return 1;
+ case 0x04: case 0xfb: return 2;
+ case 0x08: case 0xf7: return 3;
+ case 0x10: case 0x7f: return 4;
+ case 0x20: case 0xbf: return 5;
+ case 0x40: case 0xdf: return 6;
+ case 0x80: case 0xef: return 7;
+ default:
+ gcc_unreachable ();
+ }
+}
+
+static int
+bit_size_for_clip (HOST_WIDE_INT i)
+{
+ int rv;
+
+ for (rv = 0; rv < 31; rv ++)
+ if (((HOST_WIDE_INT) 1 << rv) > i)
+ return rv + 1;
+ gcc_unreachable ();
+}
+
+/* Print an operand to a assembler instruction. */
+
+void
+mep_print_operand (FILE *file, rtx x, int code)
+{
+ int i, j;
+ const char *real_name;
+
+ if (code == '<')
+ {
+ /* Print a mnemonic to do CR <- CR moves. Find out which intrinsic
+ we're using, then skip over the "mep_" part of its name. */
+ const struct cgen_insn *insn;
+
+ if (mep_get_move_insn (mep_cmov, &insn))
+ fputs (cgen_intrinsics[insn->intrinsic] + 4, file);
+ else
+ mep_intrinsic_unavailable (mep_cmov);
+ return;
+ }
+ if (code == 'L')
+ {
+ switch (GET_CODE (x))
+ {
+ case AND:
+ fputs ("clr", file);
+ return;
+ case IOR:
+ fputs ("set", file);
+ return;
+ case XOR:
+ fputs ("not", file);
+ return;
+ default:
+ output_operand_lossage ("invalid %%L code");
+ }
+ }
+ if (code == 'M')
+ {
+ /* Print the second operand of a CR <- CR move. If we're using
+ a two-operand instruction (i.e., a real cmov), then just print
+ the operand normally. If we're using a "reg, reg, immediate"
+ instruction such as caddi3, print the operand followed by a
+ zero field. If we're using a three-register instruction,
+ print the operand twice. */
+ const struct cgen_insn *insn;
+
+ mep_print_operand (file, x, 0);
+ if (mep_get_move_insn (mep_cmov, &insn)
+ && insn_data[insn->icode].n_operands == 3)
+ {
+ fputs (", ", file);
+ if (insn_data[insn->icode].operand[2].predicate (x, VOIDmode))
+ mep_print_operand (file, x, 0);
+ else
+ mep_print_operand (file, const0_rtx, 0);
+ }
+ return;
+ }
+
+ encode_pattern (x);
+ for (i = 0; conversions[i].pattern; i++)
+ if (conversions[i].code == code
+ && strcmp(conversions[i].pattern, pattern) == 0)
+ {
+ for (j = 0; conversions[i].format[j]; j++)
+ if (conversions[i].format[j] == '\\')
+ {
+ fputc (conversions[i].format[j+1], file);
+ j++;
+ }
+ else if (ISDIGIT(conversions[i].format[j]))
+ {
+ rtx r = patternr[conversions[i].format[j] - '0'];
+ switch (GET_CODE (r))
+ {
+ case REG:
+ fprintf (file, "%s", reg_names [REGNO (r)]);
+ break;
+ case CONST_INT:
+ switch (code)
+ {
+ case 'b':
+ fprintf (file, "%d", unique_bit_in (INTVAL (r)));
+ break;
+ case 'B':
+ fprintf (file, "%d", bit_size_for_clip (INTVAL (r)));
+ break;
+ case 'h':
+ fprintf (file, "0x%x", ((int) INTVAL (r) >> 16) & 0xffff);
+ break;
+ case 'U':
+ fprintf (file, "%d", bit_size_for_clip (INTVAL (r)) - 1);
+ break;
+ case 'J':
+ fprintf (file, "0x%x", (int) INTVAL (r) & 0xffff);
+ break;
+ case 'x':
+ if (INTVAL (r) & ~(HOST_WIDE_INT)0xff
+ && !(INTVAL (r) & 0xff))
+ fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL(r));
+ else
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL(r));
+ break;
+ case 'I':
+ if (INTVAL (r) & ~(HOST_WIDE_INT)0xff
+ && conversions[i].format[j+1] == 0)
+ {
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (r));
+ fprintf (file, " # 0x%x", (int) INTVAL(r) & 0xffff);
+ }
+ else
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL(r));
+ break;
+ default:
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL(r));
+ break;
+ }
+ break;
+ case CONST_DOUBLE:
+ fprintf(file, "[const_double 0x%lx]",
+ (unsigned long) CONST_DOUBLE_HIGH(r));
+ break;
+ case SYMBOL_REF:
+ real_name = TARGET_STRIP_NAME_ENCODING (XSTR (r, 0));
+ assemble_name (file, real_name);
+ break;
+ case LABEL_REF:
+ output_asm_label (r);
+ break;
+ default:
+ fprintf (stderr, "don't know how to print this operand:");
+ debug_rtx (r);
+ gcc_unreachable ();
+ }
+ }
+ else
+ {
+ if (conversions[i].format[j] == '+'
+ && (!code || code == 'I')
+ && ISDIGIT (conversions[i].format[j+1])
+ && GET_CODE (patternr[conversions[i].format[j+1] - '0']) == CONST_INT
+ && INTVAL (patternr[conversions[i].format[j+1] - '0']) < 0)
+ continue;
+ fputc(conversions[i].format[j], file);
+ }
+ break;
+ }
+ if (!conversions[i].pattern)
+ {
+ error ("unconvertible operand %c %qs", code?code:'-', pattern);
+ debug_rtx(x);
+ }
+
+ return;
+}
+
+void
+mep_final_prescan_insn (rtx insn, rtx *operands ATTRIBUTE_UNUSED,
+ int noperands ATTRIBUTE_UNUSED)
+{
+ /* Despite the fact that MeP is perfectly capable of branching and
+ doing something else in the same bundle, gcc does jump
+ optimization *after* scheduling, so we cannot trust the bundling
+ flags on jump instructions. */
+ if (GET_MODE (insn) == BImode
+ && get_attr_slots (insn) != SLOTS_CORE)
+ fputc ('+', asm_out_file);
+}
+
+/* Function args in registers. */
+
+static void
+mep_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ tree type ATTRIBUTE_UNUSED, int *pretend_size,
+ int second_time ATTRIBUTE_UNUSED)
+{
+ int nsave = 4 - (cum->nregs + 1);
+
+ if (nsave > 0)
+ cfun->machine->arg_regs_to_save = nsave;
+ *pretend_size = nsave * 4;
+}
+
+static int
+bytesize (const_tree type, enum machine_mode mode)
+{
+ if (mode == BLKmode)
+ return int_size_in_bytes (type);
+ return GET_MODE_SIZE (mode);
+}
+
+static rtx
+mep_expand_builtin_saveregs (void)
+{
+ int bufsize, i, ns;
+ rtx regbuf;
+
+ ns = cfun->machine->arg_regs_to_save;
+ bufsize = ns * (TARGET_IVC2 ? 12 : 4);
+ regbuf = assign_stack_local (SImode, bufsize, 32);
+
+ move_block_from_reg (5-ns, regbuf, ns);
+
+ if (TARGET_IVC2)
+ {
+ rtx tmp = gen_rtx_MEM (DImode, XEXP (regbuf, 0));
+ int ofs = 4 * ns;
+
+ for (i=0; i<ns; i++)
+ {
+ int rn = (4-ns) + i + 49;
+ rtx ptr;
+
+ ptr = offset_address (tmp, GEN_INT (ofs), 2);
+ emit_move_insn (ptr, gen_rtx_REG (DImode, rn));
+ ofs += 8;
+ }
+ }
+ return XEXP (regbuf, 0);
+}
+
+#define VECTOR_TYPE_P(t) (TREE_CODE(t) == VECTOR_TYPE)
+
+static tree
+mep_build_builtin_va_list (void)
+{
+ tree f_next_gp, f_next_gp_limit, f_next_cop, f_next_stack;
+ tree record;
+
+
+ record = (*lang_hooks.types.make_type) (RECORD_TYPE);
+
+ f_next_gp = build_decl (BUILTINS_LOCATION, FIELD_DECL,
+ get_identifier ("__va_next_gp"), ptr_type_node);
+ f_next_gp_limit = build_decl (BUILTINS_LOCATION, FIELD_DECL,
+ get_identifier ("__va_next_gp_limit"),
+ ptr_type_node);
+ f_next_cop = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("__va_next_cop"),
+ ptr_type_node);
+ f_next_stack = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("__va_next_stack"),
+ ptr_type_node);
+
+ DECL_FIELD_CONTEXT (f_next_gp) = record;
+ DECL_FIELD_CONTEXT (f_next_gp_limit) = record;
+ DECL_FIELD_CONTEXT (f_next_cop) = record;
+ DECL_FIELD_CONTEXT (f_next_stack) = record;
+
+ TYPE_FIELDS (record) = f_next_gp;
+ TREE_CHAIN (f_next_gp) = f_next_gp_limit;
+ TREE_CHAIN (f_next_gp_limit) = f_next_cop;
+ TREE_CHAIN (f_next_cop) = f_next_stack;
+
+ layout_type (record);
+
+ return record;
+}
+
+static void
+mep_expand_va_start (tree valist, rtx nextarg)
+{
+ tree f_next_gp, f_next_gp_limit, f_next_cop, f_next_stack;
+ tree next_gp, next_gp_limit, next_cop, next_stack;
+ tree t, u;
+ int ns;
+
+ ns = cfun->machine->arg_regs_to_save;
+
+ f_next_gp = TYPE_FIELDS (va_list_type_node);
+ f_next_gp_limit = TREE_CHAIN (f_next_gp);
+ f_next_cop = TREE_CHAIN (f_next_gp_limit);
+ f_next_stack = TREE_CHAIN (f_next_cop);
+
+ next_gp = build3 (COMPONENT_REF, TREE_TYPE (f_next_gp), valist, f_next_gp,
+ NULL_TREE);
+ next_gp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_gp_limit),
+ valist, f_next_gp_limit, NULL_TREE);
+ next_cop = build3 (COMPONENT_REF, TREE_TYPE (f_next_cop), valist, f_next_cop,
+ NULL_TREE);
+ next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
+ valist, f_next_stack, NULL_TREE);
+
+ /* va_list.next_gp = expand_builtin_saveregs (); */
+ u = make_tree (sizetype, expand_builtin_saveregs ());
+ u = fold_convert (ptr_type_node, u);
+ t = build2 (MODIFY_EXPR, ptr_type_node, next_gp, u);
+ TREE_SIDE_EFFECTS (t) = 1;
+ expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+
+ /* va_list.next_gp_limit = va_list.next_gp + 4 * ns; */
+ u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
+ size_int (4 * ns));
+ t = build2 (MODIFY_EXPR, ptr_type_node, next_gp_limit, u);
+ TREE_SIDE_EFFECTS (t) = 1;
+ expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+
+ /* va_list.next_cop = va_list.next_gp_limit; */
+ t = build2 (MODIFY_EXPR, ptr_type_node, next_cop, u);
+ TREE_SIDE_EFFECTS (t) = 1;
+ expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+
+ /* va_list.next_stack = nextarg; */
+ u = make_tree (ptr_type_node, nextarg);
+ t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
+ TREE_SIDE_EFFECTS (t) = 1;
+ expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+}
+
+static tree
+mep_gimplify_va_arg_expr (tree valist, tree type,
+ tree *pre_p, tree *post_p ATTRIBUTE_UNUSED)
+{
+ HOST_WIDE_INT size, rsize;
+ bool by_reference, ivc2_vec;
+ tree f_next_gp, f_next_gp_limit, f_next_cop, f_next_stack;
+ tree next_gp, next_gp_limit, next_cop, next_stack;
+ tree label_sover, label_selse;
+ tree tmp, res_addr;
+
+ ivc2_vec = TARGET_IVC2 && VECTOR_TYPE_P (type);
+
+ size = int_size_in_bytes (type);
+ by_reference = (size > (ivc2_vec ? 8 : 4)) || (size <= 0);
+
+ if (by_reference)
+ {
+ type = build_pointer_type (type);
+ size = 4;
+ }
+ rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
+
+ f_next_gp = TYPE_FIELDS (va_list_type_node);
+ f_next_gp_limit = TREE_CHAIN (f_next_gp);
+ f_next_cop = TREE_CHAIN (f_next_gp_limit);
+ f_next_stack = TREE_CHAIN (f_next_cop);
+
+ next_gp = build3 (COMPONENT_REF, TREE_TYPE (f_next_gp), valist, f_next_gp,
+ NULL_TREE);
+ next_gp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_gp_limit),
+ valist, f_next_gp_limit, NULL_TREE);
+ next_cop = build3 (COMPONENT_REF, TREE_TYPE (f_next_cop), valist, f_next_cop,
+ NULL_TREE);
+ next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
+ valist, f_next_stack, NULL_TREE);
+
+ /* if f_next_gp < f_next_gp_limit
+ IF (VECTOR_P && IVC2)
+ val = *f_next_cop;
+ ELSE
+ val = *f_next_gp;
+ f_next_gp += 4;
+ f_next_cop += 8;
+ else
+ label_selse:
+ val = *f_next_stack;
+ f_next_stack += rsize;
+ label_sover:
+ */
+
+ label_sover = create_artificial_label (UNKNOWN_LOCATION);
+ label_selse = create_artificial_label (UNKNOWN_LOCATION);
+ res_addr = create_tmp_var (ptr_type_node, NULL);
+
+ tmp = build2 (GE_EXPR, boolean_type_node, next_gp,
+ unshare_expr (next_gp_limit));
+ tmp = build3 (COND_EXPR, void_type_node, tmp,
+ build1 (GOTO_EXPR, void_type_node,
+ unshare_expr (label_selse)),
+ NULL_TREE);
+ gimplify_and_add (tmp, pre_p);
+
+ if (ivc2_vec)
+ {
+ tmp = build2 (MODIFY_EXPR, void_type_node, res_addr, next_cop);
+ gimplify_and_add (tmp, pre_p);
+ }
+ else
+ {
+ tmp = build2 (MODIFY_EXPR, void_type_node, res_addr, next_gp);
+ gimplify_and_add (tmp, pre_p);
+ }
+
+ tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
+ unshare_expr (next_gp), size_int (4));
+ gimplify_assign (unshare_expr (next_gp), tmp, pre_p);
+
+ tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
+ unshare_expr (next_cop), size_int (8));
+ gimplify_assign (unshare_expr (next_cop), tmp, pre_p);
+
+ tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (label_sover));
+ gimplify_and_add (tmp, pre_p);
+
+ /* - - */
+
+ tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (label_selse));
+ gimplify_and_add (tmp, pre_p);
+
+ tmp = build2 (MODIFY_EXPR, void_type_node, res_addr, unshare_expr (next_stack));
+ gimplify_and_add (tmp, pre_p);
+
+ tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
+ unshare_expr (next_stack), size_int (rsize));
+ gimplify_assign (unshare_expr (next_stack), tmp, pre_p);
+
+ /* - - */
+
+ tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (label_sover));
+ gimplify_and_add (tmp, pre_p);
+
+ res_addr = fold_convert (build_pointer_type (type), res_addr);
+
+ if (by_reference)
+ res_addr = build_va_arg_indirect_ref (res_addr);
+
+ return build_va_arg_indirect_ref (res_addr);
+}
+
+void
+mep_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
+ rtx libname ATTRIBUTE_UNUSED,
+ tree fndecl ATTRIBUTE_UNUSED)
+{
+ pcum->nregs = 0;
+
+ if (fntype && lookup_attribute ("vliw", TYPE_ATTRIBUTES (fntype)))
+ pcum->vliw = 1;
+ else
+ pcum->vliw = 0;
+}
+
+rtx
+mep_function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode,
+ tree type ATTRIBUTE_UNUSED, int named ATTRIBUTE_UNUSED)
+{
+ /* VOIDmode is a signal for the backend to pass data to the call
+ expander via the second operand to the call pattern. We use
+ this to determine whether to use "jsr" or "jsrv". */
+ if (mode == VOIDmode)
+ return GEN_INT (cum.vliw);
+
+ /* If we havn't run out of argument registers, return the next. */
+ if (cum.nregs < 4)
+ {
+ if (type && TARGET_IVC2 && VECTOR_TYPE_P (type))
+ return gen_rtx_REG (mode, cum.nregs + 49);
+ else
+ return gen_rtx_REG (mode, cum.nregs + 1);
+ }
+
+ /* Otherwise the argument goes on the stack. */
+ return NULL_RTX;
+}
+
+static bool
+mep_pass_by_reference (CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED,
+ enum machine_mode mode,
+ const_tree type,
+ bool named ATTRIBUTE_UNUSED)
+{
+ int size = bytesize (type, mode);
+ if (type && TARGET_IVC2 && cum->nregs < 4 && VECTOR_TYPE_P (type))
+ return size <= 0 || size > 8;
+ return size <= 0 || size > 4;
+}
+
+void
+mep_arg_advance (CUMULATIVE_ARGS *pcum,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ tree type ATTRIBUTE_UNUSED, int named ATTRIBUTE_UNUSED)
+{
+ pcum->nregs += 1;
+}
+
+bool
+mep_return_in_memory (const_tree type, const_tree decl ATTRIBUTE_UNUSED)
+{
+ int size = bytesize (type, BLKmode);
+ if (TARGET_IVC2 && VECTOR_TYPE_P (type))
+ return size >= 0 && size <= 8 ? 0 : 1;
+ return size >= 0 && size <= 4 ? 0 : 1;
+}
+
+static bool
+mep_narrow_volatile_bitfield (void)
+{
+ return true;
+ return false;
+}
+
+/* Implement FUNCTION_VALUE. All values are returned in $0. */
+
+rtx
+mep_function_value (tree type, tree func ATTRIBUTE_UNUSED)
+{
+ if (TARGET_IVC2 && VECTOR_TYPE_P (type))
+ return gen_rtx_REG (TYPE_MODE (type), 48);
+ return gen_rtx_REG (TYPE_MODE (type), RETURN_VALUE_REGNUM);
+}
+
+/* Implement LIBCALL_VALUE, using the same rules as mep_function_value. */
+
+rtx
+mep_libcall_value (enum machine_mode mode)
+{
+ return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
+}
+
+/* Handle pipeline hazards. */
+
+typedef enum { op_none, op_stc, op_fsft, op_ret } op_num;
+static const char *opnames[] = { "", "stc", "fsft", "ret" };
+
+static int prev_opcode = 0;
+
+/* This isn't as optimal as it could be, because we don't know what
+ control register the STC opcode is storing in. We only need to add
+ the nop if it's the relevent register, but we add it for irrelevent
+ registers also. */
+
+void
+mep_asm_output_opcode (FILE *file, const char *ptr)
+{
+ int this_opcode = op_none;
+ const char *hazard = 0;
+
+ switch (*ptr)
+ {
+ case 'f':
+ if (strncmp (ptr, "fsft", 4) == 0 && !ISGRAPH (ptr[4]))
+ this_opcode = op_fsft;
+ break;
+ case 'r':
+ if (strncmp (ptr, "ret", 3) == 0 && !ISGRAPH (ptr[3]))
+ this_opcode = op_ret;
+ break;
+ case 's':
+ if (strncmp (ptr, "stc", 3) == 0 && !ISGRAPH (ptr[3]))
+ this_opcode = op_stc;
+ break;
+ }
+
+ if (prev_opcode == op_stc && this_opcode == op_fsft)
+ hazard = "nop";
+ if (prev_opcode == op_stc && this_opcode == op_ret)
+ hazard = "nop";
+
+ if (hazard)
+ fprintf(file, "%s\t# %s-%s hazard\n\t",
+ hazard, opnames[prev_opcode], opnames[this_opcode]);
+
+ prev_opcode = this_opcode;
+}
+
+/* Handle attributes. */
+
+static tree
+mep_validate_based_tiny (tree *node, tree name, tree args,
+ int flags ATTRIBUTE_UNUSED, bool *no_add)
+{
+ if (TREE_CODE (*node) != VAR_DECL
+ && TREE_CODE (*node) != POINTER_TYPE
+ && TREE_CODE (*node) != TYPE_DECL)
+ {
+ warning (0, "%qE attribute only applies to variables", name);
+ *no_add = true;
+ }
+ else if (args == NULL_TREE && TREE_CODE (*node) == VAR_DECL)
+ {
+ if (! (TREE_PUBLIC (*node) || TREE_STATIC (*node)))
+ {
+ warning (0, "address region attributes not allowed with auto storage class");
+ *no_add = true;
+ }
+ /* Ignore storage attribute of pointed to variable: char __far * x; */
+ if (TREE_TYPE (*node) && TREE_CODE (TREE_TYPE (*node)) == POINTER_TYPE)
+ {
+ warning (0, "address region attributes on pointed-to types ignored");
+ *no_add = true;
+ }
+ }
+
+ return NULL_TREE;
+}
+
+static int
+mep_multiple_address_regions (tree list, bool check_section_attr)
+{
+ tree a;
+ int count_sections = 0;
+ int section_attr_count = 0;
+
+ for (a = list; a; a = TREE_CHAIN (a))
+ {
+ if (is_attribute_p ("based", TREE_PURPOSE (a))
+ || is_attribute_p ("tiny", TREE_PURPOSE (a))
+ || is_attribute_p ("near", TREE_PURPOSE (a))
+ || is_attribute_p ("far", TREE_PURPOSE (a))
+ || is_attribute_p ("io", TREE_PURPOSE (a)))
+ count_sections ++;
+ if (check_section_attr)
+ section_attr_count += is_attribute_p ("section", TREE_PURPOSE (a));
+ }
+
+ if (check_section_attr)
+ return section_attr_count;
+ else
+ return count_sections;
+}
+
+#define MEP_ATTRIBUTES(decl) \
+ (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
+ : DECL_ATTRIBUTES (decl) \
+ ? (DECL_ATTRIBUTES (decl)) \
+ : TYPE_ATTRIBUTES (TREE_TYPE (decl))
+
+static tree
+mep_validate_near_far (tree *node, tree name, tree args,
+ int flags ATTRIBUTE_UNUSED, bool *no_add)
+{
+ if (TREE_CODE (*node) != VAR_DECL
+ && TREE_CODE (*node) != FUNCTION_DECL
+ && TREE_CODE (*node) != METHOD_TYPE
+ && TREE_CODE (*node) != POINTER_TYPE
+ && TREE_CODE (*node) != TYPE_DECL)
+ {
+ warning (0, "%qE attribute only applies to variables and functions",
+ name);
+ *no_add = true;
+ }
+ else if (args == NULL_TREE && TREE_CODE (*node) == VAR_DECL)
+ {
+ if (! (TREE_PUBLIC (*node) || TREE_STATIC (*node)))
+ {
+ warning (0, "address region attributes not allowed with auto storage class");
+ *no_add = true;
+ }
+ /* Ignore storage attribute of pointed to variable: char __far * x; */
+ if (TREE_TYPE (*node) && TREE_CODE (TREE_TYPE (*node)) == POINTER_TYPE)
+ {
+ warning (0, "address region attributes on pointed-to types ignored");
+ *no_add = true;
+ }
+ }
+ else if (mep_multiple_address_regions (MEP_ATTRIBUTES (*node), false) > 0)
+ {
+ warning (0, "duplicate address region attribute %qE in declaration of %qE on line %d",
+ name, DECL_NAME (*node), DECL_SOURCE_LINE (*node));
+ DECL_ATTRIBUTES (*node) = NULL_TREE;
+ }
+ return NULL_TREE;
+}
+
+static tree
+mep_validate_disinterrupt (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
+ int flags ATTRIBUTE_UNUSED, bool *no_add)
+{
+ if (TREE_CODE (*node) != FUNCTION_DECL
+ && TREE_CODE (*node) != METHOD_TYPE)
+ {
+ warning (0, "%qE attribute only applies to functions", name);
+ *no_add = true;
+ }
+ return NULL_TREE;
+}
+
+static tree
+mep_validate_interrupt (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
+ int flags ATTRIBUTE_UNUSED, bool *no_add)
+{
+ tree function_type;
+
+ if (TREE_CODE (*node) != FUNCTION_DECL)
+ {
+ warning (0, "%qE attribute only applies to functions", name);
+ *no_add = true;
+ return NULL_TREE;
+ }
+
+ if (DECL_DECLARED_INLINE_P (*node))
+ error ("cannot inline interrupt function %qE", DECL_NAME (*node));
+ DECL_UNINLINABLE (*node) = 1;
+
+ function_type = TREE_TYPE (*node);
+
+ if (TREE_TYPE (function_type) != void_type_node)
+ error ("interrupt function must have return type of void");
+
+ if (TYPE_ARG_TYPES (function_type)
+ && (TREE_VALUE (TYPE_ARG_TYPES (function_type)) != void_type_node
+ || TREE_CHAIN (TYPE_ARG_TYPES (function_type)) != NULL_TREE))
+ error ("interrupt function must have no arguments");
+
+ return NULL_TREE;
+}
+
+static tree
+mep_validate_io_cb (tree *node, tree name, tree args,
+ int flags ATTRIBUTE_UNUSED, bool *no_add)
+{
+ if (TREE_CODE (*node) != VAR_DECL)
+ {
+ warning (0, "%qE attribute only applies to variables", name);
+ *no_add = true;
+ }
+
+ if (args != NULL_TREE)
+ {
+ if (TREE_CODE (TREE_VALUE (args)) == NON_LVALUE_EXPR)
+ TREE_VALUE (args) = TREE_OPERAND (TREE_VALUE (args), 0);
+ if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
+ {
+ warning (0, "%qE attribute allows only an integer constant argument",
+ name);
+ *no_add = true;
+ }
+ }
+
+ if (*no_add == false && !TARGET_IO_NO_VOLATILE)
+ TREE_THIS_VOLATILE (*node) = 1;
+
+ return NULL_TREE;
+}
+
+static tree
+mep_validate_vliw (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
+ int flags ATTRIBUTE_UNUSED, bool *no_add)
+{
+ if (TREE_CODE (*node) != FUNCTION_TYPE
+ && TREE_CODE (*node) != FUNCTION_DECL
+ && TREE_CODE (*node) != METHOD_TYPE
+ && TREE_CODE (*node) != FIELD_DECL
+ && TREE_CODE (*node) != TYPE_DECL)
+ {
+ static int gave_pointer_note = 0;
+ static int gave_array_note = 0;
+ static const char * given_type = NULL;
+
+ given_type = tree_code_name[TREE_CODE (*node)];
+ if (TREE_CODE (*node) == POINTER_TYPE)
+ given_type = "pointers";
+ if (TREE_CODE (*node) == ARRAY_TYPE)
+ given_type = "arrays";
+
+ if (given_type)
+ warning (0, "%qE attribute only applies to functions, not %s",
+ name, given_type);
+ else
+ warning (0, "%qE attribute only applies to functions",
+ name);
+ *no_add = true;
+
+ if (TREE_CODE (*node) == POINTER_TYPE
+ && !gave_pointer_note)
+ {
+ inform (input_location, "To describe a pointer to a VLIW function, use syntax like this:");
+ inform (input_location, " typedef int (__vliw *vfuncptr) ();");
+ gave_pointer_note = 1;
+ }
+
+ if (TREE_CODE (*node) == ARRAY_TYPE
+ && !gave_array_note)
+ {
+ inform (input_location, "To describe an array of VLIW function pointers, use syntax like this:");
+ inform (input_location, " typedef int (__vliw *vfuncptr[]) ();");
+ gave_array_note = 1;
+ }
+ }
+ if (!TARGET_VLIW)
+ error ("VLIW functions are not allowed without a VLIW configuration");
+ return NULL_TREE;
+}
+
+static const struct attribute_spec mep_attribute_table[11] =
+{
+ /* name min max decl type func handler */
+ { "based", 0, 0, false, false, false, mep_validate_based_tiny },
+ { "tiny", 0, 0, false, false, false, mep_validate_based_tiny },
+ { "near", 0, 0, false, false, false, mep_validate_near_far },
+ { "far", 0, 0, false, false, false, mep_validate_near_far },
+ { "disinterrupt", 0, 0, false, false, false, mep_validate_disinterrupt },
+ { "interrupt", 0, 0, false, false, false, mep_validate_interrupt },
+ { "io", 0, 1, false, false, false, mep_validate_io_cb },
+ { "cb", 0, 1, false, false, false, mep_validate_io_cb },
+ { "vliw", 0, 0, false, true, false, mep_validate_vliw },
+ { NULL, 0, 0, false, false, false, NULL }
+};
+
+static bool
+mep_function_attribute_inlinable_p (const_tree callee)
+{
+ tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (callee));
+ if (!attrs) attrs = DECL_ATTRIBUTES (callee);
+ return (lookup_attribute ("disinterrupt", attrs) == 0
+ && lookup_attribute ("interrupt", attrs) == 0);
+}
+
+#define FUNC_CALL 1
+#define FUNC_DISINTERRUPT 2
+
+
+struct GTY(()) pragma_entry {
+ int used;
+ int flag;
+ const char *funcname;
+};
+typedef struct pragma_entry pragma_entry;
+
+/* Hash table of farcall-tagged sections. */
+static GTY((param_is (pragma_entry))) htab_t pragma_htab;
+
+static int
+pragma_entry_eq (const void *p1, const void *p2)
+{
+ const pragma_entry *old = (const pragma_entry *) p1;
+ const char *new_name = (const char *) p2;
+
+ return strcmp (old->funcname, new_name) == 0;
+}
+
+static hashval_t
+pragma_entry_hash (const void *p)
+{
+ const pragma_entry *old = (const pragma_entry *) p;
+ return htab_hash_string (old->funcname);
+}
+
+static void
+mep_note_pragma_flag (const char *funcname, int flag)
+{
+ pragma_entry **slot;
+
+ if (!pragma_htab)
+ pragma_htab = htab_create_ggc (31, pragma_entry_hash,
+ pragma_entry_eq, NULL);
+
+ slot = (pragma_entry **)
+ htab_find_slot_with_hash (pragma_htab, funcname,
+ htab_hash_string (funcname), INSERT);
+
+ if (!*slot)
+ {
+ *slot = GGC_NEW (pragma_entry);
+ (*slot)->flag = 0;
+ (*slot)->used = 0;
+ (*slot)->funcname = ggc_strdup (funcname);
+ }
+ (*slot)->flag |= flag;
+}
+
+static bool
+mep_lookup_pragma_flag (const char *funcname, int flag)
+{
+ pragma_entry **slot;
+
+ if (!pragma_htab)
+ return false;
+
+ if (funcname[0] == '@' && funcname[2] == '.')
+ funcname += 3;
+
+ slot = (pragma_entry **)
+ htab_find_slot_with_hash (pragma_htab, funcname,
+ htab_hash_string (funcname), NO_INSERT);
+ if (slot && *slot && ((*slot)->flag & flag))
+ {
+ (*slot)->used |= flag;
+ return true;
+ }
+ return false;
+}
+
+bool
+mep_lookup_pragma_call (const char *funcname)
+{
+ return mep_lookup_pragma_flag (funcname, FUNC_CALL);
+}
+
+void
+mep_note_pragma_call (const char *funcname)
+{
+ mep_note_pragma_flag (funcname, FUNC_CALL);
+}
+
+bool
+mep_lookup_pragma_disinterrupt (const char *funcname)
+{
+ return mep_lookup_pragma_flag (funcname, FUNC_DISINTERRUPT);
+}
+
+void
+mep_note_pragma_disinterrupt (const char *funcname)
+{
+ mep_note_pragma_flag (funcname, FUNC_DISINTERRUPT);
+}
+
+static int
+note_unused_pragma_disinterrupt (void **slot, void *data ATTRIBUTE_UNUSED)
+{
+ const pragma_entry *d = (const pragma_entry *)(*slot);
+
+ if ((d->flag & FUNC_DISINTERRUPT)
+ && !(d->used & FUNC_DISINTERRUPT))
+ warning (0, "\"#pragma disinterrupt %s\" not used", d->funcname);
+ return 1;
+}
+
+void
+mep_file_cleanups (void)
+{
+ if (pragma_htab)
+ htab_traverse (pragma_htab, note_unused_pragma_disinterrupt, NULL);
+}
+
+
+static int
+mep_attrlist_to_encoding (tree list, tree decl)
+{
+ if (mep_multiple_address_regions (list, false) > 1)
+ {
+ warning (0, "duplicate address region attribute %qE in declaration of %qE on line %d",
+ TREE_PURPOSE (TREE_CHAIN (list)),
+ DECL_NAME (decl),
+ DECL_SOURCE_LINE (decl));
+ TREE_CHAIN (list) = NULL_TREE;
+ }
+
+ while (list)
+ {
+ if (is_attribute_p ("based", TREE_PURPOSE (list)))
+ return 'b';
+ if (is_attribute_p ("tiny", TREE_PURPOSE (list)))
+ return 't';
+ if (is_attribute_p ("near", TREE_PURPOSE (list)))
+ return 'n';
+ if (is_attribute_p ("far", TREE_PURPOSE (list)))
+ return 'f';
+ if (is_attribute_p ("io", TREE_PURPOSE (list)))
+ {
+ if (TREE_VALUE (list)
+ && TREE_VALUE (TREE_VALUE (list))
+ && TREE_CODE (TREE_VALUE (TREE_VALUE (list))) == INTEGER_CST)
+ {
+ int location = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE(list)));
+ if (location >= 0
+ && location <= 0x1000000)
+ return 'i';
+ }
+ return 'I';
+ }
+ if (is_attribute_p ("cb", TREE_PURPOSE (list)))
+ return 'c';
+ list = TREE_CHAIN (list);
+ }
+ if (TARGET_TF
+ && TREE_CODE (decl) == FUNCTION_DECL
+ && DECL_SECTION_NAME (decl) == 0)
+ return 'f';
+ return 0;
+}
+
+static int
+mep_comp_type_attributes (const_tree t1, const_tree t2)
+{
+ int vliw1, vliw2;
+
+ vliw1 = (lookup_attribute ("vliw", TYPE_ATTRIBUTES (t1)) != 0);
+ vliw2 = (lookup_attribute ("vliw", TYPE_ATTRIBUTES (t2)) != 0);
+
+ if (vliw1 != vliw2)
+ return 0;
+
+ return 1;
+}
+
+static void
+mep_insert_attributes (tree decl, tree *attributes)
+{
+ int size;
+ const char *secname = 0;
+ tree attrib, attrlist;
+ char encoding;
+
+ if (TREE_CODE (decl) == FUNCTION_DECL)
+ {
+ const char *funcname = IDENTIFIER_POINTER (DECL_NAME (decl));
+
+ if (mep_lookup_pragma_disinterrupt (funcname))
+ {
+ attrib = build_tree_list (get_identifier ("disinterrupt"), NULL_TREE);
+ *attributes = chainon (*attributes, attrib);
+ }
+ }
+
+ if (TREE_CODE (decl) != VAR_DECL
+ || ! (TREE_PUBLIC (decl) || TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
+ return;
+
+ if (TREE_READONLY (decl) && TARGET_DC)
+ /* -mdc means that const variables default to the near section,
+ regardless of the size cutoff. */
+ return;
+
+ /* User specified an attribute, so override the default.
+ Ignore storage attribute of pointed to variable. char __far * x; */
+ if (! (TREE_TYPE (decl) && TREE_CODE (TREE_TYPE (decl)) == POINTER_TYPE))
+ {
+ if (TYPE_P (decl) && TYPE_ATTRIBUTES (decl) && *attributes)
+ TYPE_ATTRIBUTES (decl) = NULL_TREE;
+ else if (DECL_ATTRIBUTES (decl) && *attributes)
+ DECL_ATTRIBUTES (decl) = NULL_TREE;
+ }
+
+ attrlist = *attributes ? *attributes : DECL_ATTRIBUTES (decl);
+ encoding = mep_attrlist_to_encoding (attrlist, decl);
+ if (!encoding && TYPE_P (TREE_TYPE (decl)))
+ {
+ attrlist = TYPE_ATTRIBUTES (TREE_TYPE (decl));
+ encoding = mep_attrlist_to_encoding (attrlist, decl);
+ }
+ if (encoding)
+ {
+ /* This means that the declaration has a specific section
+ attribute, so we should not apply the default rules. */
+
+ if (encoding == 'i' || encoding == 'I')
+ {
+ tree attr = lookup_attribute ("io", attrlist);
+ if (attr
+ && TREE_VALUE (attr)
+ && TREE_VALUE (TREE_VALUE(attr)))
+ {
+ int location = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE(attr)));
+ static tree previous_value = 0;
+ static int previous_location = 0;
+ static tree previous_name = 0;
+
+ /* We take advantage of the fact that gcc will reuse the
+ same tree pointer when applying an attribute to a
+ list of decls, but produce a new tree for attributes
+ on separate source lines, even when they're textually
+ identical. This is the behavior we want. */
+ if (TREE_VALUE (attr) == previous_value
+ && location == previous_location)
+ {
+ warning(0, "__io address 0x%x is the same for %qE and %qE",
+ location, previous_name, DECL_NAME (decl));
+ }
+ previous_name = DECL_NAME (decl);
+ previous_location = location;
+ previous_value = TREE_VALUE (attr);
+ }
+ }
+ return;
+ }
+
+
+ /* Declarations of arrays can change size. Don't trust them. */
+ if (TREE_CODE (TREE_TYPE (decl)) == ARRAY_TYPE)
+ size = 0;
+ else
+ size = int_size_in_bytes (TREE_TYPE (decl));
+
+ if (TARGET_RAND_TPGP && size <= 4 && size > 0)
+ {
+ if (TREE_PUBLIC (decl)
+ || DECL_EXTERNAL (decl)
+ || TREE_STATIC (decl))
+ {
+ const char *name = IDENTIFIER_POINTER (DECL_NAME (decl));
+ int key = 0;
+
+ while (*name)
+ key += *name++;
+
+ switch (key & 3)
+ {
+ case 0:
+ secname = "based";
+ break;
+ case 1:
+ secname = "tiny";
+ break;
+ case 2:
+ secname = "far";
+ break;
+ default:
+ ;
+ }
+ }
+ }
+ else
+ {
+ if (size <= mep_based_cutoff && size > 0)
+ secname = "based";
+ else if (size <= mep_tiny_cutoff && size > 0)
+ secname = "tiny";
+ else if (TARGET_L)
+ secname = "far";
+ }
+
+ if (mep_const_section && TREE_READONLY (decl))
+ {
+ if (strcmp (mep_const_section, "tiny") == 0)
+ secname = "tiny";
+ else if (strcmp (mep_const_section, "near") == 0)
+ return;
+ else if (strcmp (mep_const_section, "far") == 0)
+ secname = "far";
+ }
+
+ if (!secname)
+ return;
+
+ if (!mep_multiple_address_regions (*attributes, true)
+ && !mep_multiple_address_regions (DECL_ATTRIBUTES (decl), false))
+ {
+ attrib = build_tree_list (get_identifier (secname), NULL_TREE);
+
+ /* Chain the attribute directly onto the variable's DECL_ATTRIBUTES
+ in order to avoid the POINTER_TYPE bypasses in mep_validate_near_far
+ and mep_validate_based_tiny. */
+ DECL_ATTRIBUTES (decl) = chainon (DECL_ATTRIBUTES (decl), attrib);
+ }
+}
+
+static void
+mep_encode_section_info (tree decl, rtx rtl, int first)
+{
+ rtx rtlname;
+ const char *oldname;
+ const char *secname;
+ char encoding;
+ char *newname;
+ tree idp;
+ int maxsize;
+ tree type;
+ tree mep_attributes;
+
+ if (! first)
+ return;
+
+ if (TREE_CODE (decl) != VAR_DECL
+ && TREE_CODE (decl) != FUNCTION_DECL)
+ return;
+
+ rtlname = XEXP (rtl, 0);
+ if (GET_CODE (rtlname) == SYMBOL_REF)
+ oldname = XSTR (rtlname, 0);
+ else if (GET_CODE (rtlname) == MEM
+ && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
+ oldname = XSTR (XEXP (rtlname, 0), 0);
+ else
+ gcc_unreachable ();
+
+ type = TREE_TYPE (decl);
+ if (type == error_mark_node)
+ return;
+ mep_attributes = MEP_ATTRIBUTES (decl);
+
+ encoding = mep_attrlist_to_encoding (mep_attributes, decl);
+
+ if (encoding)
+ {
+ newname = (char *) alloca (strlen (oldname) + 4);
+ sprintf (newname, "@%c.%s", encoding, oldname);
+ idp = get_identifier (newname);
+ XEXP (rtl, 0) =
+ gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp));
+
+ switch (encoding)
+ {
+ case 'b':
+ maxsize = 128;
+ secname = "based";
+ break;
+ case 't':
+ maxsize = 65536;
+ secname = "tiny";
+ break;
+ case 'n':
+ maxsize = 0x1000000;
+ secname = "near";
+ break;
+ default:
+ maxsize = 0;
+ secname = 0;
+ break;
+ }
+ if (maxsize && int_size_in_bytes (TREE_TYPE (decl)) > maxsize)
+ {
+ warning (0, "variable %s (%ld bytes) is too large for the %s section (%d bytes)",
+ oldname,
+ (long) int_size_in_bytes (TREE_TYPE (decl)),
+ secname,
+ maxsize);
+ }
+ }
+
+ /* Functions do not go through select_section, so we force it here
+ by using the DECL_SECTION_NAME as if the user specified the
+ .vtext or .ftext sections. */
+ if (! DECL_SECTION_NAME (decl)
+ && TREE_CODE (decl) == FUNCTION_DECL)
+ {
+ tree secname;
+
+ if (lookup_attribute ("vliw", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
+ {
+ if (encoding == 'f')
+ DECL_SECTION_NAME (decl) = build_string (7, ".vftext");
+ else
+ DECL_SECTION_NAME (decl) = build_string (6, ".vtext");
+ }
+ else if (encoding == 'f')
+ {
+ if (flag_function_sections || DECL_ONE_ONLY (decl))
+ mep_unique_section (decl, 0);
+ else
+ DECL_SECTION_NAME (decl) = build_string (6, ".ftext");
+ }
+
+ /* This is so we can control inlining. It does not matter what
+ attribute we add, just that it has one. */
+ secname = build_tree_list (get_identifier ("section"), DECL_SECTION_NAME (decl));
+ if (TYPE_P (decl))
+ TYPE_ATTRIBUTES (decl) = chainon (TYPE_ATTRIBUTES (decl), secname);
+ else
+ DECL_ATTRIBUTES (decl) = chainon (DECL_ATTRIBUTES (decl), secname);
+ }
+}
+
+const char *
+mep_strip_name_encoding (const char *sym)
+{
+ while (1)
+ {
+ if (*sym == '*')
+ sym++;
+ else if (*sym == '@' && sym[2] == '.')
+ sym += 3;
+ else
+ return sym;
+ }
+}
+
+static section *
+mep_select_section (tree decl, int reloc ATTRIBUTE_UNUSED,
+ unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
+{
+ int readonly = 1;
+
+ switch (TREE_CODE (decl))
+ {
+ case VAR_DECL:
+ if (!TREE_READONLY (decl)
+ || TREE_SIDE_EFFECTS (decl)
+ || !DECL_INITIAL (decl)
+ || (DECL_INITIAL (decl) != error_mark_node
+ && !TREE_CONSTANT (DECL_INITIAL (decl))))
+ readonly = 0;
+ break;
+ case CONSTRUCTOR:
+ if (! TREE_CONSTANT (decl))
+ readonly = 0;
+ break;
+
+ default:
+ break;
+ }
+
+ if (TREE_CODE (decl) == VAR_DECL)
+ {
+ const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
+
+ if (name[0] == '@' && name[2] == '.')
+ switch (name[1])
+ {
+ case 'b':
+ return based_section;
+
+ case 't':
+ if (readonly)
+ return srodata_section;
+ if (DECL_INITIAL (decl))
+ return sdata_section;
+ return tinybss_section;
+
+ case 'f':
+ if (readonly)
+ return frodata_section;
+ return far_section;
+
+ case 'i':
+ case 'I':
+ error ("%Hvariable %D of type %<io%> must be uninitialized",
+ &DECL_SOURCE_LOCATION (decl), decl);
+ return data_section;
+
+ case 'c':
+ error ("%Hvariable %D of type %<cb%> must be uninitialized",
+ &DECL_SOURCE_LOCATION (decl), decl);
+ return data_section;
+ }
+ }
+
+ if (readonly)
+ return readonly_data_section;
+
+ return data_section;
+}
+
+static void
+mep_unique_section (tree decl, int reloc)
+{
+ static const char *prefixes[][2] =
+ {
+ { ".text.", ".gnu.linkonce.t." },
+ { ".rodata.", ".gnu.linkonce.r." },
+ { ".data.", ".gnu.linkonce.d." },
+ { ".based.", ".gnu.linkonce.based." },
+ { ".sdata.", ".gnu.linkonce.s." },
+ { ".far.", ".gnu.linkonce.far." },
+ { ".ftext.", ".gnu.linkonce.ft." },
+ { ".frodata.", ".gnu.linkonce.frd." },
+ { ".srodata.", ".gnu.linkonce.srd." }
+ };
+ int sec = 2; /* .data */
+ int len;
+ const char *name, *prefix;
+ char *string;
+
+ name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
+ if (DECL_RTL (decl))
+ name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
+
+ if (TREE_CODE (decl) == FUNCTION_DECL)
+ sec = 0; /* .text */
+ else if (decl_readonly_section (decl, reloc))
+ sec = 1; /* .rodata */
+
+ if (name[0] == '@' && name[2] == '.')
+ {
+ switch (name[1])
+ {
+ case 'b':
+ sec = 3; /* .based */
+ break;
+ case 't':
+ if (sec == 1)
+ sec = 8; /* .srodata */
+ else
+ sec = 4; /* .sdata */
+ break;
+ case 'f':
+ if (sec == 0)
+ sec = 6; /* .ftext */
+ else if (sec == 1)
+ sec = 7; /* .frodata */
+ else
+ sec = 5; /* .far. */
+ break;
+ }
+ name += 3;
+ }
+
+ prefix = prefixes[sec][DECL_ONE_ONLY(decl)];
+ len = strlen (name) + strlen (prefix);
+ string = (char *) alloca (len + 1);
+
+ sprintf (string, "%s%s", prefix, name);
+
+ DECL_SECTION_NAME (decl) = build_string (len, string);
+}
+
+/* Given a decl, a section name, and whether the decl initializer
+ has relocs, choose attributes for the section. */
+
+#define SECTION_MEP_VLIW SECTION_MACH_DEP
+
+static unsigned int
+mep_section_type_flags (tree decl, const char *name, int reloc)
+{
+ unsigned int flags = default_section_type_flags (decl, name, reloc);
+
+ if (decl && TREE_CODE (decl) == FUNCTION_DECL
+ && lookup_attribute ("vliw", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
+ flags |= SECTION_MEP_VLIW;
+
+ return flags;
+}
+
+/* Switch to an arbitrary section NAME with attributes as specified
+ by FLAGS. ALIGN specifies any known alignment requirements for
+ the section; 0 if the default should be used.
+
+ Differs from the standard ELF version only in support of VLIW mode. */
+
+static void
+mep_asm_named_section (const char *name, unsigned int flags, tree decl ATTRIBUTE_UNUSED)
+{
+ char flagchars[8], *f = flagchars;
+ const char *type;
+
+ if (!(flags & SECTION_DEBUG))
+ *f++ = 'a';
+ if (flags & SECTION_WRITE)
+ *f++ = 'w';
+ if (flags & SECTION_CODE)
+ *f++ = 'x';
+ if (flags & SECTION_SMALL)
+ *f++ = 's';
+ if (flags & SECTION_MEP_VLIW)
+ *f++ = 'v';
+ *f = '\0';
+
+ if (flags & SECTION_BSS)
+ type = "nobits";
+ else
+ type = "progbits";
+
+ fprintf (asm_out_file, "\t.section\t%s,\"%s\",@%s\n",
+ name, flagchars, type);
+
+ if (flags & SECTION_CODE)
+ fputs ((flags & SECTION_MEP_VLIW ? "\t.vliw\n" : "\t.core\n"),
+ asm_out_file);
+}
+
+void
+mep_output_aligned_common (FILE *stream, tree decl, const char *name,
+ int size, int align, int global)
+{
+ /* We intentionally don't use mep_section_tag() here. */
+ if (name[0] == '@'
+ && (name[1] == 'i' || name[1] == 'I' || name[1] == 'c')
+ && name[2] == '.')
+ {
+ int location = -1;
+ tree attr = lookup_attribute ((name[1] == 'c' ? "cb" : "io"),
+ DECL_ATTRIBUTES (decl));
+ if (attr
+ && TREE_VALUE (attr)
+ && TREE_VALUE (TREE_VALUE(attr)))
+ location = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE(attr)));
+ if (location == -1)
+ return;
+ if (global)
+ {
+ fprintf (stream, "\t.globl\t");
+ assemble_name (stream, name);
+ fprintf (stream, "\n");
+ }
+ assemble_name (stream, name);
+ fprintf (stream, " = %d\n", location);
+ return;
+ }
+ if (name[0] == '@' && name[2] == '.')
+ {
+ const char *sec = 0;
+ switch (name[1])
+ {
+ case 'b':
+ switch_to_section (based_section);
+ sec = ".based";
+ break;
+ case 't':
+ switch_to_section (tinybss_section);
+ sec = ".sbss";
+ break;
+ case 'f':
+ switch_to_section (farbss_section);
+ sec = ".farbss";
+ break;
+ }
+ if (sec)
+ {
+ const char *name2;
+ int p2align = 0;
+
+ while (align > BITS_PER_UNIT)
+ {
+ align /= 2;
+ p2align ++;
+ }
+ name2 = TARGET_STRIP_NAME_ENCODING (name);
+ if (global)
+ fprintf (stream, "\t.globl\t%s\n", name2);
+ fprintf (stream, "\t.p2align %d\n", p2align);
+ fprintf (stream, "\t.type\t%s,@object\n", name2);
+ fprintf (stream, "\t.size\t%s,%d\n", name2, size);
+ fprintf (stream, "%s:\n\t.zero\t%d\n", name2, size);
+ return;
+ }
+ }
+
+ if (!global)
+ {
+ fprintf (stream, "\t.local\t");
+ assemble_name (stream, name);
+ fprintf (stream, "\n");
+ }
+ fprintf (stream, "\t.comm\t");
+ assemble_name (stream, name);
+ fprintf (stream, ",%u,%u\n", size, align / BITS_PER_UNIT);
+}
+
+/* Trampolines. */
+
+void
+mep_init_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
+{
+ emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__mep_trampoline_helper"),
+ LCT_NORMAL, VOIDmode, 3,
+ addr, Pmode,
+ fnaddr, Pmode,
+ static_chain, Pmode);
+}
+
+/* Experimental Reorg. */
+
+static bool
+mep_mentioned_p (rtx in,
+ rtx reg, /* NULL for mem */
+ int modes_too) /* if nonzero, modes must match also. */
+{
+ const char *fmt;
+ int i;
+ enum rtx_code code;
+
+ if (in == 0)
+ return false;
+ if (reg && GET_CODE (reg) != REG)
+ return false;
+
+ if (GET_CODE (in) == LABEL_REF)
+ return (reg == 0);
+
+ code = GET_CODE (in);
+
+ switch (code)
+ {
+ case MEM:
+ if (reg)
+ return mep_mentioned_p (XEXP (in, 0), reg, modes_too);
+ return true;
+
+ case REG:
+ if (!reg)
+ return false;
+ if (modes_too && (GET_MODE (in) != GET_MODE (reg)))
+ return false;
+ return (REGNO (in) == REGNO (reg));
+
+ case SCRATCH:
+ case CC0:
+ case PC:
+ case CONST_INT:
+ case CONST_DOUBLE:
+ return false;
+
+ default:
+ break;
+ }
+
+ /* Set's source should be read-only. */
+ if (code == SET && !reg)
+ return mep_mentioned_p (SET_DEST (in), reg, modes_too);
+
+ fmt = GET_RTX_FORMAT (code);
+
+ for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+ {
+ if (fmt[i] == 'E')
+ {
+ register int j;
+ for (j = XVECLEN (in, i) - 1; j >= 0; j--)
+ if (mep_mentioned_p (XVECEXP (in, i, j), reg, modes_too))
+ return true;
+ }
+ else if (fmt[i] == 'e'
+ && mep_mentioned_p (XEXP (in, i), reg, modes_too))
+ return true;
+ }
+ return false;
+}
+
+#define EXPERIMENTAL_REGMOVE_REORG 1
+
+#if EXPERIMENTAL_REGMOVE_REORG
+
+static int
+mep_compatible_reg_class (int r1, int r2)
+{
+ if (GR_REGNO_P (r1) && GR_REGNO_P (r2))
+ return 1;
+ if (CR_REGNO_P (r1) && CR_REGNO_P (r2))
+ return 1;
+ return 0;
+}
+
+static void
+mep_reorg_regmove (rtx insns)
+{
+ rtx insn, next, pat, follow, *where;
+ int count = 0, done = 0, replace, before = 0;
+
+ if (dump_file)
+ for (insn = insns; insn; insn = NEXT_INSN (insn))
+ if (GET_CODE (insn) == INSN)
+ before++;
+
+ /* We're looking for (set r2 r1) moves where r1 dies, followed by a
+ set that uses the r2 and r2 dies there. We replace r2 with r1
+ and see if it's still a valid insn. If so, delete the first set.
+ Copied from reorg.c. */
+
+ while (!done)
+ {
+ done = 1;
+ for (insn = insns; insn; insn = next)
+ {
+ next = NEXT_INSN (insn);
+ if (GET_CODE (insn) != INSN)
+ continue;
+ pat = PATTERN (insn);
+
+ replace = 0;
+
+ if (GET_CODE (pat) == SET
+ && GET_CODE (SET_SRC (pat)) == REG
+ && GET_CODE (SET_DEST (pat)) == REG
+ && find_regno_note (insn, REG_DEAD, REGNO (SET_SRC (pat)))
+ && mep_compatible_reg_class (REGNO (SET_SRC (pat)), REGNO (SET_DEST (pat))))
+ {
+ follow = next_nonnote_insn (insn);
+ if (dump_file)
+ fprintf (dump_file, "superfluous moves: considering %d\n", INSN_UID (insn));
+
+ while (follow && GET_CODE (follow) == INSN
+ && GET_CODE (PATTERN (follow)) == SET
+ && !dead_or_set_p (follow, SET_SRC (pat))
+ && !mep_mentioned_p (PATTERN (follow), SET_SRC (pat), 0)
+ && !mep_mentioned_p (PATTERN (follow), SET_DEST (pat), 0))
+ {
+ if (dump_file)
+ fprintf (dump_file, "\tskipping %d\n", INSN_UID (follow));
+ follow = next_nonnote_insn (follow);
+ }
+
+ if (dump_file)
+ fprintf (dump_file, "\tfollow is %d\n", INSN_UID (follow));
+ if (follow && GET_CODE (follow) == INSN
+ && GET_CODE (PATTERN (follow)) == SET
+ && find_regno_note (follow, REG_DEAD, REGNO (SET_DEST (pat))))
+ {
+ if (GET_CODE (SET_DEST (PATTERN (follow))) == REG)
+ {
+ if (mep_mentioned_p (SET_SRC (PATTERN (follow)), SET_DEST (pat), 1))
+ {
+ replace = 1;
+ where = & SET_SRC (PATTERN (follow));
+ }
+ }
+ else if (GET_CODE (SET_DEST (PATTERN (follow))) == MEM)
+ {
+ if (mep_mentioned_p (PATTERN (follow), SET_DEST (pat), 1))
+ {
+ replace = 1;
+ where = & PATTERN (follow);
+ }
+ }
+ }
+ }
+
+ /* If so, follow is the corresponding insn */
+ if (replace)
+ {
+ if (dump_file)
+ {
+ rtx x;
+
+ fprintf (dump_file, "----- Candidate for superfluous move deletion:\n\n");
+ for (x = insn; x ;x = NEXT_INSN (x))
+ {
+ print_rtl_single (dump_file, x);
+ if (x == follow)
+ break;
+ fprintf (dump_file, "\n");
+ }
+ }
+
+ if (validate_replace_rtx_subexp (SET_DEST (pat), SET_SRC (pat),
+ follow, where))
+ {
+ count ++;
+ next = delete_insn (insn);
+ if (dump_file)
+ {
+ fprintf (dump_file, "\n----- Success! new insn:\n\n");
+ print_rtl_single (dump_file, follow);
+ }
+ done = 0;
+ }
+ }
+ }
+ }
+
+ if (dump_file)
+ {
+ fprintf (dump_file, "\n%d insn%s deleted out of %d.\n\n", count, count == 1 ? "" : "s", before);
+ fprintf (dump_file, "=====\n");
+ }
+}
+#endif
+
+
+/* Figure out where to put LABEL, which is the label for a repeat loop.
+ If INCLUDING, LAST_INSN is the last instruction in the loop, otherwise
+ the loop ends just before LAST_INSN. If SHARED, insns other than the
+ "repeat" might use LABEL to jump to the loop's continuation point.
+
+ Return the last instruction in the adjusted loop. */
+
+static rtx
+mep_insert_repeat_label_last (rtx last_insn, rtx label, bool including,
+ bool shared)
+{
+ rtx next, prev;
+ int count = 0, code, icode;
+
+ if (dump_file)
+ fprintf (dump_file, "considering end of repeat loop at insn %d\n",
+ INSN_UID (last_insn));
+
+ /* Set PREV to the last insn in the loop. */
+ prev = last_insn;
+ if (!including)
+ prev = PREV_INSN (prev);
+
+ /* Set NEXT to the next insn after the repeat label. */
+ next = last_insn;
+ if (!shared)
+ while (prev != 0)
+ {
+ code = GET_CODE (prev);
+ if (code == CALL_INSN || code == CODE_LABEL || code == BARRIER)
+ break;
+
+ if (INSN_P (prev))
+ {
+ if (GET_CODE (PATTERN (prev)) == SEQUENCE)
+ prev = XVECEXP (PATTERN (prev), 0, 1);
+
+ /* Other insns that should not be in the last two opcodes. */
+ icode = recog_memoized (prev);
+ if (icode < 0
+ || icode == CODE_FOR_repeat
+ || icode == CODE_FOR_erepeat
+ || get_attr_may_trap (prev) == MAY_TRAP_YES)
+ break;
+
+ /* That leaves JUMP_INSN and INSN. It will have BImode if it
+ is the second instruction in a VLIW bundle. In that case,
+ loop again: if the first instruction also satisfies the
+ conditions above then we will reach here again and put
+ both of them into the repeat epilogue. Otherwise both
+ should remain outside. */
+ if (GET_MODE (prev) != BImode)
+ {
+ count++;
+ next = prev;
+ if (dump_file)
+ print_rtl_single (dump_file, next);
+ if (count == 2)
+ break;
+ }
+ }
+ prev = PREV_INSN (prev);
+ }
+
+ /* See if we're adding the label immediately after the repeat insn.
+ If so, we need to separate them with a nop. */
+ prev = prev_real_insn (next);
+ if (prev)
+ switch (recog_memoized (prev))
+ {
+ case CODE_FOR_repeat:
+ case CODE_FOR_erepeat:
+ if (dump_file)
+ fprintf (dump_file, "Adding nop inside loop\n");
+ emit_insn_before (gen_nop (), next);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Insert the label. */
+ emit_label_before (label, next);
+
+ /* Insert the nops. */
+ if (dump_file && count < 2)
+ fprintf (dump_file, "Adding %d nop%s\n\n",
+ 2 - count, count == 1 ? "" : "s");
+
+ for (; count < 2; count++)
+ if (including)
+ last_insn = emit_insn_after (gen_nop (), last_insn);
+ else
+ emit_insn_before (gen_nop (), last_insn);
+
+ return last_insn;
+}
+
+
+void
+mep_emit_doloop (rtx *operands, int is_end)
+{
+ rtx tag;
+
+ if (cfun->machine->doloop_tags == 0
+ || cfun->machine->doloop_tag_from_end == is_end)
+ {
+ cfun->machine->doloop_tags++;
+ cfun->machine->doloop_tag_from_end = is_end;
+ }
+
+ tag = GEN_INT (cfun->machine->doloop_tags - 1);
+ if (is_end)
+ emit_jump_insn (gen_doloop_end_internal (operands[0], operands[4], tag));
+ else
+ emit_insn (gen_doloop_begin_internal (operands[0], operands[0], tag));
+}
+
+
+/* Code for converting doloop_begins and doloop_ends into valid
+ MeP instructions. A doloop_begin is just a placeholder:
+
+ $count = unspec ($count)
+
+ where $count is initially the number of iterations - 1.
+ doloop_end has the form:
+
+ if ($count-- == 0) goto label
+
+ The counter variable is private to the doloop insns, nothing else
+ relies on its value.
+
+ There are three cases, in decreasing order of preference:
+
+ 1. A loop has exactly one doloop_begin and one doloop_end.
+ The doloop_end branches to the first instruction after
+ the doloop_begin.
+
+ In this case we can replace the doloop_begin with a repeat
+ instruction and remove the doloop_end. I.e.:
+
+ $count1 = unspec ($count1)
+ label:
+ ...
+ insn1
+ insn2
+ if ($count2-- == 0) goto label
+
+ becomes:
+
+ repeat $count1,repeat_label
+ label:
+ ...
+ repeat_label:
+ insn1
+ insn2
+ # end repeat
+
+ 2. As for (1), except there are several doloop_ends. One of them
+ (call it X) falls through to a label L. All the others fall
+ through to branches to L.
+
+ In this case, we remove X and replace the other doloop_ends
+ with branches to the repeat label. For example:
+
+ $count1 = unspec ($count1)
+ start:
+ ...
+ if ($count2-- == 0) goto label
+ end:
+ ...
+ if ($count3-- == 0) goto label
+ goto end
+
+ becomes:
+
+ repeat $count1,repeat_label
+ start:
+ ...
+ repeat_label:
+ nop
+ nop
+ # end repeat
+ end:
+ ...
+ goto repeat_label
+
+ 3. The fallback case. Replace doloop_begins with:
+
+ $count = $count + 1
+
+ Replace doloop_ends with the equivalent of:
+
+ $count = $count - 1
+ if ($count == 0) goto label
+
+ Note that this might need a scratch register if $count
+ is stored in memory. */
+
+/* A structure describing one doloop_begin. */
+struct mep_doloop_begin {
+ /* The next doloop_begin with the same tag. */
+ struct mep_doloop_begin *next;
+
+ /* The instruction itself. */
+ rtx insn;
+
+ /* The initial counter value. This is known to be a general register. */
+ rtx counter;
+};
+
+/* A structure describing a doloop_end. */
+struct mep_doloop_end {
+ /* The next doloop_end with the same loop tag. */
+ struct mep_doloop_end *next;
+
+ /* The instruction itself. */
+ rtx insn;
+
+ /* The first instruction after INSN when the branch isn't taken. */
+ rtx fallthrough;
+
+ /* The location of the counter value. Since doloop_end_internal is a
+ jump instruction, it has to allow the counter to be stored anywhere
+ (any non-fixed register or memory location). */
+ rtx counter;
+
+ /* The target label (the place where the insn branches when the counter
+ isn't zero). */
+ rtx label;
+
+ /* A scratch register. Only available when COUNTER isn't stored
+ in a general register. */
+ rtx scratch;
+};
+
+
+/* One do-while loop. */
+struct mep_doloop {
+ /* All the doloop_begins for this loop (in no particular order). */
+ struct mep_doloop_begin *begin;
+
+ /* All the doloop_ends. When there is more than one, arrange things
+ so that the first one is the most likely to be X in case (2) above. */
+ struct mep_doloop_end *end;
+};
+
+
+/* Return true if LOOP can be converted into repeat/repeat_end form
+ (that is, if it matches cases (1) or (2) above). */
+
+static bool
+mep_repeat_loop_p (struct mep_doloop *loop)
+{
+ struct mep_doloop_end *end;
+ rtx fallthrough;
+
+ /* There must be exactly one doloop_begin and at least one doloop_end. */
+ if (loop->begin == 0 || loop->end == 0 || loop->begin->next != 0)
+ return false;
+
+ /* The first doloop_end (X) must branch back to the insn after
+ the doloop_begin. */
+ if (prev_real_insn (loop->end->label) != loop->begin->insn)
+ return false;
+
+ /* All the other doloop_ends must branch to the same place as X.
+ When the branch isn't taken, they must jump to the instruction
+ after X. */
+ fallthrough = loop->end->fallthrough;
+ for (end = loop->end->next; end != 0; end = end->next)
+ if (end->label != loop->end->label
+ || !simplejump_p (end->fallthrough)
+ || next_real_insn (JUMP_LABEL (end->fallthrough)) != fallthrough)
+ return false;
+
+ return true;
+}
+
+
+/* The main repeat reorg function. See comment above for details. */
+
+static void
+mep_reorg_repeat (rtx insns)
+{
+ rtx insn;
+ struct mep_doloop *loops, *loop;
+ struct mep_doloop_begin *begin;
+ struct mep_doloop_end *end;
+
+ /* Quick exit if we haven't created any loops. */
+ if (cfun->machine->doloop_tags == 0)
+ return;
+
+ /* Create an array of mep_doloop structures. */
+ loops = (struct mep_doloop *) alloca (sizeof (loops[0]) * cfun->machine->doloop_tags);
+ memset (loops, 0, sizeof (loops[0]) * cfun->machine->doloop_tags);
+
+ /* Search the function for do-while insns and group them by loop tag. */
+ for (insn = insns; insn; insn = NEXT_INSN (insn))
+ if (INSN_P (insn))
+ switch (recog_memoized (insn))
+ {
+ case CODE_FOR_doloop_begin_internal:
+ insn_extract (insn);
+ loop = &loops[INTVAL (recog_data.operand[2])];
+
+ begin = (struct mep_doloop_begin *) alloca (sizeof (struct mep_doloop_begin));
+ begin->next = loop->begin;
+ begin->insn = insn;
+ begin->counter = recog_data.operand[0];
+
+ loop->begin = begin;
+ break;
+
+ case CODE_FOR_doloop_end_internal:
+ insn_extract (insn);
+ loop = &loops[INTVAL (recog_data.operand[2])];
+
+ end = (struct mep_doloop_end *) alloca (sizeof (struct mep_doloop_end));
+ end->insn = insn;
+ end->fallthrough = next_real_insn (insn);
+ end->counter = recog_data.operand[0];
+ end->label = recog_data.operand[1];
+ end->scratch = recog_data.operand[3];
+
+ /* If this insn falls through to an unconditional jump,
+ give it a lower priority than the others. */
+ if (loop->end != 0 && simplejump_p (end->fallthrough))
+ {
+ end->next = loop->end->next;
+ loop->end->next = end;
+ }
+ else
+ {
+ end->next = loop->end;
+ loop->end = end;
+ }
+ break;
+ }
+
+ /* Convert the insns for each loop in turn. */
+ for (loop = loops; loop < loops + cfun->machine->doloop_tags; loop++)
+ if (mep_repeat_loop_p (loop))
+ {
+ /* Case (1) or (2). */
+ rtx repeat_label, label_ref;
+
+ /* Create a new label for the repeat insn. */
+ repeat_label = gen_label_rtx ();
+
+ /* Replace the doloop_begin with a repeat. */
+ label_ref = gen_rtx_LABEL_REF (VOIDmode, repeat_label);
+ emit_insn_before (gen_repeat (loop->begin->counter, label_ref),
+ loop->begin->insn);
+ delete_insn (loop->begin->insn);
+
+ /* Insert the repeat label before the first doloop_end.
+ Fill the gap with nops if there are other doloop_ends. */
+ mep_insert_repeat_label_last (loop->end->insn, repeat_label,
+ false, loop->end->next != 0);
+
+ /* Emit a repeat_end (to improve the readability of the output). */
+ emit_insn_before (gen_repeat_end (), loop->end->insn);
+
+ /* Delete the first doloop_end. */
+ delete_insn (loop->end->insn);
+
+ /* Replace the others with branches to REPEAT_LABEL. */
+ for (end = loop->end->next; end != 0; end = end->next)
+ {
+ emit_jump_insn_before (gen_jump (repeat_label), end->insn);
+ delete_insn (end->insn);
+ delete_insn (end->fallthrough);
+ }
+ }
+ else
+ {
+ /* Case (3). First replace all the doloop_begins with increment
+ instructions. */
+ for (begin = loop->begin; begin != 0; begin = begin->next)
+ {
+ emit_insn_before (gen_add3_insn (copy_rtx (begin->counter),
+ begin->counter, const1_rtx),
+ begin->insn);
+ delete_insn (begin->insn);
+ }
+
+ /* Replace all the doloop_ends with decrement-and-branch sequences. */
+ for (end = loop->end; end != 0; end = end->next)
+ {
+ rtx reg;
+
+ start_sequence ();
+
+ /* Load the counter value into a general register. */
+ reg = end->counter;
+ if (!REG_P (reg) || REGNO (reg) > 15)
+ {
+ reg = end->scratch;
+ emit_move_insn (copy_rtx (reg), copy_rtx (end->counter));
+ }
+
+ /* Decrement the counter. */
+ emit_insn (gen_add3_insn (copy_rtx (reg), copy_rtx (reg),
+ constm1_rtx));
+
+ /* Copy it back to its original location. */
+ if (reg != end->counter)
+ emit_move_insn (copy_rtx (end->counter), copy_rtx (reg));
+
+ /* Jump back to the start label. */
+ insn = emit_jump_insn (gen_mep_bne_true (reg, const0_rtx,
+ end->label));
+ JUMP_LABEL (insn) = end->label;
+ LABEL_NUSES (end->label)++;
+
+ /* Emit the whole sequence before the doloop_end. */
+ insn = get_insns ();
+ end_sequence ();
+ emit_insn_before (insn, end->insn);
+
+ /* Delete the doloop_end. */
+ delete_insn (end->insn);
+ }
+ }
+}
+
+
+static bool
+mep_invertable_branch_p (rtx insn)
+{
+ rtx cond, set;
+ enum rtx_code old_code;
+ int i;
+
+ set = PATTERN (insn);
+ if (GET_CODE (set) != SET)
+ return false;
+ if (GET_CODE (XEXP (set, 1)) != IF_THEN_ELSE)
+ return false;
+ cond = XEXP (XEXP (set, 1), 0);
+ old_code = GET_CODE (cond);
+ switch (old_code)
+ {
+ case EQ:
+ PUT_CODE (cond, NE);
+ break;
+ case NE:
+ PUT_CODE (cond, EQ);
+ break;
+ case LT:
+ PUT_CODE (cond, GE);
+ break;
+ case GE:
+ PUT_CODE (cond, LT);
+ break;
+ default:
+ return false;
+ }
+ INSN_CODE (insn) = -1;
+ i = recog_memoized (insn);
+ PUT_CODE (cond, old_code);
+ INSN_CODE (insn) = -1;
+ return i >= 0;
+}
+
+static void
+mep_invert_branch (rtx insn, rtx after)
+{
+ rtx cond, set, label;
+ int i;
+
+ set = PATTERN (insn);
+
+ gcc_assert (GET_CODE (set) == SET);
+ gcc_assert (GET_CODE (XEXP (set, 1)) == IF_THEN_ELSE);
+
+ cond = XEXP (XEXP (set, 1), 0);
+ switch (GET_CODE (cond))
+ {
+ case EQ:
+ PUT_CODE (cond, NE);
+ break;
+ case NE:
+ PUT_CODE (cond, EQ);
+ break;
+ case LT:
+ PUT_CODE (cond, GE);
+ break;
+ case GE:
+ PUT_CODE (cond, LT);
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ label = gen_label_rtx ();
+ emit_label_after (label, after);
+ for (i=1; i<=2; i++)
+ if (GET_CODE (XEXP (XEXP (set, 1), i)) == LABEL_REF)
+ {
+ rtx ref = XEXP (XEXP (set, 1), i);
+ if (LABEL_NUSES (XEXP (ref, 0)) == 1)
+ delete_insn (XEXP (ref, 0));
+ XEXP (ref, 0) = label;
+ LABEL_NUSES (label) ++;
+ JUMP_LABEL (insn) = label;
+ }
+ INSN_CODE (insn) = -1;
+ i = recog_memoized (insn);
+ gcc_assert (i >= 0);
+}
+
+static void
+mep_reorg_erepeat (rtx insns)
+{
+ rtx insn, prev, label_before, l, x;
+ int count;
+
+ for (insn = insns; insn; insn = NEXT_INSN (insn))
+ if (JUMP_P (insn)
+ && ! JUMP_TABLE_DATA_P (insn)
+ && mep_invertable_branch_p (insn))
+ {
+ if (dump_file)
+ {
+ fprintf (dump_file, "\n------------------------------\n");
+ fprintf (dump_file, "erepeat: considering this jump:\n");
+ print_rtl_single (dump_file, insn);
+ }
+ count = simplejump_p (insn) ? 0 : 1;
+ label_before = 0;
+ for (prev = PREV_INSN (insn); prev; prev = PREV_INSN (prev))
+ {
+ if (GET_CODE (prev) == CALL_INSN
+ || BARRIER_P (prev))
+ break;
+
+ if (prev == JUMP_LABEL (insn))
+ {
+ rtx newlast;
+ if (dump_file)
+ fprintf (dump_file, "found loop top, %d insns\n", count);
+
+ if (LABEL_NUSES (prev) == 1)
+ /* We're the only user, always safe */ ;
+ else if (LABEL_NUSES (prev) == 2)
+ {
+ /* See if there's a barrier before this label. If
+ so, we know nobody inside the loop uses it.
+ But we must be careful to put the erepeat
+ *after* the label. */
+ rtx barrier;
+ for (barrier = PREV_INSN (prev);
+ barrier && GET_CODE (barrier) == NOTE;
+ barrier = PREV_INSN (barrier))
+ ;
+ if (barrier && GET_CODE (barrier) != BARRIER)
+ break;
+ }
+ else
+ {
+ /* We don't know who else, within or without our loop, uses this */
+ if (dump_file)
+ fprintf (dump_file, "... but there are multiple users, too risky.\n");
+ break;
+ }
+
+ /* Generate a label to be used by the erepat insn. */
+ l = gen_label_rtx ();
+
+ /* Insert the erepeat after INSN's target label. */
+ x = gen_erepeat (gen_rtx_LABEL_REF (VOIDmode, l));
+ LABEL_NUSES (l)++;
+ emit_insn_after (x, prev);
+
+ /* Insert the erepeat label. */
+ newlast = (mep_insert_repeat_label_last
+ (insn, l, !simplejump_p (insn), false));
+ if (simplejump_p (insn))
+ {
+ emit_insn_before (gen_erepeat_end (), insn);
+ delete_insn (insn);
+ }
+ else
+ {
+ mep_invert_branch (insn, newlast);
+ emit_insn_after (gen_erepeat_end (), newlast);
+ }
+ break;
+ }
+
+ if (LABEL_P (prev))
+ {
+ /* A label is OK if there is exactly one user, and we
+ can find that user before the next label. */
+ rtx user = 0;
+ int safe = 0;
+ if (LABEL_NUSES (prev) == 1)
+ {
+ for (user = PREV_INSN (prev);
+ user && (INSN_P (user) || GET_CODE (user) == NOTE);
+ user = PREV_INSN (user))
+ if (GET_CODE (user) == JUMP_INSN
+ && JUMP_LABEL (user) == prev)
+ {
+ safe = INSN_UID (user);
+ break;
+ }
+ }
+ if (!safe)
+ break;
+ if (dump_file)
+ fprintf (dump_file, "... ignoring jump from insn %d to %d\n",
+ safe, INSN_UID (prev));
+ }
+
+ if (INSN_P (prev))
+ {
+ count ++;
+ if (count == 2)
+ label_before = prev;
+ }
+ }
+ }
+ if (dump_file)
+ fprintf (dump_file, "\n==============================\n");
+}
+
+/* Replace a jump to a return, with a copy of the return. GCC doesn't
+ always do this on its own. */
+
+static void
+mep_jmp_return_reorg (rtx insns)
+{
+ rtx insn, label, ret;
+ int ret_code;
+
+ for (insn = insns; insn; insn = NEXT_INSN (insn))
+ if (simplejump_p (insn))
+ {
+ /* Find the fist real insn the jump jumps to. */
+ label = ret = JUMP_LABEL (insn);
+ while (ret
+ && (GET_CODE (ret) == NOTE
+ || GET_CODE (ret) == CODE_LABEL
+ || GET_CODE (PATTERN (ret)) == USE))
+ ret = NEXT_INSN (ret);
+
+ if (ret)
+ {
+ /* Is it a return? */
+ ret_code = recog_memoized (ret);
+ if (ret_code == CODE_FOR_return_internal
+ || ret_code == CODE_FOR_eh_return_internal)
+ {
+ /* It is. Replace the jump with a return. */
+ LABEL_NUSES (label) --;
+ if (LABEL_NUSES (label) == 0)
+ delete_insn (label);
+ PATTERN (insn) = copy_rtx (PATTERN (ret));
+ INSN_CODE (insn) = -1;
+ }
+ }
+ }
+}
+
+
+static void
+mep_reorg_addcombine (rtx insns)
+{
+ rtx i, n;
+
+ for (i = insns; i; i = NEXT_INSN (i))
+ if (INSN_P (i)
+ && INSN_CODE (i) == CODE_FOR_addsi3
+ && GET_CODE (SET_DEST (PATTERN (i))) == REG
+ && GET_CODE (XEXP (SET_SRC (PATTERN (i)), 0)) == REG
+ && REGNO (SET_DEST (PATTERN (i))) == REGNO (XEXP (SET_SRC (PATTERN (i)), 0))
+ && GET_CODE (XEXP (SET_SRC (PATTERN (i)), 1)) == CONST_INT)
+ {
+ n = NEXT_INSN (i);
+ if (INSN_P (n)
+ && INSN_CODE (n) == CODE_FOR_addsi3
+ && GET_CODE (SET_DEST (PATTERN (n))) == REG
+ && GET_CODE (XEXP (SET_SRC (PATTERN (n)), 0)) == REG
+ && REGNO (SET_DEST (PATTERN (n))) == REGNO (XEXP (SET_SRC (PATTERN (n)), 0))
+ && GET_CODE (XEXP (SET_SRC (PATTERN (n)), 1)) == CONST_INT)
+ {
+ int ic = INTVAL (XEXP (SET_SRC (PATTERN (i)), 1));
+ int nc = INTVAL (XEXP (SET_SRC (PATTERN (n)), 1));
+ if (REGNO (SET_DEST (PATTERN (i))) == REGNO (SET_DEST (PATTERN (n)))
+ && ic + nc < 32767
+ && ic + nc > -32768)
+ {
+ XEXP (SET_SRC (PATTERN (i)), 1) = GEN_INT (ic + nc);
+ NEXT_INSN (i) = NEXT_INSN (n);
+ if (NEXT_INSN (i))
+ PREV_INSN (NEXT_INSN (i)) = i;
+ }
+ }
+ }
+}
+
+/* If this insn adjusts the stack, return the adjustment, else return
+ zero. */
+static int
+add_sp_insn_p (rtx insn)
+{
+ rtx pat;
+
+ if (! single_set (insn))
+ return 0;
+ pat = PATTERN (insn);
+ if (GET_CODE (SET_DEST (pat)) != REG)
+ return 0;
+ if (REGNO (SET_DEST (pat)) != SP_REGNO)
+ return 0;
+ if (GET_CODE (SET_SRC (pat)) != PLUS)
+ return 0;
+ if (GET_CODE (XEXP (SET_SRC (pat), 0)) != REG)
+ return 0;
+ if (REGNO (XEXP (SET_SRC (pat), 0)) != SP_REGNO)
+ return 0;
+ if (GET_CODE (XEXP (SET_SRC (pat), 1)) != CONST_INT)
+ return 0;
+ return INTVAL (XEXP (SET_SRC (pat), 1));
+}
+
+/* Check for trivial functions that set up an unneeded stack
+ frame. */
+static void
+mep_reorg_noframe (rtx insns)
+{
+ rtx start_frame_insn;
+ rtx end_frame_insn = 0;
+ int sp_adjust, sp2;
+ rtx sp;
+
+ /* The first insn should be $sp = $sp + N */
+ while (insns && ! INSN_P (insns))
+ insns = NEXT_INSN (insns);
+ if (!insns)
+ return;
+
+ sp_adjust = add_sp_insn_p (insns);
+ if (sp_adjust == 0)
+ return;
+
+ start_frame_insn = insns;
+ sp = SET_DEST (PATTERN (start_frame_insn));
+
+ insns = next_real_insn (insns);
+
+ while (insns)
+ {
+ rtx next = next_real_insn (insns);
+ if (!next)
+ break;
+
+ sp2 = add_sp_insn_p (insns);
+ if (sp2)
+ {
+ if (end_frame_insn)
+ return;
+ end_frame_insn = insns;
+ if (sp2 != -sp_adjust)
+ return;
+ }
+ else if (mep_mentioned_p (insns, sp, 0))
+ return;
+ else if (CALL_P (insns))
+ return;
+
+ insns = next;
+ }
+
+ if (end_frame_insn)
+ {
+ delete_insn (start_frame_insn);
+ delete_insn (end_frame_insn);
+ }
+}
+
+static void
+mep_reorg (void)
+{
+ rtx insns = get_insns ();
+ mep_reorg_addcombine (insns);
+#if EXPERIMENTAL_REGMOVE_REORG
+ /* VLIW packing has been done already, so we can't just delete things. */
+ if (!mep_vliw_function_p (cfun->decl))
+ mep_reorg_regmove (insns);
+#endif
+ mep_jmp_return_reorg (insns);
+ mep_bundle_insns (insns);
+ mep_reorg_repeat (insns);
+ if (optimize
+ && !profile_flag
+ && !profile_arc_flag
+ && TARGET_OPT_REPEAT
+ && (!mep_interrupt_p () || mep_interrupt_saved_reg (RPB_REGNO)))
+ mep_reorg_erepeat (insns);
+
+ /* This may delete *insns so make sure it's last. */
+ mep_reorg_noframe (insns);
+}
+
+\f
+
+/*----------------------------------------------------------------------*/
+/* Builtins */
+/*----------------------------------------------------------------------*/
+
+/* Element X gives the index into cgen_insns[] of the most general
+ implementation of intrinsic X. Unimplemented intrinsics are
+ mapped to -1. */
+int mep_intrinsic_insn[ARRAY_SIZE (cgen_intrinsics)];
+
+/* Element X gives the index of another instruction that is mapped to
+ the same intrinsic as cgen_insns[X]. It is -1 when there is no other
+ instruction.
+
+ Things are set up so that mep_intrinsic_chain[X] < X. */
+static int mep_intrinsic_chain[ARRAY_SIZE (cgen_insns)];
+
+/* The bitmask for the current ISA. The ISA masks are declared
+ in mep-intrin.h. */
+unsigned int mep_selected_isa;
+
+struct mep_config {
+ const char *config_name;
+ unsigned int isa;
+};
+
+static struct mep_config mep_configs[] = {
+#ifdef COPROC_SELECTION_TABLE
+ COPROC_SELECTION_TABLE,
+#endif
+ { 0, 0 }
+};
+
+/* Initialize the global intrinsics variables above. */
+
+static void
+mep_init_intrinsics (void)
+{
+ size_t i;
+
+ /* Set MEP_SELECTED_ISA to the ISA flag for this configuration. */
+ mep_selected_isa = mep_configs[0].isa;
+ if (mep_config_string != 0)
+ for (i = 0; mep_configs[i].config_name; i++)
+ if (strcmp (mep_config_string, mep_configs[i].config_name) == 0)
+ {
+ mep_selected_isa = mep_configs[i].isa;
+ break;
+ }
+
+ /* Assume all intrinsics are unavailable. */
+ for (i = 0; i < ARRAY_SIZE (mep_intrinsic_insn); i++)
+ mep_intrinsic_insn[i] = -1;
+
+ /* Build up the global intrinsic tables. */
+ for (i = 0; i < ARRAY_SIZE (cgen_insns); i++)
+ if ((cgen_insns[i].isas & mep_selected_isa) != 0)
+ {
+ mep_intrinsic_chain[i] = mep_intrinsic_insn[cgen_insns[i].intrinsic];
+ mep_intrinsic_insn[cgen_insns[i].intrinsic] = i;
+ }
+ /* See whether we can directly move values between one coprocessor
+ register and another. */
+ for (i = 0; i < ARRAY_SIZE (mep_cmov_insns); i++)
+ if (MEP_INTRINSIC_AVAILABLE_P (mep_cmov_insns[i]))
+ mep_have_copro_copro_moves_p = true;
+
+ /* See whether we can directly move values between core and
+ coprocessor registers. */
+ mep_have_core_copro_moves_p = (MEP_INTRINSIC_AVAILABLE_P (mep_cmov1)
+ && MEP_INTRINSIC_AVAILABLE_P (mep_cmov2));
+
+ mep_have_core_copro_moves_p = 1;
+}
+
+/* Declare all available intrinsic functions. Called once only. */
+
+static tree cp_data_bus_int_type_node;
+static tree opaque_vector_type_node;
+static tree v8qi_type_node;
+static tree v4hi_type_node;
+static tree v2si_type_node;
+static tree v8uqi_type_node;
+static tree v4uhi_type_node;
+static tree v2usi_type_node;
+
+static tree
+mep_cgen_regnum_to_type (enum cgen_regnum_operand_type cr)
+{
+ switch (cr)
+ {
+ case cgen_regnum_operand_type_POINTER: return ptr_type_node;
+ case cgen_regnum_operand_type_LONG: return long_integer_type_node;
+ case cgen_regnum_operand_type_ULONG: return long_unsigned_type_node;
+ case cgen_regnum_operand_type_SHORT: return short_integer_type_node;
+ case cgen_regnum_operand_type_USHORT: return short_unsigned_type_node;
+ case cgen_regnum_operand_type_CHAR: return char_type_node;
+ case cgen_regnum_operand_type_UCHAR: return unsigned_char_type_node;
+ case cgen_regnum_operand_type_SI: return intSI_type_node;
+ case cgen_regnum_operand_type_DI: return intDI_type_node;
+ case cgen_regnum_operand_type_VECTOR: return opaque_vector_type_node;
+ case cgen_regnum_operand_type_V8QI: return v8qi_type_node;
+ case cgen_regnum_operand_type_V4HI: return v4hi_type_node;
+ case cgen_regnum_operand_type_V2SI: return v2si_type_node;
+ case cgen_regnum_operand_type_V8UQI: return v8uqi_type_node;
+ case cgen_regnum_operand_type_V4UHI: return v4uhi_type_node;
+ case cgen_regnum_operand_type_V2USI: return v2usi_type_node;
+ case cgen_regnum_operand_type_CP_DATA_BUS_INT: return cp_data_bus_int_type_node;
+ default:
+ return void_type_node;
+ }
+}
+
+static void
+mep_init_builtins (void)
+{
+ size_t i;
+
+ if (TARGET_64BIT_CR_REGS)
+ cp_data_bus_int_type_node = long_long_integer_type_node;
+ else
+ cp_data_bus_int_type_node = long_integer_type_node;
+
+ opaque_vector_type_node = build_opaque_vector_type (intQI_type_node, 8);
+ v8qi_type_node = build_vector_type (intQI_type_node, 8);
+ v4hi_type_node = build_vector_type (intHI_type_node, 4);
+ v2si_type_node = build_vector_type (intSI_type_node, 2);
+ v8uqi_type_node = build_vector_type (unsigned_intQI_type_node, 8);
+ v4uhi_type_node = build_vector_type (unsigned_intHI_type_node, 4);
+ v2usi_type_node = build_vector_type (unsigned_intSI_type_node, 2);
+
+ (*lang_hooks.decls.pushdecl)
+ (build_decl (BUILTINS_LOCATION, TYPE_DECL, get_identifier ("cp_data_bus_int"),
+ cp_data_bus_int_type_node));
+
+ (*lang_hooks.decls.pushdecl)
+ (build_decl (BUILTINS_LOCATION, TYPE_DECL, get_identifier ("cp_vector"),
+ opaque_vector_type_node));
+
+ (*lang_hooks.decls.pushdecl)
+ (build_decl (BUILTINS_LOCATION, TYPE_DECL, get_identifier ("cp_v8qi"),
+ v8qi_type_node));
+ (*lang_hooks.decls.pushdecl)
+ (build_decl (BUILTINS_LOCATION, TYPE_DECL, get_identifier ("cp_v4hi"),
+ v4hi_type_node));
+ (*lang_hooks.decls.pushdecl)
+ (build_decl (BUILTINS_LOCATION, TYPE_DECL, get_identifier ("cp_v2si"),
+ v2si_type_node));
+
+ (*lang_hooks.decls.pushdecl)
+ (build_decl (BUILTINS_LOCATION, TYPE_DECL, get_identifier ("cp_v8uqi"),
+ v8uqi_type_node));
+ (*lang_hooks.decls.pushdecl)
+ (build_decl (BUILTINS_LOCATION, TYPE_DECL, get_identifier ("cp_v4uhi"),
+ v4uhi_type_node));
+ (*lang_hooks.decls.pushdecl)
+ (build_decl (BUILTINS_LOCATION, TYPE_DECL, get_identifier ("cp_v2usi"),
+ v2usi_type_node));
+
+ /* Intrinsics like mep_cadd3 are implemented with two groups of
+ instructions, one which uses UNSPECs and one which uses a specific
+ rtl code such as PLUS. Instructions in the latter group belong
+ to GROUP_KNOWN_CODE.
+
+ In such cases, the intrinsic will have two entries in the global
+ tables above. The unspec form is accessed using builtin functions
+ while the specific form is accessed using the mep_* enum in
+ mep-intrin.h.
+
+ The idea is that __cop arithmetic and builtin functions have
+ different optimization requirements. If mep_cadd3() appears in
+ the source code, the user will surely except gcc to use cadd3
+ rather than a work-alike such as add3. However, if the user
+ just writes "a + b", where a or b are __cop variables, it is
+ reasonable for gcc to choose a core instruction rather than
+ cadd3 if it believes that is more optimal. */
+ for (i = 0; i < ARRAY_SIZE (cgen_insns); i++)
+ if ((cgen_insns[i].groups & GROUP_KNOWN_CODE) == 0
+ && mep_intrinsic_insn[cgen_insns[i].intrinsic] >= 0)
+ {
+ tree ret_type = void_type_node;
+ tree bi_type;
+
+ if (i > 0 && cgen_insns[i].intrinsic == cgen_insns[i-1].intrinsic)
+ continue;
+
+ if (cgen_insns[i].cret_p)
+ ret_type = mep_cgen_regnum_to_type (cgen_insns[i].regnums[0].type);
+
+ bi_type = build_function_type (ret_type, 0);
+ add_builtin_function (cgen_intrinsics[cgen_insns[i].intrinsic],
+ bi_type,
+ cgen_insns[i].intrinsic, BUILT_IN_MD, NULL, NULL);
+ }
+}
+
+/* Report the unavailablity of the given intrinsic. */
+
+#if 1
+static void
+mep_intrinsic_unavailable (int intrinsic)
+{
+ static int already_reported_p[ARRAY_SIZE (cgen_intrinsics)];
+
+ if (already_reported_p[intrinsic])
+ return;
+
+ if (mep_intrinsic_insn[intrinsic] < 0)
+ error ("coprocessor intrinsic %qs is not available in this configuration",
+ cgen_intrinsics[intrinsic]);
+ else if (CGEN_CURRENT_GROUP == GROUP_VLIW)
+ error ("%qs is not available in VLIW functions",
+ cgen_intrinsics[intrinsic]);
+ else
+ error ("%qs is not available in non-VLIW functions",
+ cgen_intrinsics[intrinsic]);
+
+ already_reported_p[intrinsic] = 1;
+}
+#endif
+
+
+/* See if any implementation of INTRINSIC is available to the
+ current function. If so, store the most general implementation
+ in *INSN_PTR and return true. Return false otherwise. */
+
+static bool
+mep_get_intrinsic_insn (int intrinsic ATTRIBUTE_UNUSED, const struct cgen_insn **insn_ptr ATTRIBUTE_UNUSED)
+{
+ int i;
+
+ i = mep_intrinsic_insn[intrinsic];
+ while (i >= 0 && !CGEN_ENABLE_INSN_P (i))
+ i = mep_intrinsic_chain[i];
+
+ if (i >= 0)
+ {
+ *insn_ptr = &cgen_insns[i];
+ return true;
+ }
+ return false;
+}
+
+
+/* Like mep_get_intrinsic_insn, but with extra handling for moves.
+ If INTRINSIC is mep_cmov, but there is no pure CR <- CR move insn,
+ try using a work-alike instead. In this case, the returned insn
+ may have three operands rather than two. */
+
+static bool
+mep_get_move_insn (int intrinsic, const struct cgen_insn **cgen_insn)
+{
+ size_t i;
+
+ if (intrinsic == mep_cmov)
+ {
+ for (i = 0; i < ARRAY_SIZE (mep_cmov_insns); i++)
+ if (mep_get_intrinsic_insn (mep_cmov_insns[i], cgen_insn))
+ return true;
+ return false;
+ }
+ return mep_get_intrinsic_insn (intrinsic, cgen_insn);
+}
+
+
+/* If ARG is a register operand that is the same size as MODE, convert it
+ to MODE using a subreg. Otherwise return ARG as-is. */
+
+static rtx
+mep_convert_arg (enum machine_mode mode, rtx arg)
+{
+ if (GET_MODE (arg) != mode
+ && register_operand (arg, VOIDmode)
+ && GET_MODE_SIZE (GET_MODE (arg)) == GET_MODE_SIZE (mode))
+ return simplify_gen_subreg (mode, arg, GET_MODE (arg), 0);
+ return arg;
+}
+
+
+/* Apply regnum conversions to ARG using the description given by REGNUM.
+ Return the new argument on success and null on failure. */
+
+static rtx
+mep_convert_regnum (const struct cgen_regnum_operand *regnum, rtx arg)
+{
+ if (regnum->count == 0)
+ return arg;
+
+ if (GET_CODE (arg) != CONST_INT
+ || INTVAL (arg) < 0
+ || INTVAL (arg) >= regnum->count)
+ return 0;
+
+ return gen_rtx_REG (SImode, INTVAL (arg) + regnum->base);
+}
+
+
+/* Try to make intrinsic argument ARG match the given operand.
+ UNSIGNED_P is true if the argument has an unsigned type. */
+
+static rtx
+mep_legitimize_arg (const struct insn_operand_data *operand, rtx arg,
+ int unsigned_p)
+{
+ if (GET_CODE (arg) == CONST_INT)
+ {
+ /* CONST_INTs can only be bound to integer operands. */
+ if (GET_MODE_CLASS (operand->mode) != MODE_INT)
+ return 0;
+ }
+ else if (GET_CODE (arg) == CONST_DOUBLE)
+ /* These hold vector constants. */;
+ else if (GET_MODE_SIZE (GET_MODE (arg)) != GET_MODE_SIZE (operand->mode))
+ {
+ /* If the argument is a different size from what's expected, we must
+ have a value in the right mode class in order to convert it. */
+ if (GET_MODE_CLASS (operand->mode) != GET_MODE_CLASS (GET_MODE (arg)))
+ return 0;
+
+ /* If the operand is an rvalue, promote or demote it to match the
+ operand's size. This might not need extra instructions when
+ ARG is a register value. */
+ if (operand->constraint[0] != '=')
+ arg = convert_to_mode (operand->mode, arg, unsigned_p);
+ }
+
+ /* If the operand is an lvalue, bind the operand to a new register.
+ The caller will copy this value into ARG after the main
+ instruction. By doing this always, we produce slightly more
+ optimal code. */
+ /* But not for control registers. */
+ if (operand->constraint[0] == '='
+ && (! REG_P (arg)
+ || ! (CCR_REGNO_P (REGNO (arg)) || CR_REGNO_P (REGNO (arg)))
+ ))
+ return gen_reg_rtx (operand->mode);
+
+ /* Try simple mode punning. */
+ arg = mep_convert_arg (operand->mode, arg);
+ if (operand->predicate (arg, operand->mode))
+ return arg;
+
+ /* See if forcing the argument into a register will make it match. */
+ if (GET_CODE (arg) == CONST_INT || GET_CODE (arg) == CONST_DOUBLE)
+ arg = force_reg (operand->mode, arg);
+ else
+ arg = mep_convert_arg (operand->mode, force_reg (GET_MODE (arg), arg));
+ if (operand->predicate (arg, operand->mode))
+ return arg;
+
+ return 0;
+}
+
+
+/* Report that ARG cannot be passed to argument ARGNUM of intrinsic
+ function FNNAME. OPERAND describes the operand to which ARGNUM
+ is mapped. */
+
+static void
+mep_incompatible_arg (const struct insn_operand_data *operand, rtx arg,
+ int argnum, tree fnname)
+{
+ size_t i;
+
+ if (GET_CODE (arg) == CONST_INT)
+ for (i = 0; i < ARRAY_SIZE (cgen_immediate_predicates); i++)
+ if (operand->predicate == cgen_immediate_predicates[i].predicate)
+ {
+ const struct cgen_immediate_predicate *predicate;
+ HOST_WIDE_INT argval;
+
+ predicate = &cgen_immediate_predicates[i];
+ argval = INTVAL (arg);
+ if (argval < predicate->lower || argval >= predicate->upper)
+ error ("argument %d of %qE must be in the range %d...%d",
+ argnum, fnname, predicate->lower, predicate->upper - 1);
+ else
+ error ("argument %d of %qE must be a multiple of %d",
+ argnum, fnname, predicate->align);
+ return;
+ }
+
+ error ("incompatible type for argument %d of %qE", argnum, fnname);
+}
+
+static rtx
+mep_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
+ rtx subtarget ATTRIBUTE_UNUSED,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ int ignore ATTRIBUTE_UNUSED)
+{
+ rtx pat, op[10], arg[10];
+ unsigned int a;
+ int opindex, unsigned_p[10];
+ tree fndecl, args;
+ unsigned int n_args;
+ tree fnname;
+ const struct cgen_insn *cgen_insn;
+ const struct insn_data *idata;
+ int first_arg = 0;
+ int return_type = void_type_node;
+ int builtin_n_args;
+
+ fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
+ fnname = DECL_NAME (fndecl);
+
+ /* Find out which instruction we should emit. Note that some coprocessor
+ intrinsics may only be available in VLIW mode, or only in normal mode. */
+ if (!mep_get_intrinsic_insn (DECL_FUNCTION_CODE (fndecl), &cgen_insn))
+ {
+ mep_intrinsic_unavailable (DECL_FUNCTION_CODE (fndecl));
+ return error_mark_node;
+ }
+ idata = &insn_data[cgen_insn->icode];
+
+ builtin_n_args = cgen_insn->num_args;
+
+ if (cgen_insn->cret_p)
+ {
+ if (cgen_insn->cret_p > 1)
+ builtin_n_args ++;
+ first_arg = 1;
+ return_type = mep_cgen_regnum_to_type (cgen_insn->regnums[0].type);
+ builtin_n_args --;
+ }
+
+ /* Evaluate each argument. */
+ n_args = call_expr_nargs (exp);
+
+ if (n_args < builtin_n_args)
+ {
+ error ("too few arguments to %qE", fnname);
+ return error_mark_node;
+ }
+ if (n_args > builtin_n_args)
+ {
+ error ("too many arguments to %qE", fnname);
+ return error_mark_node;
+ }
+
+ for (a = first_arg; a < builtin_n_args+first_arg; a++)
+ {
+ tree value;
+
+ args = CALL_EXPR_ARG (exp, a-first_arg);
+
+ value = args;
+
+#if 0
+ if (cgen_insn->regnums[a].reference_p)
+ {
+ if (TREE_CODE (value) != ADDR_EXPR)
+ {
+ debug_tree(value);
+ error ("argument %d of %qE must be an address", a+1, fnname);
+ return error_mark_node;
+ }
+ value = TREE_OPERAND (value, 0);
+ }
+#endif
+
+ /* If the argument has been promoted to int, get the unpromoted
+ value. This is necessary when sub-int memory values are bound
+ to reference parameters. */
+ if (TREE_CODE (value) == NOP_EXPR
+ && TREE_TYPE (value) == integer_type_node
+ && INTEGRAL_TYPE_P (TREE_TYPE (TREE_OPERAND (value, 0)))
+ && (TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (value, 0)))
+ < TYPE_PRECISION (TREE_TYPE (value))))
+ value = TREE_OPERAND (value, 0);
+
+ /* If the argument has been promoted to double, get the unpromoted
+ SFmode value. This is necessary for FMAX support, for example. */
+ if (TREE_CODE (value) == NOP_EXPR
+ && SCALAR_FLOAT_TYPE_P (TREE_TYPE (value))
+ && SCALAR_FLOAT_TYPE_P (TREE_TYPE (TREE_OPERAND (value, 0)))
+ && TYPE_MODE (TREE_TYPE (value)) == DFmode
+ && TYPE_MODE (TREE_TYPE (TREE_OPERAND (value, 0))) == SFmode)
+ value = TREE_OPERAND (value, 0);
+
+ unsigned_p[a] = TYPE_UNSIGNED (TREE_TYPE (value));
+ arg[a] = expand_expr (value, NULL, VOIDmode, EXPAND_NORMAL);
+ arg[a] = mep_convert_regnum (&cgen_insn->regnums[a], arg[a]);
+ if (cgen_insn->regnums[a].reference_p)
+ {
+ tree pointed_to = TREE_TYPE (TREE_TYPE (value));
+ enum machine_mode pointed_mode = TYPE_MODE (pointed_to);
+
+ arg[a] = gen_rtx_MEM (pointed_mode, arg[a]);
+ }
+ if (arg[a] == 0)
+ {
+ error ("argument %d of %qE must be in the range %d...%d",
+ a + 1, fnname, 0, cgen_insn->regnums[a].count - 1);
+ return error_mark_node;
+ }
+ }
+
+ for (a=0; a<first_arg; a++)
+ {
+ if (a == 0 && target && GET_MODE (target) == idata->operand[0].mode)
+ arg[a] = target;
+ else
+ arg[a] = gen_reg_rtx (idata->operand[0].mode);
+ }
+
+ /* Convert the arguments into a form suitable for the intrinsic.
+ Report an error if this isn't possible. */
+ for (opindex = 0; opindex < idata->n_operands; opindex++)
+ {
+ a = cgen_insn->op_mapping[opindex];
+ op[opindex] = mep_legitimize_arg (&idata->operand[opindex],
+ arg[a], unsigned_p[a]);
+ if (op[opindex] == 0)
+ {
+ mep_incompatible_arg (&idata->operand[opindex],
+ arg[a], a + 1 - first_arg, fnname);
+ return error_mark_node;
+ }
+ }
+
+ /* Emit the instruction. */
+ pat = idata->genfun (op[0], op[1], op[2], op[3], op[4],
+ op[5], op[6], op[7], op[8], op[9]);
+
+ if (GET_CODE (pat) == SET
+ && GET_CODE (SET_DEST (pat)) == PC
+ && GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
+ emit_jump_insn (pat);
+ else
+ emit_insn (pat);
+
+ /* Copy lvalues back to their final locations. */
+ for (opindex = 0; opindex < idata->n_operands; opindex++)
+ if (idata->operand[opindex].constraint[0] == '=')
+ {
+ a = cgen_insn->op_mapping[opindex];
+ if (a >= first_arg)
+ {
+ if (GET_MODE_CLASS (GET_MODE (arg[a]))
+ != GET_MODE_CLASS (GET_MODE (op[opindex])))
+ emit_move_insn (arg[a], gen_lowpart (GET_MODE (arg[a]),
+ op[opindex]));
+ else
+ {
+ /* First convert the operand to the right mode, then copy it
+ into the destination. Doing the conversion as a separate
+ step (rather than using convert_move) means that we can
+ avoid creating no-op moves when ARG[A] and OP[OPINDEX]
+ refer to the same register. */
+ op[opindex] = convert_to_mode (GET_MODE (arg[a]),
+ op[opindex], unsigned_p[a]);
+ if (!rtx_equal_p (arg[a], op[opindex]))
+ emit_move_insn (arg[a], op[opindex]);
+ }
+ }
+ }
+
+ if (first_arg > 0 && target && target != op[0])
+ {
+ emit_move_insn (target, op[0]);
+ }
+
+ return target;
+}
+
+static bool
+mep_vector_mode_supported_p (enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ return false;
+}
+\f
+/* A subroutine of global_reg_mentioned_p, returns 1 if *LOC mentions
+ a global register. */
+
+static int
+global_reg_mentioned_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
+{
+ int regno;
+ rtx x = *loc;
+
+ if (! x)
+ return 0;
+
+ switch (GET_CODE (x))
+ {
+ case SUBREG:
+ if (REG_P (SUBREG_REG (x)))
+ {
+ if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
+ && global_regs[subreg_regno (x)])
+ return 1;
+ return 0;
+ }
+ break;
+
+ case REG:
+ regno = REGNO (x);
+ if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
+ return 1;
+ return 0;
+
+ case SCRATCH:
+ case PC:
+ case CC0:
+ case CONST_INT:
+ case CONST_DOUBLE:
+ case CONST:
+ case LABEL_REF:
+ return 0;
+
+ case CALL:
+ /* A non-constant call might use a global register. */
+ return 1;
+
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+/* Returns nonzero if X mentions a global register. */
+
+static int
+global_reg_mentioned_p (rtx x)
+{
+ if (INSN_P (x))
+ {
+ if (CALL_P (x))
+ {
+ if (! RTL_CONST_OR_PURE_CALL_P (x))
+ return 1;
+ x = CALL_INSN_FUNCTION_USAGE (x);
+ if (x == 0)
+ return 0;
+ }
+ else
+ x = PATTERN (x);
+ }
+
+ return for_each_rtx (&x, global_reg_mentioned_p_1, NULL);
+}
+/* Scheduling hooks for VLIW mode.
+
+ Conceptually this is very simple: we have a two-pack architecture
+ that takes one core insn and one coprocessor insn to make up either
+ a 32- or 64-bit instruction word (depending on the option bit set in
+ the chip). I.e. in VL32 mode, we can pack one 16-bit core insn and
+ one 16-bit cop insn; in VL64 mode we can pack one 16-bit core insn
+ and one 48-bit cop insn or two 32-bit core/cop insns.
+
+ In practice, instruction selection will be a bear. Consider in
+ VL64 mode the following insns
+
+ add $1, 1
+ cmov $cr0, $0
+
+ these cannot pack, since the add is a 16-bit core insn and cmov
+ is a 32-bit cop insn. However,
+
+ add3 $1, $1, 1
+ cmov $cr0, $0
+
+ packs just fine. For good VLIW code generation in VL64 mode, we
+ will have to have 32-bit alternatives for many of the common core
+ insns. Not implemented. */
+
+static int
+mep_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
+{
+ int cost_specified;
+
+ if (REG_NOTE_KIND (link) != 0)
+ {
+ /* See whether INSN and DEP_INSN are intrinsics that set the same
+ hard register. If so, it is more important to free up DEP_INSN
+ than it is to free up INSN.
+
+ Note that intrinsics like mep_mulr are handled differently from
+ the equivalent mep.md patterns. In mep.md, if we don't care
+ about the value of $lo and $hi, the pattern will just clobber
+ the registers, not set them. Since clobbers don't count as
+ output dependencies, it is often possible to reorder two mulrs,
+ even after reload.
+
+ In contrast, mep_mulr() sets both $lo and $hi to specific values,
+ so any pair of mep_mulr()s will be inter-dependent. We should
+ therefore give the first mep_mulr() a higher priority. */
+ if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
+ && global_reg_mentioned_p (PATTERN (insn))
+ && global_reg_mentioned_p (PATTERN (dep_insn)))
+ return 1;
+
+ /* If the dependence is an anti or output dependence, assume it
+ has no cost. */
+ return 0;
+ }
+
+ /* If we can't recognize the insns, we can't really do anything. */
+ if (recog_memoized (dep_insn) < 0)
+ return cost;
+
+ /* The latency attribute doesn't apply to MeP-h1: we use the stall
+ attribute instead. */
+ if (!TARGET_H1)
+ {
+ cost_specified = get_attr_latency (dep_insn);
+ if (cost_specified != 0)
+ return cost_specified;
+ }
+
+ return cost;
+}
+
+/* ??? We don't properly compute the length of a load/store insn,
+ taking into account the addressing mode. */
+
+static int
+mep_issue_rate (void)
+{
+ return TARGET_IVC2 ? 3 : 2;
+}
+
+/* Return true if function DECL was declared with the vliw attribute. */
+
+bool
+mep_vliw_function_p (tree decl)
+{
+ return lookup_attribute ("vliw", TYPE_ATTRIBUTES (TREE_TYPE (decl))) != 0;
+}
+
+static rtx
+mep_find_ready_insn (rtx *ready, int nready, enum attr_slot slot, int length)
+{
+ int i;
+
+ for (i = nready - 1; i >= 0; --i)
+ {
+ rtx insn = ready[i];
+ if (recog_memoized (insn) >= 0
+ && get_attr_slot (insn) == slot
+ && get_attr_length (insn) == length)
+ return insn;
+ }
+
+ return NULL_RTX;
+}
+
+static void
+mep_move_ready_insn (rtx *ready, int nready, rtx insn)
+{
+ int i;
+
+ for (i = 0; i < nready; ++i)
+ if (ready[i] == insn)
+ {
+ for (; i < nready - 1; ++i)
+ ready[i] = ready[i + 1];
+ ready[i] = insn;
+ return;
+ }
+
+ gcc_unreachable ();
+}
+
+static void
+mep_print_sched_insn (FILE *dump, rtx insn)
+{
+ const char *slots = "none";
+ const char *name = NULL;
+ int code;
+ char buf[30];
+
+ if (GET_CODE (PATTERN (insn)) == SET
+ || GET_CODE (PATTERN (insn)) == PARALLEL)
+ {
+ switch (get_attr_slots (insn))
+ {
+ case SLOTS_CORE: slots = "core"; break;
+ case SLOTS_C3: slots = "c3"; break;
+ case SLOTS_P0: slots = "p0"; break;
+ case SLOTS_P0_P0S: slots = "p0,p0s"; break;
+ case SLOTS_P0_P1: slots = "p0,p1"; break;
+ case SLOTS_P0S: slots = "p0s"; break;
+ case SLOTS_P0S_P1: slots = "p0s,p1"; break;
+ case SLOTS_P1: slots = "p1"; break;
+ default:
+ sprintf(buf, "%d", get_attr_slots (insn));
+ slots = buf;
+ break;
+ }
+ }
+ if (GET_CODE (PATTERN (insn)) == USE)
+ slots = "use";
+
+ code = INSN_CODE (insn);
+ if (code >= 0)
+ name = get_insn_name (code);
+ if (!name)
+ name = "{unknown}";
+
+ fprintf (dump,
+ "insn %4d %4d %8s %s\n",
+ code,
+ INSN_UID (insn),
+ name,
+ slots);
+}
+
+static int
+mep_sched_reorder (FILE *dump ATTRIBUTE_UNUSED,
+ int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
+ int *pnready, int clock ATTRIBUTE_UNUSED)
+{
+ int nready = *pnready;
+ rtx core_insn, cop_insn;
+ int i;
+
+ if (dump && sched_verbose > 1)
+ {
+ fprintf (dump, "\nsched_reorder: clock %d nready %d\n", clock, nready);
+ for (i=0; i<nready; i++)
+ mep_print_sched_insn (dump, ready[i]);
+ fprintf (dump, "\n");
+ }
+
+ if (!mep_vliw_function_p (cfun->decl))
+ return 1;
+ if (nready < 2)
+ return 1;
+
+ /* IVC2 uses a DFA to determine what's ready and what's not. */
+ if (TARGET_IVC2)
+ return nready;
+
+ /* We can issue either a core or coprocessor instruction.
+ Look for a matched pair of insns to reorder. If we don't
+ find any, don't second-guess the scheduler's priorities. */
+
+ if ((core_insn = mep_find_ready_insn (ready, nready, SLOT_CORE, 2))
+ && (cop_insn = mep_find_ready_insn (ready, nready, SLOT_COP,
+ TARGET_OPT_VL64 ? 6 : 2)))
+ ;
+ else if (TARGET_OPT_VL64
+ && (core_insn = mep_find_ready_insn (ready, nready, SLOT_CORE, 4))
+ && (cop_insn = mep_find_ready_insn (ready, nready, SLOT_COP, 4)))
+ ;
+ else
+ /* We didn't find a pair. Issue the single insn at the head
+ of the ready list. */
+ return 1;
+
+ /* Reorder the two insns first. */
+ mep_move_ready_insn (ready, nready, core_insn);
+ mep_move_ready_insn (ready, nready - 1, cop_insn);
+ return 2;
+}
+
+/* A for_each_rtx callback. Return true if *X is a register that is
+ set by insn PREV. */
+
+static int
+mep_store_find_set (rtx *x, void *prev)
+{
+ return REG_P (*x) && reg_set_p (*x, (const_rtx) prev);
+}
+
+/* Like mep_store_bypass_p, but takes a pattern as the second argument,
+ not the containing insn. */
+
+static bool
+mep_store_data_bypass_1 (rtx prev, rtx pat)
+{
+ /* Cope with intrinsics like swcpa. */
+ if (GET_CODE (pat) == PARALLEL)
+ {
+ int i;
+
+ for (i = 0; i < XVECLEN (pat, 0); i++)
+ if (mep_store_data_bypass_p (prev, XVECEXP (pat, 0, i)))
+ return true;
+
+ return false;
+ }
+
+ /* Check for some sort of store. */
+ if (GET_CODE (pat) != SET
+ || GET_CODE (SET_DEST (pat)) != MEM)
+ return false;
+
+ /* Intrinsics use patterns of the form (set (mem (scratch)) (unspec ...)).
+ The first operand to the unspec is the store data and the other operands
+ are used to calculate the address. */
+ if (GET_CODE (SET_SRC (pat)) == UNSPEC)
+ {
+ rtx src;
+ int i;
+
+ src = SET_SRC (pat);
+ for (i = 1; i < XVECLEN (src, 0); i++)
+ if (for_each_rtx (&XVECEXP (src, 0, i), mep_store_find_set, prev))
+ return false;
+
+ return true;
+ }
+
+ /* Otherwise just check that PREV doesn't modify any register mentioned
+ in the memory destination. */
+ return !for_each_rtx (&SET_DEST (pat), mep_store_find_set, prev);
+}
+
+/* Return true if INSN is a store instruction and if the store address
+ has no true dependence on PREV. */
+
+bool
+mep_store_data_bypass_p (rtx prev, rtx insn)
+{
+ return INSN_P (insn) ? mep_store_data_bypass_1 (prev, PATTERN (insn)) : false;
+}
+
+/* A for_each_rtx subroutine of mep_mul_hilo_bypass_p. Return 1 if *X
+ is a register other than LO or HI and if PREV sets *X. */
+
+static int
+mep_mul_hilo_bypass_1 (rtx *x, void *prev)
+{
+ return (REG_P (*x)
+ && REGNO (*x) != LO_REGNO
+ && REGNO (*x) != HI_REGNO
+ && reg_set_p (*x, (const_rtx) prev));
+}
+
+/* Return true if, apart from HI/LO, there are no true dependencies
+ between multiplication instructions PREV and INSN. */
+
+bool
+mep_mul_hilo_bypass_p (rtx prev, rtx insn)
+{
+ rtx pat;
+
+ pat = PATTERN (insn);
+ if (GET_CODE (pat) == PARALLEL)
+ pat = XVECEXP (pat, 0, 0);
+ return (GET_CODE (pat) == SET
+ && !for_each_rtx (&SET_SRC (pat), mep_mul_hilo_bypass_1, prev));
+}
+
+/* Return true if INSN is an ldc instruction that issues to the
+ MeP-h1 integer pipeline. This is true for instructions that
+ read from PSW, LP, SAR, HI and LO. */
+
+bool
+mep_ipipe_ldc_p (rtx insn)
+{
+ rtx pat, src;
+
+ pat = PATTERN (insn);
+
+ /* Cope with instrinsics that set both a hard register and its shadow.
+ The set of the hard register comes first. */
+ if (GET_CODE (pat) == PARALLEL)
+ pat = XVECEXP (pat, 0, 0);
+
+ if (GET_CODE (pat) == SET)
+ {
+ src = SET_SRC (pat);
+
+ /* Cope with intrinsics. The first operand to the unspec is
+ the source register. */
+ if (GET_CODE (src) == UNSPEC || GET_CODE (src) == UNSPEC_VOLATILE)
+ src = XVECEXP (src, 0, 0);
+
+ if (REG_P (src))
+ switch (REGNO (src))
+ {
+ case PSW_REGNO:
+ case LP_REGNO:
+ case SAR_REGNO:
+ case HI_REGNO:
+ case LO_REGNO:
+ return true;
+ }
+ }
+ return false;
+}
+
+/* Create a VLIW bundle from core instruction CORE and coprocessor
+ instruction COP. COP always satisfies INSN_P, but CORE can be
+ either a new pattern or an existing instruction.
+
+ Emit the bundle in place of COP and return it. */
+
+static rtx
+mep_make_bundle (rtx core, rtx cop)
+{
+ rtx insn;
+
+ /* If CORE is an existing instruction, remove it, otherwise put
+ the new pattern in an INSN harness. */
+ if (INSN_P (core))
+ remove_insn (core);
+ else
+ core = make_insn_raw (core);
+
+ /* Generate the bundle sequence and replace COP with it. */
+ insn = gen_rtx_SEQUENCE (VOIDmode, gen_rtvec (2, core, cop));
+ insn = emit_insn_after (insn, cop);
+ remove_insn (cop);
+
+ /* Set up the links of the insns inside the SEQUENCE. */
+ PREV_INSN (core) = PREV_INSN (insn);
+ NEXT_INSN (core) = cop;
+ PREV_INSN (cop) = core;
+ NEXT_INSN (cop) = NEXT_INSN (insn);
+
+ /* Set the VLIW flag for the coprocessor instruction. */
+ PUT_MODE (core, VOIDmode);
+ PUT_MODE (cop, BImode);
+
+ /* Derive a location for the bundle. Individual instructions cannot
+ have their own location because there can be no assembler labels
+ between CORE and COP. */
+ INSN_LOCATOR (insn) = INSN_LOCATOR (INSN_LOCATOR (core) ? core : cop);
+ INSN_LOCATOR (core) = 0;
+ INSN_LOCATOR (cop) = 0;
+
+ return insn;
+}
+
+/* A helper routine for ms1_insn_dependent_p called through note_stores. */
+
+static void
+mep_insn_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
+{
+ rtx * pinsn = (rtx *) data;
+
+ if (*pinsn && reg_mentioned_p (x, *pinsn))
+ *pinsn = NULL_RTX;
+}
+
+/* Return true if anything in insn X is (anti,output,true) dependent on
+ anything in insn Y. */
+
+static int
+mep_insn_dependent_p (rtx x, rtx y)
+{
+ rtx tmp;
+
+ gcc_assert (INSN_P (x));
+ gcc_assert (INSN_P (y));
+
+ tmp = PATTERN (y);
+ note_stores (PATTERN (x), mep_insn_dependent_p_1, &tmp);
+ if (tmp == NULL_RTX)
+ return 1;
+
+ tmp = PATTERN (x);
+ note_stores (PATTERN (y), mep_insn_dependent_p_1, &tmp);
+ if (tmp == NULL_RTX)
+ return 1;
+
+ return 0;
+}
+
+static int
+core_insn_p (rtx insn)
+{
+ if (GET_CODE (PATTERN (insn)) == USE)
+ return 0;
+ if (get_attr_slot (insn) == SLOT_CORE)
+ return 1;
+ return 0;
+}
+
+/* Mark coprocessor instructions that can be bundled together with
+ the immediately preceeding core instruction. This is later used
+ to emit the "+" that tells the assembler to create a VLIW insn.
+
+ For unbundled insns, the assembler will automatically add coprocessor
+ nops, and 16-bit core nops. Due to an apparent oversight in the
+ spec, the assembler will _not_ automatically add 32-bit core nops,
+ so we have to emit those here.
+
+ Called from mep_insn_reorg. */
+
+static void
+mep_bundle_insns (rtx insns)
+{
+ rtx insn, last = NULL_RTX, first = NULL_RTX;
+ int saw_scheduling = 0;
+
+ /* Only do bundling if we're in vliw mode. */
+ if (!mep_vliw_function_p (cfun->decl))
+ return;
+
+ /* The first insn in a bundle are TImode, the remainder are
+ VOIDmode. After this function, the first has VOIDmode and the
+ rest have BImode. */
+
+ /* First, move any NOTEs that are within a bundle, to the beginning
+ of the bundle. */
+ for (insn = insns; insn ; insn = NEXT_INSN (insn))
+ {
+ if (NOTE_P (insn) && first)
+ /* Don't clear FIRST. */;
+
+ else if (INSN_P (insn) && GET_MODE (insn) == TImode)
+ first = insn;
+
+ else if (INSN_P (insn) && GET_MODE (insn) == VOIDmode && first)
+ {
+ rtx note, prev;
+
+ /* INSN is part of a bundle; FIRST is the first insn in that
+ bundle. Move all intervening notes out of the bundle.
+ In addition, since the debug pass may insert a label
+ whenever the current line changes, set the location info
+ for INSN to match FIRST. */
+
+ INSN_LOCATOR (insn) = INSN_LOCATOR (first);
+
+ note = PREV_INSN (insn);
+ while (note && note != first)
+ {
+ prev = PREV_INSN (note);
+
+ if (NOTE_P (note))
+ {
+ /* Remove NOTE from here... */
+ PREV_INSN (NEXT_INSN (note)) = PREV_INSN (note);
+ NEXT_INSN (PREV_INSN (note)) = NEXT_INSN (note);
+ /* ...and put it in here. */
+ NEXT_INSN (note) = first;
+ PREV_INSN (note) = PREV_INSN (first);
+ NEXT_INSN (PREV_INSN (note)) = note;
+ PREV_INSN (NEXT_INSN (note)) = note;
+ }
+
+ note = prev;
+ }
+ }
+
+ else if (!INSN_P (insn))
+ first = 0;
+ }
+
+ /* Now fix up the bundles. */
+ for (insn = insns; insn ; insn = NEXT_INSN (insn))
+ {
+ if (NOTE_P (insn))
+ continue;
+
+ if (!INSN_P (insn))
+ {
+ last = 0;
+ continue;
+ }
+
+ /* If we're not optimizing enough, there won't be scheduling
+ info. We detect that here. */
+ if (GET_MODE (insn) == TImode)
+ saw_scheduling = 1;
+ if (!saw_scheduling)
+ continue;
+
+ if (TARGET_IVC2)
+ {
+ rtx core_insn = NULL_RTX;
+
+ /* IVC2 slots are scheduled by DFA, so we just accept
+ whatever the scheduler gives us. However, we must make
+ sure the core insn (if any) is the first in the bundle.
+ The IVC2 assembler can insert whatever NOPs are needed,
+ and allows a COP insn to be first. */
+
+ if (INSN_P (insn)
+ && GET_CODE (PATTERN (insn)) != USE
+ && GET_MODE (insn) == TImode)
+ {
+ for (last = insn;
+ NEXT_INSN (last)
+ && GET_MODE (NEXT_INSN (last)) == VOIDmode
+ && INSN_P (NEXT_INSN (last));
+ last = NEXT_INSN (last))
+ {
+ if (core_insn_p (last))
+ core_insn = last;
+ }
+ if (core_insn_p (last))
+ core_insn = last;
+
+ if (core_insn && core_insn != insn)
+ {
+ /* Swap core insn to first in the bundle. */
+
+ /* Remove core insn. */
+ if (PREV_INSN (core_insn))
+ NEXT_INSN (PREV_INSN (core_insn)) = NEXT_INSN (core_insn);
+ if (NEXT_INSN (core_insn))
+ PREV_INSN (NEXT_INSN (core_insn)) = PREV_INSN (core_insn);
+
+ /* Re-insert core insn. */
+ PREV_INSN (core_insn) = PREV_INSN (insn);
+ NEXT_INSN (core_insn) = insn;
+
+ if (PREV_INSN (core_insn))
+ NEXT_INSN (PREV_INSN (core_insn)) = core_insn;
+ PREV_INSN (insn) = core_insn;
+
+ PUT_MODE (core_insn, TImode);
+ PUT_MODE (insn, VOIDmode);
+ }
+ }
+
+ /* The first insn has TImode, the rest have VOIDmode */
+ if (GET_MODE (insn) == TImode)
+ PUT_MODE (insn, VOIDmode);
+ else
+ PUT_MODE (insn, BImode);
+ continue;
+ }
+
+ PUT_MODE (insn, VOIDmode);
+ if (recog_memoized (insn) >= 0
+ && get_attr_slot (insn) == SLOT_COP)
+ {
+ if (GET_CODE (insn) == JUMP_INSN
+ || ! last
+ || recog_memoized (last) < 0
+ || get_attr_slot (last) != SLOT_CORE
+ || (get_attr_length (insn)
+ != (TARGET_OPT_VL64 ? 8 : 4) - get_attr_length (last))
+ || mep_insn_dependent_p (insn, last))
+ {
+ switch (get_attr_length (insn))
+ {
+ case 8:
+ break;
+ case 6:
+ insn = mep_make_bundle (gen_nop (), insn);
+ break;
+ case 4:
+ if (TARGET_OPT_VL64)
+ insn = mep_make_bundle (gen_nop32 (), insn);
+ break;
+ case 2:
+ if (TARGET_OPT_VL64)
+ error ("2 byte cop instructions are"
+ " not allowed in 64-bit VLIW mode");
+ else
+ insn = mep_make_bundle (gen_nop (), insn);
+ break;
+ default:
+ error ("unexpected %d byte cop instruction",
+ get_attr_length (insn));
+ break;
+ }
+ }
+ else
+ insn = mep_make_bundle (last, insn);
+ }
+
+ last = insn;
+ }
+}
+
+
+/* Try to instantiate INTRINSIC with the operands given in OPERANDS.
+ Return true on success. This function can fail if the intrinsic
+ is unavailable or if the operands don't satisfy their predicates. */
+
+bool
+mep_emit_intrinsic (int intrinsic, const rtx *operands)
+{
+ const struct cgen_insn *cgen_insn;
+ const struct insn_data *idata;
+ rtx newop[10];
+ int i;
+
+ if (!mep_get_intrinsic_insn (intrinsic, &cgen_insn))
+ return false;
+
+ idata = &insn_data[cgen_insn->icode];
+ for (i = 0; i < idata->n_operands; i++)
+ {
+ newop[i] = mep_convert_arg (idata->operand[i].mode, operands[i]);
+ if (!idata->operand[i].predicate (newop[i], idata->operand[i].mode))
+ return false;
+ }
+
+ emit_insn (idata->genfun (newop[0], newop[1], newop[2],
+ newop[3], newop[4], newop[5],
+ newop[6], newop[7], newop[8]));
+
+ return true;
+}
+
+
+/* Apply the given unary intrinsic to OPERANDS[1] and store it on
+ OPERANDS[0]. Report an error if the instruction could not
+ be synthesized. OPERANDS[1] is a register_operand. For sign
+ and zero extensions, it may be smaller than SImode. */
+
+bool
+mep_expand_unary_intrinsic (int ATTRIBUTE_UNUSED intrinsic,
+ rtx * operands ATTRIBUTE_UNUSED)
+{
+ return false;
+}
+
+
+/* Likewise, but apply a binary operation to OPERANDS[1] and
+ OPERANDS[2]. OPERANDS[1] is a register_operand, OPERANDS[2]
+ can be a general_operand.
+
+ IMMEDIATE and IMMEDIATE3 are intrinsics that take an immediate
+ third operand. REG and REG3 take register operands only. */
+
+bool
+mep_expand_binary_intrinsic (int ATTRIBUTE_UNUSED immediate,
+ int ATTRIBUTE_UNUSED immediate3,
+ int ATTRIBUTE_UNUSED reg,
+ int ATTRIBUTE_UNUSED reg3,
+ rtx * operands ATTRIBUTE_UNUSED)
+{
+ return false;
+}
+
+static bool
+mep_rtx_cost (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total, bool ATTRIBUTE_UNUSED speed_t)
+{
+ switch (code)
+ {
+ case CONST_INT:
+ if (INTVAL (x) >= -128 && INTVAL (x) < 127)
+ *total = 0;
+ else if (INTVAL (x) >= -32768 && INTVAL (x) < 65536)
+ *total = 1;
+ else
+ *total = 3;
+ return true;
+
+ case SYMBOL_REF:
+ *total = optimize_size ? COSTS_N_INSNS (0) : COSTS_N_INSNS (1);
+ return true;
+
+ case MULT:
+ *total = (GET_CODE (XEXP (x, 1)) == CONST_INT
+ ? COSTS_N_INSNS (3)
+ : COSTS_N_INSNS (2));
+ return true;
+ }
+ return false;
+}
+
+static int
+mep_address_cost (rtx addr ATTRIBUTE_UNUSED, bool ATTRIBUTE_UNUSED speed_p)
+{
+ return 1;
+}
+
+static bool
+mep_handle_option (size_t code,
+ const char *arg ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED)
+{
+ int i;
+
+ switch (code)
+ {
+ case OPT_mall_opts:
+ target_flags |= MEP_ALL_OPTS;
+ break;
+
+ case OPT_mno_opts:
+ target_flags &= ~ MEP_ALL_OPTS;
+ break;
+
+ case OPT_mcop64:
+ target_flags |= MASK_COP;
+ target_flags |= MASK_64BIT_CR_REGS;
+ break;
+
+ case OPT_mtiny_:
+ option_mtiny_specified = 1;
+
+ case OPT_mivc2:
+ target_flags |= MASK_COP;
+ target_flags |= MASK_64BIT_CR_REGS;
+ target_flags |= MASK_VLIW;
+ target_flags |= MASK_OPT_VL64;
+ target_flags |= MASK_IVC2;
+
+ for (i=0; i<32; i++)
+ fixed_regs[i+48] = 0;
+ for (i=0; i<32; i++)
+ call_used_regs[i+48] = 1;
+ for (i=6; i<8; i++)
+ call_used_regs[i+48] = 0;
+
+ call_used_regs[FIRST_CCR_REGNO + 1] = 0;
+ fixed_regs[FIRST_CCR_REGNO + 1] = 0;
+ for (i=8; i<=11; i++)
+ {
+ call_used_regs[FIRST_CCR_REGNO + i] = 0;
+ fixed_regs[FIRST_CCR_REGNO + i] = 0;
+ }
+ for (i=16; i<=31; i++)
+ {
+ call_used_regs[FIRST_CCR_REGNO + i] = 0;
+ fixed_regs[FIRST_CCR_REGNO + i] = 0;
+ }
+
+#define RN(n,s) reg_names[FIRST_CCR_REGNO + n] = s
+ RN (0, "$csar0");
+ RN (1, "$cc");
+ RN (4, "$cofr0");
+ RN (5, "$cofr1");
+ RN (6, "$cofa0");
+ RN (7, "$cofa1");
+ RN (15, "$csar1");
+
+ RN (16, "$acc0_0");
+ RN (17, "$acc0_1");
+ RN (18, "$acc0_2");
+ RN (19, "$acc0_3");
+ RN (20, "$acc0_4");
+ RN (21, "$acc0_5");
+ RN (22, "$acc0_6");
+ RN (23, "$acc0_7");
+
+ RN (24, "$acc1_0");
+ RN (25, "$acc1_1");
+ RN (26, "$acc1_2");
+ RN (27, "$acc1_3");
+ RN (28, "$acc1_4");
+ RN (29, "$acc1_5");
+ RN (30, "$acc1_6");
+ RN (31, "$acc1_7");
+#undef RN
+
+ break;
+
+ default:
+ break;
+ }
+ return TRUE;
+}
+
+static void
+mep_asm_init_sections (void)
+{
+ based_section
+ = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
+ "\t.section .based,\"aw\"");
+
+ tinybss_section
+ = get_unnamed_section (SECTION_WRITE | SECTION_BSS, output_section_asm_op,
+ "\t.section .sbss,\"aw\"");
+
+ sdata_section
+ = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
+ "\t.section .sdata,\"aw\",@progbits");
+
+ far_section
+ = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
+ "\t.section .far,\"aw\"");
+
+ farbss_section
+ = get_unnamed_section (SECTION_WRITE | SECTION_BSS, output_section_asm_op,
+ "\t.section .farbss,\"aw\"");
+
+ frodata_section
+ = get_unnamed_section (0, output_section_asm_op,
+ "\t.section .frodata,\"a\"");
+
+ srodata_section
+ = get_unnamed_section (0, output_section_asm_op,
+ "\t.section .srodata,\"a\"");
+
+}
+
+#include "gt-mep.h"
--- /dev/null
+(include "mep-default.cpu")
--- /dev/null
+/* Definitions for Toshiba Media Processor
+ Copyright (C) 2001, 2003, 2004, 2005, 2007, 2008, 2009
+ Free Software Foundation, Inc.
+ Contributed by Red Hat, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+\f
+
+#undef CPP_SPEC
+#define CPP_SPEC "\
+-D__MEP__ -D__MeP__ \
+-D__section(_x)=__attribute__((section(_x))) \
+-D__align(_x)=__attribute__((aligned(_x))) \
+-D__io(_x)=__attribute__((io(_x))) \
+-D__cb(_x)=__attribute__((cb(_x))) \
+-D__based=__attribute__((based)) \
+-D__tiny=__attribute__((tiny)) \
+-D__near=__attribute__((near)) \
+-D__far=__attribute__((far)) \
+-D__vliw=__attribute__((vliw)) \
+-D__interrupt=__attribute__((interrupt)) \
+-D__disinterrupt=__attribute__((disinterrupt)) \
+-D__cop=__attribute__((cop)) \
+%{!meb:%{!mel:-D__BIG_ENDIAN__}} \
+%{meb:-U__LITTLE_ENDIAN__ -D__BIG_ENDIAN__} \
+%{mel:-U__BIG_ENDIAN__ -D__LITTLE_ENDIAN__} \
+%{mconfig=*:-D__MEP_CONFIG_%*} \
+%{mivc2:-D__MEP_CONFIG_CP_DATA_BUS_WIDTH=64} \
+"
+
+#undef CC1_SPEC
+#define CC1_SPEC "%{!mlibrary:%(config_cc_spec)} \
+%{!.cc:%{O2:%{!funroll*:--param max-completely-peeled-insns=10 \
+ --param max-unrolled-insns=10 -funroll-loops}}}"
+
+#undef CC1PLUS_SPEC
+#define CC1PLUS_SPEC "%{!mlibrary:%(config_cc_spec)}"
+
+#undef ASM_SPEC
+#define ASM_SPEC "%{mconfig=*} %{meb:-EB} %{mel:-EL} \
+%{mno-satur} %{msatur} %{mno-clip} %{mclip} %{mno-minmax} %{mminmax} \
+%{mno-absdiff} %{mabsdiff} %{mno-leadz} %{mleadz} %{mno-bitops} %{mbitops} \
+%{mno-div} %{mdiv} %{mno-mult} %{mmult} %{mno-average} %{maverage} \
+%{mcop32} %{mno-debug} %{mdebug} %{mlibrary}"
+
+/* The MeP config tool will edit this spec. */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "%{msdram:%{msim:simsdram-crt0.o%s}} \
+%{mno-sdram:%{msim:sim-crt0.o%s}} \
+%{msdram:%{!msim*:sdram-crt0.o%s}} \
+%{mno-sdram:%{!msim*:crt0.o%s}} \
+%(config_start_spec) \
+%{msimnovec:simnovec-crt0.o%s} \
+crtbegin.o%s"
+
+#undef LIB_SPEC
+#define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) %(config_link_spec)"
+
+#undef LINK_SPEC
+#define LINK_SPEC "%{meb:-EB} %{mel:-EL}"
+
+#undef ENDFILE_SPEC
+#define ENDFILE_SPEC "crtend.o%s %{msim*:sim-crtn.o%s}%{!msim*:crtn.o%s}"
+
+/* The MeP config tool will edit this spec. */
+#define CONFIG_CC_SPEC "\
+%{mconfig=default: -mbitops -mleadz -mabsdiff -maverage -mminmax -mclip -msatur -mvl64 -mvliw -mcop64 -D__MEP_CONFIG_CP_DATA_BUS_WIDTH=64 -mivc2}\
+"
+/* end-config-cc-spec */
+
+/* The MeP config tool will edit this spec. */
+#define CONFIG_LINK_SPEC "\
+%{mconfig=default: %{!T*:-Tdefault.ld}}\
+"
+/* end-config-link-spec */
+
+/* The MeP config tool will edit this spec. */
+#define CONFIG_START_SPEC "\
+%{!msdram:%{!mno-sdram:%{!msim*:crt0.o%s}}} \
+%{!msdram:%{!mno-sdram:%{msim:sim-crt0.o%s}}} \
+"
+/* end-config-start-spec */
+
+#define EXTRA_SPECS \
+ { "config_cc_spec", CONFIG_CC_SPEC }, \
+ { "config_link_spec", CONFIG_LINK_SPEC }, \
+ { "config_start_spec", CONFIG_START_SPEC },
+\f
+
+#define TARGET_CPU_CPP_BUILTINS() \
+ do \
+ { \
+ builtin_define_std ("mep"); \
+ builtin_assert ("machine=mep"); \
+ } \
+ while (0)
+
+extern int target_flags;
+
+/* Controlled by MeP-Integrator. */
+#define TARGET_H1 0
+
+#define MEP_ALL_OPTS (MASK_OPT_AVERAGE \
+ | MASK_OPT_MULT \
+ | MASK_OPT_DIV \
+ | MASK_OPT_BITOPS \
+ | MASK_OPT_LEADZ \
+ | MASK_OPT_ABSDIFF \
+ | MASK_OPT_MINMAX \
+ | MASK_OPT_CLIP \
+ | MASK_OPT_SATUR )
+
+#define TARGET_DEFAULT (MASK_IO_VOLATILE | MASK_OPT_REPEAT | MEP_ALL_OPTS | MASK_LITTLE_ENDIAN)
+
+#define TARGET_IO_NO_VOLATILE (! (target_flags & MASK_IO_VOLATILE))
+#define TARGET_OPT_NOREPEAT (! (target_flags & MASK_OPT_REPEAT))
+#define TARGET_32BIT_CR_REGS (! (target_flags & MASK_64BIT_CR_REGS))
+#define TARGET_BIG_ENDIAN (! (target_flags & MASK_LITTLE_ENDIAN))
+
+#define TARGET_COPRO_MULT 0
+
+#define TARGET_VERSION fprintf (stderr, " (Toshiba Media Processor (MeP))");
+
+#define OVERRIDE_OPTIONS mep_override_options ();
+
+/* The MeP config tool will add TARGET_OPTION_TRANSLATE_TABLE here. */
+#define TARGET_OPTION_TRANSLATE_TABLE \
+ {"-mall-opts", "-maverage -mmult -mdiv -mbitops -mleadz \
+ -mabsdiff -mminmax -mclip -msatur -mdebug" }, \
+ {"-mno-opts", "-mno-average -mno-mult -mno-div -mno-bitops -mno-leadz \
+ -mno-absdiff -mno-minmax -mno-clip -mno-satur -mno-debug" }, \
+ {"-mfar", "-ml -mtf -mc=far" } \
+/* start-target-option-table */ \
+, {"-mconfig=default", "-mconfig=default -mmult -mdiv -D__MEP_CONFIG_ISA=1" } \
+/* end-target-option-table */
+
+/* The MeP config tool will replace this as appropriate. */
+#define DEFAULT_ENDIAN_SPEC "%{!meb: -mel}"
+
+/* The MeP config tool will replace this with an -mconfig= switch. */
+#define LIBRARY_CONFIG_SPEC "-mconfig=default"
+
+/* Don't add an endian option when building the libraries. */
+#define DRIVER_SELF_SPECS \
+ "%{!mlibrary:" DEFAULT_ENDIAN_SPEC "}", \
+ "%{mlibrary: " LIBRARY_CONFIG_SPEC " %{!mel:-meb}}"
+
+/* The MeP config tool will add COPROC_SELECTION_TABLE here. */
+/* start-coproc-selection-table */
+#define COPROC_SELECTION_TABLE \
+{"default", ISA_EXT1}
+/* end-coproc-selection-table */
+
+#define CAN_DEBUG_WITHOUT_FP
+
+#define OPTIMIZATION_OPTIONS(LEVEL, FOR_SIZE) mep_optimization_options ()
+\f
+
+#define BITS_BIG_ENDIAN 0
+#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN ? 0 : 1)
+#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN ? 0 : 1)
+
+#ifdef __LITTLE_ENDIAN__
+#define LIBGCC2_WORDS_BIG_ENDIAN 0
+#else
+#define LIBGCC2_WORDS_BIG_ENDIAN 1
+#endif
+
+#define UNITS_PER_WORD 4
+
+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
+ do \
+ { \
+ if (GET_MODE_CLASS (MODE) == MODE_INT \
+ && GET_MODE_SIZE (MODE) < 4) \
+ (MODE) = SImode; \
+ } \
+ while (0)
+
+#define PARM_BOUNDARY 32
+#define STACK_BOUNDARY 32
+#define PREFERRED_STACK_BOUNDARY 64
+#define FUNCTION_BOUNDARY 16
+#define BIGGEST_ALIGNMENT 64
+
+#define DATA_ALIGNMENT(TYPE, ALIGN) \
+ (TREE_CODE (TYPE) == ARRAY_TYPE \
+ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
+ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
+
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
+ (TREE_CODE (EXP) == STRING_CST \
+ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
+
+#define STRICT_ALIGNMENT 1
+
+#define PCC_BITFIELD_TYPE_MATTERS 1
+
+#define DEFAULT_VTABLE_THUNKS 1
+
+\f
+#define INT_TYPE_SIZE 32
+#define SHORT_TYPE_SIZE 16
+#define LONG_TYPE_SIZE 32
+#define LONG_LONG_TYPE_SIZE 64
+#define CHAR_TYPE_SIZE 8
+#define FLOAT_TYPE_SIZE 32
+#define DOUBLE_TYPE_SIZE 64
+#define LONG_DOUBLE_TYPE_SIZE 64
+#define DEFAULT_SIGNED_CHAR 1
+\f
+/* Register numbers:
+ 0..15 core registers
+ 16..47 control registers
+ 48..79 coprocessor registers
+ 80..111 coprocessor control registers
+ 112 virtual arg pointer register */
+
+#define FIRST_PSEUDO_REGISTER (LAST_SHADOW_REGISTER + 1)
+
+ /* R12 is optionally FP. R13 is TP, R14 is GP, R15 is SP. */
+ /* hi and lo can be used as general registers. Others have
+ immutable bits. */
+/* A "1" here means the register is generally not available to gcc,
+ and is assumed to remain unchanged or unused throughout. */
+#define FIXED_REGISTERS { \
+ /* core registers */ \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
+ /* control registers */ \
+ 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ /* coprocessor registers */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ /* coprocessor control registers */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ /* virtual arg pointer */ \
+ 1, FIXED_SHADOW_REGISTERS \
+ }
+
+/* This is a call-clobbered reg not used for args or return value,
+ that we use as a temp for saving control registers in the prolog
+ and restoring them in the epilog. */
+#define REGSAVE_CONTROL_TEMP 11
+
+/* A "1" here means a register may be changed by a function without
+ needing to preserve its previous value. */
+#define CALL_USED_REGISTERS { \
+ /* core registers */ \
+ 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, \
+ /* control registers */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ /* coprocessor registers */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ /* coprocessor control registers */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ /* virtual arg pointer */ \
+ 1, CALL_USED_SHADOW_REGISTERS \
+ }
+
+#define CONDITIONAL_REGISTER_USAGE \
+ mep_conditional_register_usage (fixed_regs, call_used_regs);
+
+#define REG_ALLOC_ORDER { \
+ /* core registers */ \
+ 3, 2, 1, 0, 9, 10, 11, 12, 4, 5, 6, 7, 8, 13, 14, 15, \
+ /* control registers */ \
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
+ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
+ /* coprocessor registers */ \
+ /* Prefer to use the non-loadable registers when looking for a \
+ member of CR_REGS (as opposed to LOADABLE_CR_REGS). */ \
+ 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 48, 49, 50, 51, 52, 58, \
+ 59, 60, 61, 62, 63, 53, 54, 55, 56, 57, 74, 75, 76, 77, 78, 79, \
+ /* coprocessor control registers */ \
+ 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
+ 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, \
+ /* virtual arg pointer */ \
+ 112, SHADOW_REG_ALLOC_ORDER \
+ }
+
+/* We must somehow disable register remapping for interrupt functions. */
+extern char mep_leaf_registers[];
+#define LEAF_REGISTERS mep_leaf_registers
+#define LEAF_REG_REMAP(REG) (REG)
+
+\f
+#define FIRST_GR_REGNO 0
+#define FIRST_CONTROL_REGNO (FIRST_GR_REGNO + 16)
+#define FIRST_CR_REGNO (FIRST_CONTROL_REGNO + 32)
+#define FIRST_CCR_REGNO (FIRST_CR_REGNO + 32)
+
+#define GR_REGNO_P(REGNO) \
+ ((unsigned) ((REGNO) - FIRST_GR_REGNO) < 16)
+
+#define CONTROL_REGNO_P(REGNO) \
+ ((unsigned) ((REGNO) - FIRST_CONTROL_REGNO) < 32)
+
+#define LOADABLE_CR_REGNO_P(REGNO) \
+ ((unsigned) ((REGNO) - FIRST_CR_REGNO) < 16)
+
+#define CR_REGNO_P(REGNO) \
+ ((unsigned) ((REGNO) - FIRST_CR_REGNO) < 32)
+
+#define CCR_REGNO_P(REGNO) \
+ ((unsigned) ((REGNO) - FIRST_CCR_REGNO) < 32)
+
+#define ANY_CONTROL_REGNO_P(REGNO) \
+ (CONTROL_REGNO_P (REGNO) || CCR_REGNO_P (REGNO))
+
+#define HARD_REGNO_NREGS(REGNO, MODE) \
+ ((CR_REGNO_P (REGNO) && TARGET_64BIT_CR_REGS) \
+ ? (GET_MODE_SIZE (MODE) + 8 - 1) / 8 \
+ : (GET_MODE_SIZE (MODE) + 4 - 1) / 4)
+
+#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
+
+#define MODES_TIEABLE_P(MODE1, MODE2) 1
+
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
+ mep_cannot_change_mode_class (FROM, TO, CLASS)
+\f
+enum reg_class
+{
+ NO_REGS,
+ SP_REGS,
+ TP_REGS,
+ GP_REGS,
+ R0_REGS,
+ RPC_REGS,
+ HI_REGS,
+ LO_REGS,
+ HILO_REGS,
+ TPREL_REGS,
+ GENERAL_NOT_R0_REGS,
+ GENERAL_REGS,
+ CONTROL_REGS,
+ CONTROL_OR_GENERAL_REGS,
+ USER0_REGS,
+ USER1_REGS,
+ USER2_REGS,
+ USER3_REGS,
+ LOADABLE_CR_REGS,
+ CR_REGS,
+ CCR_REGS,
+ ALL_REGS,
+ LIM_REG_CLASSES
+};
+
+#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
+
+#define REG_CLASS_NAMES { \
+ "NO_REGS", \
+ "SP_REGS", \
+ "TP_REGS", \
+ "GP_REGS", \
+ "R0_REGS", \
+ "RPC_REGS", \
+ "HI_REGS", \
+ "LO_REGS", \
+ "HILO_REGS", \
+ "TPREL_REGS", \
+ "GENERAL_NOT_R0_REGS", \
+ "GENERAL_REGS", \
+ "CONTROL_REGS", \
+ "CONTROL_OR_GENERAL_REGS", \
+ "USER0_REGS", \
+ "USER1_REGS", \
+ "USER2_REGS", \
+ "USER3_REGS", \
+ "LOADABLE_CR_REGS", \
+ "CR_REGS", \
+ "CCR_REGS", \
+ "ALL_REGS" }
+
+#define REG_CLASS_CONTENTS { \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
+ { 0x00008000, 0x00000000, 0x00000000, 0x00000000 }, /* SP_REGS */ \
+ { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* TP_REGS */ \
+ { 0x00004000, 0x00000000, 0x00000000, 0x00000000 }, /* GP_REGS */ \
+ { 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* R0_REGS */ \
+ { 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* RPC_REGS */ \
+ { 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
+ { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
+ { 0x01800000, 0x00000000, 0x00000000, 0x00000000 }, /* HILO_REGS */ \
+ { 0x000000ff, 0x00000000, 0x00000000, 0x00000000 }, /* TPREL_REGS */ \
+ { 0x0000fffe, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_NOT_R0_REGS */ \
+ { 0x0000ffff, 0x00000000, 0x00000000, 0x00010000 }, /* GENERAL_REGS */ \
+ { 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* CONTROL_REGS */ \
+ { 0xffffffff, 0x0000ffff, 0x00000000, 0x00000000 }, /* CONTROL_OR_GENERAL_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER0_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER1_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER2_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER3_REGS */ \
+ { 0x00000000, 0xffff0000, 0x00000000, 0x00000000 }, /* LOADABLE_CR_REGS */ \
+ { 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* CR_REGS */ \
+ { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* CCR_REGS */ \
+ { 0xffffffff, 0xffffffff, 0xffffffff, 0x0001ffff }, /* ALL_REGS */ \
+ }
+
+#define REGNO_REG_CLASS(REGNO) mep_regno_reg_class (REGNO)
+
+#define IRA_COVER_CLASSES { GENERAL_REGS, CONTROL_REGS, CR_REGS, CCR_REGS, LIM_REG_CLASSES }
+
+#define BASE_REG_CLASS GENERAL_REGS
+#define INDEX_REG_CLASS GENERAL_REGS
+
+#if 0
+#define REG_CLASS_FROM_CONSTRAINT(CHAR, STRING) \
+ mep_reg_class_from_constraint (CHAR, STRING)
+#endif
+
+#define REGNO_OK_FOR_BASE_P(NUM) (GR_REGNO_P (NUM) \
+ || (NUM) == ARG_POINTER_REGNUM \
+ || (NUM) >= FIRST_PSEUDO_REGISTER)
+
+#define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
+
+#define PREFERRED_RELOAD_CLASS(X, CLASS) mep_preferred_reload_class (X, CLASS)
+
+#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
+ mep_secondary_input_reload_class (CLASS, MODE, X)
+#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
+ mep_secondary_output_reload_class (CLASS, MODE, X)
+#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
+ mep_secondary_memory_needed (CLASS1, CLASS2, MODE)
+
+#define CLASS_MAX_NREGS(CLASS, MODE) \
+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+#if 0
+#define CONST_OK_FOR_LETTER_P(VALUE, C) mep_const_ok_for_letter_p (VALUE, C)
+
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
+
+#define CONSTRAINT_LEN(C, STR) \
+ ((C) == 'e' ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
+#define EXTRA_CONSTRAINT(VALUE, C) mep_extra_constraint (VALUE, C)
+#endif
+
+#define WANT_GCC_DECLARATIONS
+#include "mep-intrin.h"
+#undef WANT_GCC_DECLARATIONS
+
+extern int mep_intrinsic_insn[];
+extern unsigned int mep_selected_isa;
+
+/* True if intrinsic X is available. X is a mep_* value declared
+ in mep-intrin.h. */
+#define MEP_INTRINSIC_AVAILABLE_P(X) (mep_intrinsic_insn[X] >= 0)
+
+/* Used to define CGEN_ENABLE_INTRINSIC_P in mep-intrin.h. */
+#define CGEN_CURRENT_ISAS mep_selected_isa
+#define CGEN_CURRENT_GROUP \
+ (mep_vliw_function_p (cfun->decl) ? GROUP_VLIW : GROUP_NORMAL)
+
+\f
+
+#define STACK_GROWS_DOWNWARD 1
+#define FRAME_GROWS_DOWNWARD 1
+#define STARTING_FRAME_OFFSET 0
+#define FIRST_PARM_OFFSET(FUNDECL) 0
+#define INCOMING_FRAME_SP_OFFSET 0
+
+#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) mep_return_addr_rtx (COUNT)
+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, LP_REGNO)
+#define DWARF_FRAME_RETURN_COLUMN LP_REGNO
+
+#define STACK_POINTER_REGNUM 15
+#define FRAME_POINTER_REGNUM 8
+#define ARG_POINTER_REGNUM 112
+#define RETURN_ADDRESS_POINTER_REGNUM 17
+#define STATIC_CHAIN_REGNUM 0
+
+\f
+
+#define FRAME_POINTER_REQUIRED 0
+
+#define ELIMINABLE_REGS \
+{ \
+ {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
+ {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \
+}
+
+#define CAN_ELIMINATE(FROM, TO) \
+ ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
+ ? ! frame_pointer_needed \
+ : 1)
+
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
+ (OFFSET) = mep_elimination_offset (FROM, TO)
+
+#define ACCUMULATE_OUTGOING_ARGS 1
+
+#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
+
+\f
+
+/* The ABI is thus: Arguments are in $1, $2, $3, $4, stack. Arguments
+ larger than 4 bytes are passed indirectly. Return value in 0,
+ unless bigger than 4 bytes, then the caller passes a pointer as the
+ first arg. For varargs, we copy $1..$4 to the stack. */
+
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
+ mep_function_arg (CUM, MODE, TYPE, NAMED)
+
+#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) 1
+
+typedef struct
+{
+ int nregs;
+ int vliw;
+} CUMULATIVE_ARGS;
+
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
+ mep_init_cumulative_args (& (CUM), FNTYPE, LIBNAME, FNDECL)
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
+ mep_arg_advance (& (CUM), MODE, TYPE, NAMED)
+
+#define FUNCTION_ARG_REGNO_P(REGNO) ((REGNO) >= 1 && (REGNO) <= 4)
+
+#define RETURN_VALUE_REGNUM 0
+
+#define FUNCTION_VALUE(VALTYPE, FUNC) mep_function_value (VALTYPE, FUNC)
+#define LIBCALL_VALUE(MODE) mep_libcall_value (MODE)
+
+#define FUNCTION_VALUE_REGNO_P(REGNO) \
+ ((REGNO) == RETURN_VALUE_REGNUM)
+
+#define DEFAULT_PCC_STRUCT_RETURN 0
+
+#define STRUCT_VALUE 0
+
+#define FUNCTION_OK_FOR_SIBCALL(DECL) mep_function_ok_for_sibcall(DECL)
+\f
+/* Prologue and epilogues are all handled via RTL. */
+
+#define EXIT_IGNORE_STACK 1
+
+#define EPILOGUE_USES(REGNO) mep_epilogue_uses (REGNO)
+
+/* Profiling is supported. */
+
+#define FUNCTION_PROFILER(FILE, LABELNO) mep_function_profiler (FILE);
+#undef TARGET_HAS_F_SETLKW
+#define NO_PROFILE_COUNTERS 1
+\f
+/* Trampolines are built at run-time. The cache is invalidated at
+ run-time also. */
+
+#define TRAMPOLINE_SIZE 20
+
+#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
+ mep_init_trampoline (ADDR, FNADDR, STATIC_CHAIN)
+
+\f
+
+#define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
+
+#define MAX_REGS_PER_ADDRESS 1
+
+#ifdef REG_OK_STRICT
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
+ if (mep_legitimate_address ((MODE), (X), 1)) goto LABEL
+#else
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
+ if (mep_legitimate_address ((MODE), (X), 0)) goto LABEL
+#endif
+
+#ifdef REG_OK_STRICT
+#define REG_OK_FOR_BASE_P(X) GR_REGNO_P (REGNO (X))
+#else
+#define REG_OK_FOR_BASE_P(X) (GR_REGNO_P (REGNO (X)) \
+ || REGNO (X) == ARG_POINTER_REGNUM \
+ || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+#endif
+
+#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
+
+#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
+ if (mep_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE), (IND_LEVELS))) \
+ goto WIN
+
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
+
+#define LEGITIMATE_CONSTANT_P(X) 1
+
+#define SELECT_CC_MODE(OP, X, Y) CCmode
+\f
+
+/* Moves between control regs need a scratch. */
+#define REGISTER_MOVE_COST(MODE, FROM, TO) mep_register_move_cost (MODE, FROM, TO)
+
+#define SLOW_BYTE_ACCESS 1
+
+/* Define this macro if it is as good or better to call a constant function
+ address than to call an address kept in a register. */
+#define NO_FUNCTION_CSE
+
+\f
+#define TEXT_SECTION_ASM_OP "\t.text\n\t.core"
+#define DATA_SECTION_ASM_OP "\t.data"
+#define BSS_SECTION_ASM_OP ".bss"
+
+#define TARGET_ASM_FILE_END mep_file_cleanups
+
+#define ASM_APP_ON "#APP\n"
+#define ASM_APP_OFF "#NO_APP\n"
+
+#define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
+ do \
+ { \
+ long l[2]; \
+ \
+ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
+ fprintf (FILE, "\t.long\t0x%lx,0x%lx\n", l[0], l[1]); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_FLOAT(FILE, VALUE) \
+ do \
+ { \
+ long l; \
+ \
+ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
+ fprintf ((FILE), "\t.long\t0x%lx\n", l); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_CHAR(FILE, VALUE) \
+ do \
+ { \
+ fprintf (FILE, "\t.byte\t"); \
+ output_addr_const (FILE, (VALUE)); \
+ fprintf (FILE, "\n"); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_SHORT(FILE, VALUE) \
+ do \
+ { \
+ fprintf (FILE, "\t.hword\t"); \
+ output_addr_const (FILE, (VALUE)); \
+ fprintf (FILE, "\n"); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_INT(FILE, VALUE) \
+ do \
+ { \
+ fprintf (FILE, "\t.word\t"); \
+ output_addr_const (FILE, (VALUE)); \
+ fprintf (FILE, "\n"); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_BYTE(STREAM, VALUE) \
+ fprintf (STREAM, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
+
+/* Most of these are here to support based/tiny/far/io attributes. */
+
+#define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
+ mep_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
+
+#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
+ mep_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
+
+#define ASM_OUTPUT_LABEL(STREAM, NAME) \
+ do \
+ { \
+ assemble_name (STREAM, NAME); \
+ fputs (":\n", STREAM); \
+ } \
+ while (0)
+
+/* Globalizing directive for a label. */
+#define GLOBAL_ASM_OP "\t.globl "
+
+#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
+ asm_fprintf ((STREAM), "%U%s", mep_strip_name_encoding (NAME))
+
+#define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \
+ do \
+ { \
+ (OUTVAR) = (char *) alloca (strlen ((NAME)) + 12); \
+ sprintf ((OUTVAR), "%s.%ld", (NAME), (long)(NUMBER)); \
+ } \
+ while (0)
+\f
+
+#define REGISTER_NAMES \
+{ \
+ /* Core registers. */ \
+ "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
+ "$8", "$9", "$10", "$11", "$12", "$tp", "$gp", "$sp", \
+ /* Control registers. */ \
+ "$pc", "$lp", "$sar", "3", "$rpb", "$rpe", "$rpc", "$hi", \
+ "$lo", "9", "10", "11", "$mb0", "$me0", "$mb1", "$me1", \
+ "$psw", "$id", "$tmp", "$epc", "$exc", "$cfg", "22", "$npc", \
+ "$dbg", "$depc", "$opt", "$rcfg", "$ccfg", "29", "30", "31", \
+ /* Coprocessor registers. */ \
+ "$c0", "$c1", "$c2", "$c3", "$c4", "$c5", "$c6", "$c7", \
+ "$c8", "$c9", "$c10", "$c11", "$c12", "$c13", "$c14", "$c15", \
+ "$c16", "$c17", "$c18", "$c19", "$c20", "$c21", "$c22", "$c23", \
+ "$c24", "$c25", "$c26", "$c27", "$c28", "$c29", "$c30", "$c31", \
+ /* Coprocessor control registers. */ \
+ "$ccr0", "$ccr1", "$ccr2", "$ccr3", "$ccr4", "$ccr5", "$ccr6", \
+ "$ccr7", "$ccr8", "$ccr9", "$ccr10", "$ccr11", "$ccr12", "$ccr13", \
+ "$ccr14", "$ccr15", "$ccr16", "$ccr17", "$ccr18", "$ccr19", "$ccr20", \
+ "$ccr21", "$ccr22", "$ccr23", "$ccr24", "$ccr25", "$ccr26", "$ccr27", \
+ "$ccr28", "$ccr29", "$ccr30", "$ccr31", \
+ /* Virtual arg pointer. */ \
+ "$argp", SHADOW_REGISTER_NAMES \
+}
+
+/* We duplicate some of the above because we twiddle the above
+ according to *how* the registers are used. Likewise, we include
+ the standard names for coprocessor control registers so that
+ coprocessor options can rename them in the default table. Note
+ that these are compared to stripped names (see REGISTER_PREFIX
+ below). */
+#define ADDITIONAL_REGISTER_NAMES \
+{ \
+ { "8", 8 }, { "fp", 8 }, \
+ { "13", 13 }, { "tp", 13 }, \
+ { "14", 14 }, { "gp", 14 }, \
+ { "15", 15 }, { "sp", 15 }, \
+ { "ccr0", FIRST_CCR_REGNO + 0 }, \
+ { "ccr1", FIRST_CCR_REGNO + 1 }, \
+ { "ccr2", FIRST_CCR_REGNO + 2 }, \
+ { "ccr3", FIRST_CCR_REGNO + 3 }, \
+ { "ccr4", FIRST_CCR_REGNO + 4 }, \
+ { "ccr5", FIRST_CCR_REGNO + 5 }, \
+ { "ccr6", FIRST_CCR_REGNO + 6 }, \
+ { "ccr7", FIRST_CCR_REGNO + 7 }, \
+ { "ccr8", FIRST_CCR_REGNO + 8 }, \
+ { "ccr9", FIRST_CCR_REGNO + 9 }, \
+ { "ccr10", FIRST_CCR_REGNO + 10 }, \
+ { "ccr11", FIRST_CCR_REGNO + 11 }, \
+ { "ccr12", FIRST_CCR_REGNO + 12 }, \
+ { "ccr13", FIRST_CCR_REGNO + 13 }, \
+ { "ccr14", FIRST_CCR_REGNO + 14 }, \
+ { "ccr15", FIRST_CCR_REGNO + 15 }, \
+ { "ccr16", FIRST_CCR_REGNO + 16 }, \
+ { "ccr17", FIRST_CCR_REGNO + 17 }, \
+ { "ccr18", FIRST_CCR_REGNO + 18 }, \
+ { "ccr19", FIRST_CCR_REGNO + 19 }, \
+ { "ccr20", FIRST_CCR_REGNO + 20 }, \
+ { "ccr21", FIRST_CCR_REGNO + 21 }, \
+ { "ccr22", FIRST_CCR_REGNO + 22 }, \
+ { "ccr23", FIRST_CCR_REGNO + 23 }, \
+ { "ccr24", FIRST_CCR_REGNO + 24 }, \
+ { "ccr25", FIRST_CCR_REGNO + 25 }, \
+ { "ccr26", FIRST_CCR_REGNO + 26 }, \
+ { "ccr27", FIRST_CCR_REGNO + 27 }, \
+ { "ccr28", FIRST_CCR_REGNO + 28 }, \
+ { "ccr29", FIRST_CCR_REGNO + 29 }, \
+ { "ccr30", FIRST_CCR_REGNO + 30 }, \
+ { "ccr31", FIRST_CCR_REGNO + 31 } \
+}
+
+/* We watch for pipeline hazards with these */
+#define ASM_OUTPUT_OPCODE(STREAM, PTR) mep_asm_output_opcode (STREAM, PTR)
+#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) mep_final_prescan_insn (INSN, OPVEC, NOPERANDS)
+
+#define PRINT_OPERAND(STREAM, X, CODE) mep_print_operand (STREAM, X, CODE)
+
+#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '!' || (CODE) == '<')
+
+#define PRINT_OPERAND_ADDRESS(STREAM, X) mep_print_operand_address (STREAM, X)
+
+#define REGISTER_PREFIX "$"
+#define LOCAL_LABEL_PREFIX "."
+#define USER_LABEL_PREFIX ""
+#define IMMEDIATE_PREFIX ""
+
+\f
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
+ fprintf (STREAM, "\t.word .L%d\n", VALUE)
+
+\f
+
+#undef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+#define DWARF2_DEBUGGING_INFO 1
+#define DWARF2_UNWIND_INFO 1
+
+#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 10 : INVALID_REGNUM)
+
+#define EH_RETURN_STACKADJ_RTX mep_return_stackadj_rtx ()
+#define EH_RETURN_HANDLER_RTX mep_return_handler_rtx ()
+
+#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
+
+\f
+
+#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
+ fprintf ((STREAM), "\t.p2align %d\n", (POWER))
+
+\f
+
+#define CASE_VECTOR_MODE SImode
+
+#define WORD_REGISTER_OPERATIONS
+#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
+
+#define SHORT_IMMEDIATES_SIGN_EXTEND
+
+#define MOVE_MAX 4
+
+#define SHIFT_COUNT_TRUNCATED 1
+
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
+
+#define STORE_FLAG_VALUE 1
+
+#define Pmode SImode
+
+#define FUNCTION_MODE SImode
+
+#define REGISTER_TARGET_PRAGMAS() mep_register_pragmas ()
+
+#define HANDLE_PRAGMA_PACK_PUSH_POP 1
+
+/* If defined, a C expression to determine the base term of address X.
+ This macro is used in only one place: `find_base_term' in alias.c.
+
+ It is always safe for this macro to not be defined. It exists so
+ that alias analysis can understand machine-dependent addresses.
+
+ The typical use of this macro is to handle addresses containing
+ a label_ref or symbol_ref within an UNSPEC. */
+#define FIND_BASE_TERM(X) mep_find_base_term (X)
+
+/* start-sanitize-never */
+
+#define INCLUDE_MEP_EEMBC
+#define NO_GCSE_BACK_EDGE_INSERTIONS
+/* end-sanitize-never */
--- /dev/null
+;; Toshiba Media Processor Machine description template
+;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009 Free
+;; Software Foundation, Inc.
+;; Contributed by Red Hat Inc
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>. */
+
+\f
+
+;; Constraints:
+;;
+;; a $sp
+;; b $tp
+;; c control regs
+;; h $hi ($23)
+;; l $lo ($24)
+;; d $hi/$lo pair (DImode)
+;; j $rpc ($22)
+;; r $0..$15
+;; t $0..$7
+;; v $gp
+;; x $c0..$c31
+;; ex coprocessor registers that can be moved to other coprocessor registers
+;; er coprocessor registers that can be moved to and from core registers
+;; em coprocessor registers that can be moves to and from memory
+;; y $ccr0..$ccr31
+;; z $0
+;;
+;; I sign imm16 mov/add
+;; J zero imm16 mov/add
+;; K zero imm24 mov
+;; L sign imm6 add
+;; M zero imm5 slt,shifts
+;; N zero imm4 bCC
+;; O high imm16 mov
+;;
+;; R near symbol
+;; S sign imm8 mov
+;; T tp or gp relative symbol
+;; U non-absolute memory
+;; W %hi(sym)
+;; Y (Rn)
+;; Z Control Bus Symbol
+;;
+;; Modifiers:
+;;
+;; b print unique bit in mask
+;; B print bits required for value (for clip)
+;; h print decimal >> 16.
+;; I print decimal, with hex comment if more than 8 bits
+;; J print unsigned hex
+;; L print set, clr or not (for bitops)
+;; P print memory as a post-inc with no increment
+;; U print bits required for value (for clipu)
+;; x print unsigned decimal or hex, depending on where set bits are
+
+(define_constants [
+ (REGSAVE_CONTROL_TEMP 11)
+ (FP_REGNO 8)
+ (TP_REGNO 13)
+ (GP_REGNO 14)
+ (SP_REGNO 15)
+ (PSW_REGNO 16)
+ (LP_REGNO 17)
+ (SAR_REGNO 18)
+ (RPB_REGNO 20)
+ (RPE_REGNO 21)
+ (RPC_REGNO 22)
+ (HI_REGNO 23)
+ (LO_REGNO 24)
+ (CBCR_REGNO 81)
+ ])
+
+(define_constants [
+ (UNS_BLOCKAGE 0)
+ (UNS_TPREL 2)
+ (UNS_GPREL 3)
+ (UNS_REPEAT_BEG 4)
+ (UNS_REPEAT_END 5)
+ (UNS_EH_EPILOGUE 6)
+ (UNS_EREPEAT_BEG 7)
+ (UNS_EREPEAT_END 8)
+ (UNS_BB_TRACE_RET 9)
+ (UNS_DISABLE_INT 10)
+ (UNS_ENABLE_INT 11)
+ (UNS_RETI 12)
+ ])
+\f
+;; This attribute determines the VLIW packing mechanism. The IVC2
+;; coprocessor has two pipelines (P0 and P1), and a MeP+IVC2 can issue
+;; up to three insns at a time. Most IVC2 insns can run on either
+;; pipeline, however, scheduling some insns on P0 precludes packing a
+;; core insn with it, and only 16-bit core insns can pack with any P0
+;; insn.
+(define_attr "vliw" "basic,ivc2"
+ (const (symbol_ref "TARGET_IVC2")))
+
+;; This attribute describes the kind of memory operand present in the
+;; instruction. This is used to compute the length of the insn based
+;; on the addressing mode used.
+(define_attr "memop" "none,core0,core1,cop0,cop1"
+ (const_string "none"))
+
+(define_attr "intrinsic" "none,cmov,cmov1,cmov2,cmovc1,cmovc2,cmovh1,cmovh2"
+ (const_string "none"))
+
+;; This attribute describes how the instruction may be bundled in a
+;; VLIW instruction. Type MULTI is assumed to use both slots.
+(define_attr "slot" "core,cop,multi"
+ (cond [(eq_attr "intrinsic" "!none")
+ (const_string "cop")]
+ (const_string "core")))
+
+;; This attribute describes the latency of the opcode (ready delay).
+;; The 0 is used to indicate "unspecified". An instruction that
+;; completes immediately with no potential stalls would have a value
+;; of 1, a one cycle stall would be 2, etc.
+(define_attr "latency" ""
+ (const_int 0))
+
+(define_attr "shiftop" "none,operand2"
+ (const_string "none"))
+
+;; This attribute describes the size of the instruction in bytes.
+;; This *must* be exact unless the pattern is SLOT_MULTI, as this
+;; is used by the VLIW bundling code.
+(define_attr "length" ""
+ (cond [(eq_attr "memop" "core0")
+ (symbol_ref "mep_core_address_length (insn, 0)")
+ (eq_attr "memop" "core1")
+ (symbol_ref "mep_core_address_length (insn, 1)")
+ (eq_attr "memop" "cop0")
+ (symbol_ref "mep_cop_address_length (insn, 0)")
+ (eq_attr "memop" "cop1")
+ (symbol_ref "mep_cop_address_length (insn, 1)")
+ ]
+ ; Catch patterns that don't define the length properly.
+ (symbol_ref "(abort (), 0)")))
+
+;; This attribute describes a pipeline hazard seen in the insn.
+(define_attr "stall" "none,int2,ssarb,load,store,ldc,stc,ldcb,stcb,ssrab,fsft,ret,advck,mul,mulr,div"
+ (cond [(and (eq_attr "shiftop" "operand2")
+ (not (match_operand:SI 2 "mep_single_shift_operand" "")))
+ (const_string "int2")]
+ (const_string "none")))
+
+(define_attr "may_trap" "no,yes"
+ (const_string "no"))
+
+;; Describe a user's asm statement.
+(define_asm_attributes
+ [(set_attr "length" "4")
+ (set_attr "slot" "multi")])
+
+;; Each IVC2 instruction uses one of these two pipelines. P0S insns
+;; use P0; C3 insns use P1.
+(define_automaton "mep_ivc2")
+(define_cpu_unit "ivc2_core,ivc2_p0,ivc2_p1" "mep_ivc2")
+
+;; Each core or IVC2 instruction is bundled into one of these slots.
+;; Supported bundlings:
+;;
+;; Core mode:
+;;
+;; C1 [-----core-----]
+;; C2 [-------------core-------------]
+;; C3 [--------------c3--------------]
+;;
+;; VLIW mode:
+;;
+;; V1 [-----core-----][--------p0s-------][------------p1------------]
+;; V2 [-------------core-------------]xxxx[------------p1------------]
+;; V3 1111[--p0--]0111[--------p0--------][------------p1------------]
+
+(define_attr "slots" "core,c3,p0,p0_p0s,p0_p1,p0s,p0s_p1,p1" (const_string "core"))
+
+(define_cpu_unit "ivc2_slot_c16,ivc2_slot_c32,ivc2_slot_c3,ivc2_slot_p0s,ivc2_slot_p0,ivc2_slot_p1" "mep_ivc2")
+
+(define_insn_reservation "ivc2_insn_core16" 1
+ (and (eq_attr "vliw" "ivc2")
+ (and (eq (symbol_ref "get_attr_length(insn)") (const_int 2))
+ (and (eq_attr "intrinsic" "none")
+ (eq_attr "slot" "!cop"))))
+ "ivc2_core+ivc2_slot_c16")
+
+(define_insn_reservation "ivc2_insn_core32" 1
+ (and (eq_attr "vliw" "ivc2")
+ (and (eq (symbol_ref "get_attr_length(insn)") (const_int 4))
+ (and (eq_attr "intrinsic" "none")
+ (eq_attr "slot" "!cop"))))
+ "ivc2_core+ivc2_slot_c32")
+
+;; These shouldn't happen when in VLIW mode.
+(define_insn_reservation "ivc2_insn_c3" 1
+ (and (eq_attr "vliw" "ivc2")
+ (eq_attr "slots" "c3"))
+ "ivc2_p1+ivc2_slot_c3")
+
+(define_insn_reservation "ivc2_insn_p0" 1
+ (and (eq_attr "vliw" "ivc2")
+ (eq_attr "slots" "p0"))
+ "ivc2_p0+ivc2_slot_p0")
+
+(define_insn_reservation "ivc2_insn_p0_p0s" 1
+ (and (eq_attr "vliw" "ivc2")
+ (eq_attr "slots" "p0_p0s"))
+ "ivc2_p0+ivc2_slot_p0|ivc2_p0+ivc2_slot_p0s")
+
+(define_insn_reservation "ivc2_insn_p0_p1" 1
+ (and (eq_attr "vliw" "ivc2")
+ (eq_attr "slots" "p0_p1"))
+ "ivc2_p0+ivc2_slot_p0|ivc2_p1+ivc2_slot_p1")
+
+(define_insn_reservation "ivc2_insn_p0s" 1
+ (and (eq_attr "vliw" "ivc2")
+ (eq_attr "slots" "p0s"))
+ "ivc2_p0+ivc2_slot_p0s")
+
+(define_insn_reservation "ivc2_insn_p0s_p1" 1
+ (and (eq_attr "vliw" "ivc2")
+ (eq_attr "slots" "p0s_p1"))
+ "ivc2_p0+ivc2_slot_p0s|ivc2_p1+ivc2_slot_p1")
+
+(define_insn_reservation "ivc2_insn_p1" 1
+ (and (eq_attr "vliw" "ivc2")
+ (eq_attr "slots" "p1"))
+ "ivc2_p1+ivc2_slot_p1")
+
+;; these run in C3 also, but when we're doing VLIW scheduling, they
+;; only run in P0.
+(define_insn_reservation "ivc2_insn_cmov" 1
+ (and (eq_attr "vliw" "ivc2")
+ (eq_attr "intrinsic" "!none"))
+ "ivc2_p0+ivc2_slot_p0")
+
+
+(exclusion_set "ivc2_slot_c32"
+ "ivc2_slot_p0,ivc2_slot_p0s")
+(exclusion_set "ivc2_slot_p0"
+ "ivc2_slot_p0s")
+(exclusion_set "ivc2_slot_c16"
+ "ivc2_slot_p0")
+(exclusion_set "ivc2_slot_c16"
+ "ivc2_slot_c32")
+
+;; Non-IVC2 scheduling.
+(define_automaton "mep")
+(define_cpu_unit "core,cop" "mep")
+
+;; Latencies are the time between one insn entering the second pipeline
+;; stage (E2, LD, A2 or V2) and the next instruction entering the same
+;; stage. When an instruction assigns to general registers, the default
+;; latencies are for when the next instruction receives the register
+;; through bypass 1.
+
+;; Arithmetic instructions that execute in a single stage.
+(define_insn_reservation "h1_int1" 2
+ (and (eq_attr "slot" "!cop")
+ (eq_attr "stall" "none"))
+ "core")
+(define_bypass 1 "h1_int1" "h1_int1,h1_ssarb")
+(define_bypass 1 "h1_int1" "h1_store" "mep_store_data_bypass_p")
+
+;; $sar can be read by an immediately following fsft or ldc.
+(define_insn_reservation "h1_ssarb" 1
+ (eq_attr "stall" "ssarb")
+ "core")
+
+;; Arithmetic instructions that execute in two stages.
+(define_insn_reservation "h1_int2" 2
+ (eq_attr "stall" "int2,fsft")
+ "core")
+(define_bypass 1 "h1_int2" "h1_int1,h1_ssarb")
+(define_bypass 1 "h1_int2" "h1_store" "mep_store_data_bypass_p")
+
+(define_insn_reservation "h1_load" 4
+ (eq_attr "stall" "load")
+ "core")
+(define_bypass 3 "h1_load" "h1_int1,h1_ssarb")
+(define_bypass 3 "h1_load" "h1_store" "mep_store_data_bypass_p")
+
+(define_insn_reservation "h1_store" 1
+ (eq_attr "stall" "store")
+ "core")
+
+(define_insn_reservation "h1_ipipe_ldc" 2
+ (and (eq_attr "stall" "ldc")
+ (ne (symbol_ref "mep_ipipe_ldc_p(insn)") (const_int 0)))
+ "core")
+(define_bypass 1 "h1_ipipe_ldc" "h1_int1,h1_ssarb")
+(define_bypass 1 "h1_ipipe_ldc" "h1_store" "mep_store_data_bypass_p")
+
+(define_insn_reservation "h1_apipe_ldc" 2
+ (and (eq_attr "stall" "ldc")
+ (eq (symbol_ref "mep_ipipe_ldc_p(insn)") (const_int 0)))
+ "core")
+
+;; 2 is correct for stc->ret and stc->fsft. The most important remaining
+;; case is stc->madd, which induces no stall.
+(define_insn_reservation "h1_stc" 2
+ (eq_attr "stall" "stc")
+ "core")
+(define_bypass 1 "h1_stc" "h1_mul")
+
+;; ??? Parameterised latency.
+(define_insn_reservation "h1_ldcb" 5
+ (eq_attr "stall" "ldcb")
+ "core")
+
+(define_insn_reservation "h1_stcb" 1
+ (eq_attr "stall" "stcb")
+ "core")
+
+(define_insn_reservation "h1_advck" 6
+ (eq_attr "stall" "advck")
+ "core")
+
+(define_insn_reservation "h1_mul" 5
+ (eq_attr "stall" "mul,mulr")
+ "core")
+(define_bypass 4 "h1_mul" "h1_int1,h1_ssarb")
+(define_bypass 4 "h1_mul" "h1_store" "mep_store_data_bypass_p")
+(define_bypass 1 "h1_mul" "h1_mul" "mep_mul_hilo_bypass_p")
+
+(define_insn_reservation "h1_div" 36
+ (eq_attr "stall" "div")
+ "core")
+
+(define_insn_reservation "h1_cop" 1
+ (eq_attr "slot" "cop")
+ "cop")
+\f
+(include "predicates.md")
+(include "constraints.md")
+(include "intrinsics.md")
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: Moves
+;; ::
+;; ::::::::::::::::::::
+
+(define_expand "movqi"
+ [(set (match_operand:QI 0 "general_operand" "")
+ (match_operand:QI 1 "general_operand" ""))]
+ ""
+ "
+{
+ if (mep_expand_mov (operands, QImode))
+ DONE;
+}")
+
+;; The Idea here is to prefer the 16-bit tp-relative load, but to fall back
+;; to the general 32-bit load rather than do silly things with spill regs.
+(define_insn "*movqi_tprel_load"
+ [(set (match_operand:QI 0 "mep_tprel_operand" "=t,*r")
+ (mem:QI (plus:SI (match_operand:SI 1 "mep_tp_operand" "b,*r")
+ (const:SI (unspec:SI [(match_operand:SI 2
+ "symbolic_operand" "s,s")]
+ UNS_TPREL)))))]
+ ""
+ "lb\\t%0, %%tpoff(%2)(%1)"
+ [(set_attr "length" "2,4")
+ (set_attr "stall" "load")])
+
+(define_insn "*movqi_tprel_store"
+ [(set (mem:QI (plus:SI (match_operand:SI 0 "mep_tp_operand" "b,*r")
+ (const:SI (unspec:SI [(match_operand:SI 1
+ "symbolic_operand" "s,s")]
+ UNS_TPREL))))
+ (match_operand:QI 2 "mep_tprel_operand" "t,*r"))]
+ ""
+ "sb\\t%2, %%tpoff(%1)(%0)"
+ [(set_attr "length" "2,4")
+ (set_attr "stall" "store")])
+
+(define_insn "*movqi_internal"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r, r,m,r,c,r,y,r,er,ex,em,Y")
+ (match_operand:QI 1 "general_operand" " r,n,rm,r,c,r,y,r,er,r,ex,Y,em"))]
+ "mep_mov_ok (operands, QImode)"
+ "@
+ mov\\t%0, %1
+ mov\\t%0, %1
+ lb\\t%0, %1
+ sb\\t%1, %0
+ ldc\\t%0, %1
+ stc\\t%1, %0
+ cmovc\\t%0, %1
+ cmovc\\t%0, %1
+ cmov\\t%0, %1
+ cmov\\t%0, %1
+ %<\\t%0, %M1
+ lbcpa\\t%0, %P1
+ sbcpa\\t%1, %P0"
+ [(set_attr "length" "2,2,*,*,2,2,4,4,4,4,*,4,4")
+ (set_attr "intrinsic" "*,*,*,*,*,*,cmovc2,cmovc1,cmov2,cmov1,cmov,*,*")
+ (set_attr "stall" "*,*,load,store,ldc,stc,*,*,*,*,*,load,store")
+ (set_attr "memop" "*,*,core1,core0,*,*,*,*,*,*,*,*,*")])
+
+(define_expand "movhi"
+ [(set (match_operand:HI 0 "general_operand" "")
+ (match_operand:HI 1 "general_operand" ""))]
+ ""
+ "
+{
+ if (mep_expand_mov (operands, HImode))
+ DONE;
+}")
+
+(define_insn "*movhi_tprel_load"
+ [(set (match_operand:HI 0 "mep_tprel_operand" "=t,*r")
+ (mem:HI (plus:SI (match_operand:SI 1 "mep_tp_operand" "b,*r")
+ (const:SI (unspec:SI [(match_operand:SI 2
+ "symbolic_operand" "s,s")]
+ UNS_TPREL)))))]
+ ""
+ "lh\\t%0, %%tpoff(%2)(%1)"
+ [(set_attr "length" "2,4")
+ (set_attr "stall" "load")])
+
+(define_insn "*movhi_tprel_store"
+ [(set (mem:HI (plus:SI (match_operand:SI 0 "mep_tp_operand" "b,*r")
+ (const:SI (unspec:SI [(match_operand:SI 1
+ "symbolic_operand" "s,s")]
+ UNS_TPREL))))
+ (match_operand:HI 2 "mep_tprel_operand" "t,*r"))]
+ ""
+ "sh\\t%2, %%tpoff(%1)(%0)"
+ [(set_attr "length" "2,4")
+ (set_attr "stall" "store")])
+
+(define_insn "*movhi_internal"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,m,r,c,r,y,r,er,ex,em,Y")
+ (match_operand:HI 1 "general_operand" " r,S,n,m,r,c,r,y,r,er,r,ex,Y,em"))]
+ "mep_mov_ok (operands, HImode)"
+ "@
+ mov\\t%0, %1
+ mov\\t%0, %I1
+ mov\\t%0, %I1
+ lh\\t%0, %1
+ sh\\t%1, %0
+ ldc\\t%0, %1
+ stc\\t%1, %0
+ cmovc\\t%0, %1
+ cmovc\\t%0, %1
+ cmov\\t%0, %1
+ cmov\\t%0, %1
+ %<\\t%0, %M1
+ lhcpa\\t%0, %P1
+ shcpa\\t%1, %P0"
+ [(set_attr "length" "2,2,4,*,*,2,2,4,4,4,4,*,4,4")
+ (set_attr "intrinsic" "*,*,*,*,*,*,*,cmovc2,cmovc1,cmov2,cmov1,cmov,*,*")
+ (set_attr "stall" "*,*,*,load,store,ldc,stc,*,*,*,*,*,load,store")
+ (set_attr "memop" "*,*,*,core1,core0,*,*,*,*,*,*,*,*,*")])
+
+(define_expand "movsi"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "")
+ (match_operand:SI 1 "general_operand" ""))]
+ ""
+ "
+{
+ if (mep_expand_mov (operands, SImode))
+ DONE;
+}")
+
+(define_insn "*movsi_tprel_load"
+ [(set (match_operand:SI 0 "mep_tprel_operand" "=t,*r")
+ (mem:SI (plus:SI (match_operand:SI 1 "mep_tp_operand" "b,*r")
+ (const:SI (unspec:SI [(match_operand:SI 2
+ "symbolic_operand" "s,s")]
+ UNS_TPREL)))))]
+ ""
+ "lw\\t%0, %%tpoff(%2)(%1)"
+ [(set_attr "length" "2,4")
+ (set_attr "stall" "load")])
+
+(define_insn "*movsi_tprel_store"
+ [(set (mem:SI (plus:SI (match_operand:SI 0 "mep_tp_operand" "b,*r")
+ (const:SI (unspec:SI [(match_operand:SI 1
+ "symbolic_operand" "s,s")]
+ UNS_TPREL))))
+ (match_operand:SI 2 "mep_tprel_operand" "t,*r"))]
+ ""
+ "sw\\t%2, %%tpoff(%1)(%0)"
+ [(set_attr "length" "2,4")
+ (set_attr "stall" "store")])
+
+(define_insn "movsi_topsym_s"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (high:SI (match_operand:SI 1 "symbolic_operand" "s")))]
+ ""
+ "movh\\t%0, %%hi(%1)"
+ [(set_attr "length" "4")])
+
+(define_insn "movsi_botsym_s"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "symbolic_operand" "s")))]
+ ""
+ "add3\\t%0, %1, %%lo(%2)"
+ [(set_attr "length" "4")])
+
+
+
+(define_insn "cmovh_getsub"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (subreg:SI (match_operand:DI 1 "register_operand" "er") 4))]
+ "0 && TARGET_64BIT_CR_REGS"
+ "cmovh\\t%0, %1"
+ [(set_attr "intrinsic" "cmovh2")
+ (set_attr "length" "4")])
+
+(define_insn "*movsi_internal"
+ [(set (match_operand:SI 0 "mep_movdest_operand"
+ "=r,r,r,r,r, t,t,r,r,r,Z,m,r,c,r,y,r, er,ex,em,U ")
+ (match_operand:SI 1 "general_operand"
+ " r,S,I,J,OW,K,s,i,Z,m,r,r,c,r,y,r,er,r, ex,U, em"))]
+ "mep_mov_ok (operands, SImode)"
+ "@
+ mov\\t%0, %1
+ mov\\t%0, %I1
+ mov\\t%0, %I1
+ movu\\t%0, %J1
+ movh\\t%0, %h1
+ movu\\t%0, %x1
+ movu\\t%0, %1
+ #
+ ldcb\\t%0, %1
+ lw\\t%0, %1
+ stcb\\t%1, %0
+ sw\\t%1, %0
+ ldc\\t%0, %1
+ stc\\t%1, %0
+ cmovc\\t%0, %1
+ cmovc\\t%0, %1
+ cmov\\t%0, %1
+ cmov\\t%0, %1
+ %<\\t%0, %M1
+ lwcp\\t%0, %1
+ swcp\\t%1, %0"
+ [(set_attr "length" "2,2,4,4,4,4,4,*,4,*,4,*,2,2,4,4,4,4,4,*,*")
+ (set_attr "intrinsic" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,cmovc2,cmovc1,cmov2,cmov1,cmov,*,*")
+ (set_attr "stall" "*,*,*,*,*,*,*,*,ldcb,load,stcb,store,ldc,stc,*,*,*,*,*,load,store")
+ (set_attr "memop" "*,*,*,*,*,*,*,*,*,core1,*,core0,*,*,*,*,*,*,*,cop1,cop0")
+ (set_attr "slot" "*,*,*,*,*,*,*,multi,*,*,*,*,*,*,*,*,*,*,*,*,*")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (match_operand:SI 1 "const_int_operand" ""))]
+ "mep_split_mov (operands, 0)"
+ [(set (match_dup 0) (match_dup 2))
+ (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 3)))]
+ "
+{
+ HOST_WIDE_INT value;
+ int lo, hi;
+
+ value = INTVAL (operands[1]);
+
+ lo = value & 0xffff;
+ hi = trunc_int_for_mode (value & 0xffff0000, SImode);
+
+ operands[2] = GEN_INT (hi);
+ operands[3] = GEN_INT (lo);
+}")
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (match_operand:SI 1 "immediate_operand" ""))]
+ "mep_split_mov (operands, 1)"
+ [(set (match_dup 0) (high:SI (match_dup 1)))
+ (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
+ "")
+
+;; ??? What purpose do these two serve that high+lo_sum do not?
+(define_insn "movsi_topsym_u"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (and:SI (match_operand:SI 1 "symbolic_operand" "s")
+ (const_int -65536)))]
+ ""
+ "movh\\t%0, %%uhi(%1)"
+ [(set_attr "length" "4")])
+
+(define_insn "movsi_botsym_u"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI (match_operand:SI 1 "register_operand" "0")
+ (and:SI (match_operand:SI 2 "symbolic_operand" "s")
+ (const_int 65535))))]
+ ""
+ "or3\\t%0, %1, %%lo(%2)"
+ [(set_attr "length" "4")])
+
+(define_expand "movdi"
+ [(set (match_operand:DI 0 "" "")
+ (match_operand:DI 1 "" ""))]
+ ""
+ "
+{
+ if (mep_expand_mov (operands, DImode))
+ DONE;
+}")
+
+(define_insn "*movdi_internal_32"
+ [(set (match_operand:DI 0 "mep_movdest_operand" "= r,m,r,c,r,er,ex,em,U")
+ (match_operand:DI 1 "general_operand" "rim,r,c,r,er,r,ex,U,em"))]
+ "TARGET_32BIT_CR_REGS && mep_mov_ok (operands, DImode)"
+ "#"
+ [(set_attr "slot" "multi")])
+
+(define_insn "*movdi_internal_64"
+ [(set (match_operand:DI 0 "mep_movdest_operand" "=r,r,m,r,c,r,er,ex,em,U")
+ (match_operand:DI 1 "general_operand" "r,im,r,c,r,er,r,ex,U,em"))]
+ "TARGET_64BIT_CR_REGS && mep_mov_ok (operands, DImode)"
+ "@
+ #
+ #
+ #
+ #
+ #
+ #
+ #
+ %<\\t%0, %M1
+ lmcp\\t%0, %1
+ smcp\\t%1, %0"
+ [(set_attr "slot" "multi,multi,multi,multi,multi,multi,multi,*,*,*")
+ (set_attr "intrinsic" "*,*,*,*,*,*,*,cmov,*,*")
+ (set_attr "memop" "*,*,*,*,*,*,*,cop0,cop1,cop0")
+ (set_attr "stall" "*,*,*,*,*,*,*,*,load,store")])
+
+(define_insn "*movdi_cop_postinc"
+ [(parallel [(set (match_operand:DI 0 "register_operand" "=em")
+ (mem:DI (reg:SI SP_REGNO)))
+ (set (reg:SI SP_REGNO)
+ (plus:SI (reg:SI SP_REGNO)
+ (const_int 8)))
+ ]
+ )]
+ "TARGET_COP"
+ "lmcpi\\t%0,($sp+)"
+ [(set_attr "length" "2")])
+
+(define_insn "*movdi_cop_postinc"
+ [(parallel [(set (match_operand:DI 0 "register_operand" "=em")
+ (mem:DI (match_operand:SI 2 "register_operand" "r")))
+ (set (match_operand:SI 1 "register_operand" "=0")
+ (plus:SI (match_operand:SI 3 "register_operand" "0")
+ (const_int 8)))
+ ]
+ )]
+ "TARGET_COP"
+ "lmcpi\\t%0,(%1+)"
+ [(set_attr "length" "2")])
+
+(define_insn "*cmovh_set"
+ [(set (zero_extract:SI (match_operand:DI 0 "register_operand" "+er")
+ (const_int 32)
+ (const_int 32))
+ (match_operand:SI 1 "register_operand" "r"))]
+ "TARGET_64BIT_CR_REGS"
+ "cmovh\\t%0, %1"
+ [(set_attr "intrinsic" "cmovh1")
+ (set_attr "length" "4")])
+
+(define_insn "cmovh_get"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extract:SI (match_operand:DI 1 "register_operand" "er")
+ (const_int 32)
+ (const_int 32)))]
+ "TARGET_64BIT_CR_REGS"
+ "cmovh\\t%0, %1"
+ [(set_attr "intrinsic" "cmovh2")
+ (set_attr "length" "4")])
+
+(define_split
+ [(set (match_operand:DI 0 "mep_movdest_operand" "")
+ (match_operand:DI 1 "general_operand" ""))]
+ "reload_completed && mep_multi_slot (insn)"
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 4) (match_dup 5))]
+ "mep_split_wide_move (operands, DImode);")
+
+;; Floating Point Moves
+
+(define_expand "movsf"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "")
+ (match_operand:SF 1 "general_operand" ""))]
+ ""
+ "
+{
+ if (mep_expand_mov (operands, SFmode))
+ DONE;
+}")
+
+(define_insn "*movsf_tprel_load"
+ [(set (match_operand:SF 0 "mep_tprel_operand" "=t,*r")
+ (mem:SF (plus:SI (match_operand:SI 1 "mep_tp_operand" "b,*r")
+ (const:SI (unspec:SI [(match_operand:SI 2
+ "symbolic_operand" "s,s")]
+ UNS_TPREL)))))]
+ ""
+ "lw\\t%0, %%tpoff(%2)(%1)"
+ [(set_attr "length" "2,4")
+ (set_attr "stall" "load")])
+
+(define_insn "*movsf_tprel_store"
+ [(set (mem:SF (plus:SI (match_operand:SI 0 "mep_tp_operand" "b,*r")
+ (const:SI (unspec:SI [(match_operand:SI 1
+ "symbolic_operand" "s,s")]
+ UNS_TPREL))))
+ (match_operand:SF 2 "mep_tprel_operand" "t,*r"))]
+ ""
+ "sw\\t%2, %%tpoff(%1)(%0)"
+ [(set_attr "length" "2,4")
+ (set_attr "stall" "store")])
+
+(define_insn "*movsf_internal"
+ [(set (match_operand:SF 0 "mep_movdest_operand"
+ "=r,r,r,r,Z,m,r,c,r,y,r,er,ex,em,U")
+ (match_operand:SF 1 "general_operand"
+ " r,F,Z,m,r,r,c,r,y,r,er,r,ex,U,em"))]
+ "mep_mov_ok (operands, SFmode)"
+ "@
+ mov\\t%0, %1
+ #
+ ldcb\\t%0, %1
+ lw\\t%0, %1
+ stcb\\t%1, %0
+ sw\\t%1, %0
+ ldc\\t%0, %1
+ stc\\t%1, %0
+ cmovc\\t%0, %1
+ cmovc\\t%0, %1
+ cmov\\t%0, %1
+ cmov\\t%0, %1
+ %<\\t%0, %M1
+ lwcp\\t%0, %1
+ swcp\\t%1, %0"
+ [(set_attr "length" "2,*,2,*,2,*,2,2,*,*,4,4,*,*,*")
+ (set_attr "intrinsic" "*,*,*,*,*,*,*,*,cmovc2,cmovc1,cmov2,cmov1,cmov,*,*")
+ (set_attr "stall" "*,*,ldcb,load,stcb,store,ldc,stc,*,*,*,*,*,load,store")
+ (set_attr "memop" "*,*,*,core1,*,core0,*,*,*,*,*,*,*,cop1,cop0")])
+
+(define_split
+ [(set (match_operand:SF 0 "register_operand" "")
+ (match_operand:SF 1 "const_double_operand" ""))]
+ "reload_completed"
+ [(const_int 0)]
+ "
+{
+ REAL_VALUE_TYPE rv;
+ HOST_WIDE_INT value;
+ HOST_WIDE_INT lo, hi;
+ rtx out;
+
+ REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
+ REAL_VALUE_TO_TARGET_SINGLE (rv, value);
+
+ lo = value & 0xffff;
+ hi = trunc_int_for_mode (value & 0xffff0000, SImode);
+
+ out = gen_rtx_REG (SImode, REGNO (operands[0]));
+ emit_move_insn (out, GEN_INT (hi));
+ if (lo != 0)
+ emit_insn (gen_iorsi3 (out, out, GEN_INT (lo)));
+ DONE;
+}")
+
+(define_expand "movdf"
+ [(set (match_operand:DF 0 "" "")
+ (match_operand:DF 1 "" ""))]
+ ""
+ "
+{
+ if (mep_expand_mov (operands, DFmode))
+ DONE;
+}")
+
+(define_insn "*movdf_internal_32"
+ [(set (match_operand:DF 0 "mep_movdest_operand" "= r,m,r,c,r,er,ex,em,U")
+ (match_operand:DF 1 "general_operand" "rFm,r,c,r,er,r,ex,U,em"))]
+ "TARGET_32BIT_CR_REGS && mep_mov_ok (operands, DFmode)"
+ "#"
+ [(set_attr "slot" "multi")])
+
+(define_insn "*movdf_internal_64"
+ [(set (match_operand:DF 0 "mep_movdest_operand" "= r,m,r,c,r,er,ex,em,U")
+ (match_operand:DF 1 "general_operand" "rFm,r,c,r,er,r,ex,U,em"))]
+ "TARGET_64BIT_CR_REGS && mep_mov_ok (operands, DFmode)"
+ "@
+ #
+ #
+ #
+ #
+ #
+ #
+ %<\\t%0, %M1
+ lmcp\\t%0, %1
+ smcp\\t%1, %0"
+ [(set_attr "slot" "multi,multi,multi,multi,multi,multi,*,*,*")
+ (set_attr "intrinsic" "*,*,*,*,*,*,cmov,*,*")
+ (set_attr "memop" "*,*,*,*,*,*,*,cop1,cop0")
+ (set_attr "stall" "*,*,*,*,*,*,*,load,store")])
+
+(define_split
+ [(set (match_operand:DF 0 "mep_movdest_operand" "")
+ (match_operand:DF 1 "general_operand" ""))]
+ "reload_completed && mep_multi_slot (insn)"
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 4) (match_dup 5))]
+ "mep_split_wide_move (operands, DFmode);")
+
+\f
+(define_insn "*lbcpa"
+ [(set (match_operand:SI 0 "register_operand" "=em")
+ (sign_extend:SI (mem:QI (match_operand:SI 2 "register_operand" "1"))))
+ (set (match_operand:SI 1 "register_operand" "=r")
+ (plus:SI (match_dup 2)
+ (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")))]
+ "TARGET_COP && reload_completed"
+ "lbcpa\t%0, (%1+), %3"
+ [(set_attr "length" "4")
+ (set_attr "stall" "load")])
+
+(define_insn "*sbcpa"
+ [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
+ (match_operand:QI 2 "register_operand" "em"))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (match_dup 1)
+ (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")))]
+ "TARGET_COP && reload_completed"
+ "sbcpa\t%2, (%0+), %3"
+ [(set_attr "length" "4")
+ (set_attr "stall" "store")])
+
+(define_insn "*lhcpa"
+ [(set (match_operand:SI 0 "register_operand" "=em")
+ (sign_extend:SI (mem:HI (match_operand:SI 2 "register_operand" "1"))))
+ (set (match_operand:SI 1 "register_operand" "=r")
+ (plus:SI (match_dup 2)
+ (match_operand:SI 3 "cgen_h_sint_7a2_immediate" "")))]
+ "TARGET_COP && reload_completed"
+ "lhcpa\t%0, (%1+), %3"
+ [(set_attr "length" "4")
+ (set_attr "stall" "load")])
+
+(define_insn "*shcpa"
+ [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
+ (match_operand:HI 2 "register_operand" "em"))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (match_dup 1)
+ (match_operand:SI 3 "cgen_h_sint_7a2_immediate" "")))]
+ "TARGET_COP && reload_completed"
+ "shcpa\t%2, (%0+), %3"
+ [(set_attr "length" "4")
+ (set_attr "stall" "store")])
+
+(define_insn "*lwcpi"
+ [(set (match_operand:SI 0 "register_operand" "=em")
+ (mem:SI (match_operand:SI 2 "register_operand" "1")))
+ (set (match_operand:SI 1 "register_operand" "=r")
+ (plus:SI (match_dup 2)
+ (const_int 4)))]
+ "TARGET_COP && reload_completed"
+ "lwcpi\t%0, (%1+)"
+ [(set_attr "length" "2")
+ (set_attr "stall" "load")])
+
+(define_insn "*lwcpa"
+ [(set (match_operand:SI 0 "register_operand" "=em")
+ (mem:SI (match_operand:SI 2 "register_operand" "1")))
+ (set (match_operand:SI 1 "register_operand" "=r")
+ (plus:SI (match_dup 2)
+ (match_operand:SI 3 "cgen_h_sint_6a4_immediate" "")))]
+ "TARGET_COP && reload_completed"
+ "lwcpa\t%0, (%1+), %3"
+ [(set_attr "length" "4")
+ (set_attr "stall" "load")])
+
+(define_insn "*swcpi"
+ [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
+ (match_operand:SI 2 "register_operand" "em"))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (match_dup 1)
+ (const_int 4)))]
+ "TARGET_COP && reload_completed"
+ "swcpi\t%2, (%0+)"
+ [(set_attr "length" "2")
+ (set_attr "stall" "store")])
+
+(define_insn "*swcpa"
+ [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
+ (match_operand:SI 2 "register_operand" "em"))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (match_dup 1)
+ (match_operand:SI 3 "cgen_h_sint_6a4_immediate" "")))]
+ "TARGET_COP && reload_completed"
+ "swcpa\t%2, (%0+), %3"
+ [(set_attr "length" "4")
+ (set_attr "stall" "store")])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (plus:SI (match_dup 0)
+ (match_operand:SI 1 "cgen_h_sint_8a1_immediate" "")))]
+ "TARGET_COP && mep_use_post_modify_p (insn, operands[0], operands[1])"
+ [(const_int 0)]
+{
+ emit_note (NOTE_INSN_DELETED);
+ DONE;
+})
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: Reloads
+;; ::
+;; ::::::::::::::::::::
+
+(define_expand "reload_insi"
+ [(set (match_operand:SI 0 "mep_reload_operand" "")
+ (match_operand:SI 1 "mep_reload_operand" "r"))
+ (clobber (match_operand:SI 2 "register_operand" "=&r"))]
+ ""
+ "
+{
+ mep_expand_reload (operands, SImode);
+ DONE;
+}")
+
+(define_expand "reload_outsi"
+ [(set (match_operand:SI 0 "mep_reload_operand" "=r")
+ (match_operand:SI 1 "mep_reload_operand" ""))
+ (clobber (match_operand:SI 2 "register_operand" "=&r"))]
+ ""
+ "
+{
+ mep_expand_reload (operands, SImode);
+ DONE;
+}")
+
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: Conversions
+;; ::
+;; ::::::::::::::::::::
+
+(define_insn "extendqisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,em")
+ (sign_extend:SI
+ (match_operand:QI 1 "nonimmediate_operand" "0,m,Y")))]
+ ""
+ "@
+ extb\\t%0
+ lb\\t%0, %1
+ lbcpa\\t%0, %P1"
+ [(set_attr "length" "2,*,*")
+ (set_attr "stall" "*,load,load")
+ (set_attr "memop" "*,core1,cop1")])
+
+(define_insn "extendhisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,em")
+ (sign_extend:SI
+ (match_operand:HI 1 "nonimmediate_operand" "0,m,Y")))]
+ ""
+ "@
+ exth\\t%0
+ lh\\t%0, %1
+ lhcpa\\t%0, %P1"
+ [(set_attr "length" "2,*,*")
+ (set_attr "stall" "*,load,load")
+ (set_attr "memop" "*,core1,cop1")])
+
+(define_insn "zero_extendqisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (zero_extend:SI
+ (match_operand:QI 1 "nonimmediate_operand" "0,r,m")))]
+ ""
+ "@
+ extub\\t%0
+ and3\\t%0, %1, 255
+ lbu\\t%0, %1"
+ [(set_attr "length" "2,4,*")
+ (set_attr "stall" "*,*,load")
+ (set_attr "memop" "*,*,core1")])
+
+(define_insn "zero_extendhisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (zero_extend:SI
+ (match_operand:HI 1 "nonimmediate_operand" "0,r,m")))]
+ ""
+ "@
+ extuh\\t%0
+ and3\\t%0, %1, 65535
+ lhu\\t%0, %1"
+ [(set_attr "length" "2,4,*")
+ (set_attr "stall" "*,*,load")
+ (set_attr "memop" "*,*,core1")])
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: 32 bit Integer arithmetic
+;; ::
+;; ::::::::::::::::::::
+
+(define_insn "addsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (plus:SI (match_operand:SI 1 "register_operand" "%r,0,r")
+ (match_operand:SI 2 "mep_add_operand" "r,L,IT")))]
+ ""
+ "@
+ add3\\t%0, %1, %2
+ add\\t%0, %2
+ add3\\t%0, %1, %I2"
+ [(set (attr "length")
+ (if_then_else (eq_attr "alternative" "2")
+ (if_then_else (and (match_operand:SI 1 "mep_sp_operand" "")
+ (match_operand:SI 2 "mep_imm7a4_operand" ""))
+ (const_int 2)
+ (const_int 4))
+ (const_int 2)))])
+
+;; The intention here is to combine the 16-bit add with the 16-bit
+;; move to create a 32-bit add. It's the same size, but takes one
+;; less machine cycle. It will happen to match a 32-bit add with a
+;; 16-bit move also, but gcc shouldn't be doing that ;)
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (plus:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "immediate_operand" "")))
+ (set (match_operand:SI 3 "register_operand" "")
+ (match_operand:SI 4 "register_operand" ""))]
+ "REGNO (operands[0]) == REGNO (operands[1])
+ && REGNO (operands[0]) == REGNO (operands[4])
+ && GR_REGNO_P (REGNO (operands[3]))
+ && dead_or_set_p (peep2_next_insn (1), operands[4])"
+ [(set (match_dup 3)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "")
+
+(define_insn "subsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (minus:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r")))]
+ ""
+ "sub\\t%0, %2"
+ [(set_attr "length" "2")])
+
+(define_expand "mulsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (mult:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "register_operand" "")))]
+ "TARGET_OPT_MULT || TARGET_COPRO_MULT"
+{
+ emit_insn (gen_mulsi3_1 (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+;; Generated by mep_reuse_lo_p when no GPR destination is needed.
+(define_insn "mulsi3_lo"
+ [(set (match_operand:SI 0 "mep_lo_operand" "=l")
+ (mult:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")))
+ (clobber (match_scratch:SI 3 "=h"))]
+ "TARGET_OPT_MULT && reload_completed"
+ "mul\\t%1, %2"
+ [(set_attr "length" "2")
+ (set_attr "stall" "mul")])
+
+;; Generated by mep_reuse_lo_p when both destinations of a mulr
+;; are needed.
+(define_insn "mulsi3r"
+ [(set (match_operand:SI 0 "mep_lo_operand" "=l")
+ (mult:SI (match_operand:SI 2 "register_operand" "1")
+ (match_operand:SI 3 "register_operand" "r")))
+ (set (match_operand:SI 1 "register_operand" "=r")
+ (mult:SI (match_dup 2)
+ (match_dup 3)))
+ (clobber (match_scratch:SI 4 "=h"))]
+ "TARGET_OPT_MULT && reload_completed"
+ "mulr\\t%2, %3"
+ [(set_attr "length" "2")
+ (set_attr "stall" "mulr")])
+
+(define_insn "mulsi3_1"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (mult:SI (match_operand:SI 1 "register_operand" "%0")
+ (match_operand:SI 2 "register_operand" "r")))
+ (clobber (match_scratch:SI 3 "=l"))
+ (clobber (match_scratch:SI 4 "=h"))]
+ "TARGET_OPT_MULT"
+ "mulr\\t%1, %2"
+ [(set_attr "length" "2")
+ (set_attr "stall" "mulr")])
+
+(define_expand "mulsidi3"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
+ (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))]
+ "TARGET_OPT_MULT"
+ "
+{
+ rtx hi = gen_reg_rtx (SImode);
+ rtx lo = gen_reg_rtx (SImode);
+
+ emit_insn (gen_mulsidi3_i (hi, lo, operands[1], operands[2]));
+ emit_move_insn (gen_lowpart (SImode, operands[0]), lo);
+ emit_move_insn (gen_highpart (SImode, operands[0]), hi);
+ DONE;
+}")
+
+(define_insn "mulsidi3_i"
+ [(set (match_operand:SI 0 "mep_hi_operand" "=h")
+ (truncate:SI
+ (lshiftrt:DI
+ (mult:DI (sign_extend:DI
+ (match_operand:SI 2 "register_operand" "r"))
+ (sign_extend:DI
+ (match_operand:SI 3 "register_operand" "r")))
+ (const_int 32))))
+ (set (match_operand:SI 1 "mep_lo_operand" "=l")
+ (mult:SI (match_dup 2)
+ (match_dup 3)))]
+ "TARGET_OPT_MULT"
+ "mul\\t%2, %3"
+ [(set_attr "length" "2")
+ (set_attr "stall" "mul")])
+
+(define_insn "smulsi3_highpart"
+ [(set (match_operand:SI 0 "mep_hi_operand" "=h")
+ (truncate:SI
+ (lshiftrt:DI
+ (mult:DI (sign_extend:DI
+ (match_operand:SI 1 "register_operand" "r"))
+ (sign_extend:DI
+ (match_operand:SI 2 "register_operand" "r")))
+ (const_int 32))))
+ (clobber (reg:SI LO_REGNO))]
+ "TARGET_OPT_MULT"
+ "mul\\t%1, %2"
+ [(set_attr "length" "2")
+ (set_attr "stall" "mul")])
+
+(define_expand "umulsidi3"
+ [(set (match_operand:DI 0 "mep_hi_operand" "")
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
+ (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))]
+ "TARGET_OPT_MULT"
+ "
+{
+ rtx hi = gen_reg_rtx (SImode);
+ rtx lo = gen_reg_rtx (SImode);
+
+ emit_insn (gen_umulsidi3_i (hi, lo, operands[1], operands[2]));
+ emit_move_insn (gen_lowpart (SImode, operands[0]), lo);
+ emit_move_insn (gen_highpart (SImode, operands[0]), hi);
+ DONE;
+}")
+
+(define_insn "umulsidi3_i"
+ [(set (match_operand:SI 0 "mep_hi_operand" "=h")
+ (truncate:SI
+ (lshiftrt:DI
+ (mult:DI (zero_extend:DI
+ (match_operand:SI 2 "register_operand" "r"))
+ (zero_extend:DI
+ (match_operand:SI 3 "register_operand" "r")))
+ (const_int 32))))
+ (set (match_operand:SI 1 "mep_lo_operand" "=l")
+ (mult:SI (match_dup 2)
+ (match_dup 3)))]
+ "TARGET_OPT_MULT"
+ "mulu\\t%2, %3"
+ [(set_attr "length" "2")
+ (set_attr "stall" "mul")])
+
+(define_insn "umulsi3_highpart"
+ [(set (match_operand:SI 0 "mep_hi_operand" "=h")
+ (truncate:SI
+ (lshiftrt:DI
+ (mult:DI (zero_extend:DI
+ (match_operand:SI 1 "register_operand" "r"))
+ (zero_extend:DI
+ (match_operand:SI 2 "register_operand" "r")))
+ (const_int 32))))
+ (clobber (reg:SI LO_REGNO))]
+ "TARGET_OPT_MULT"
+ "mulu %1, %2"
+ [(set_attr "length" "2")
+ (set_attr "stall" "mul")])
+
+;; These two don't currently match because we don't have an adddi3 pattern.
+(define_insn "*smultdi_and_add"
+ [(set (match_operand:DI 0 "mep_hi_operand" "=d")
+ (plus:DI (mult:DI (zero_extend:DI
+ (match_operand:SI 1 "register_operand" "r"))
+ (zero_extend:DI
+ (match_operand:SI 2 "register_operand" "r")))
+ (match_operand:DI 3 "mep_hi_operand" "0")))]
+ "TARGET_OPT_MULT && TARGET_BIG_ENDIAN"
+ "maddu\\t%1, %2"
+ [(set_attr "length" "4")
+ (set_attr "stall" "mul")])
+
+(define_insn "*umultdi_and_add"
+ [(set (match_operand:DI 0 "mep_hi_operand" "=d")
+ (plus:DI (mult:DI (sign_extend:DI
+ (match_operand:SI 1 "register_operand" "r"))
+ (sign_extend:DI
+ (match_operand:SI 2 "register_operand" "r")))
+ (match_operand:DI 3 "mep_hi_operand" "0")))]
+ "TARGET_OPT_MULT && TARGET_BIG_ENDIAN"
+ "madd\\t%1, %2"
+ [(set_attr "length" "4")
+ (set_attr "stall" "mul")])
+
+;; A pattern for 'r1 = r2 * r3 + r4'. There are three possible
+;; implementations:
+;;
+;; (1) 'mulr;add3'. This is usually the best choice if the instruction
+;; is not part of a natural multiply-accumulate chain. It has the
+;; same latency as 'stc;maddr' but doesn't tie up $lo for as long.
+;;
+;; (2) 'madd'. This is the best choice if the instruction is in the
+;; middle of a natural multiply-accumulate chain. r4 will already
+;; be in $lo and r1 will also be needed in $lo.
+;;
+;; (3) 'maddr'. This is the best choice if the instruction is at the
+;; end of a natural multiply-accumulate chain. r4 will be in $lo
+;; but r1 will be needed in a GPR.
+;;
+;; In theory, we could put all the alternatives into a single pattern and
+;; leave the register allocator to choose between them. However, this can
+;; sometimes produce poor results in practice.
+;;
+;; This pattern therefore describes a general GPR-to-GPR operation that
+;; has a slight preference for cases in which operands 0 and 1 are tied.
+;; After reload, we try to rewrite the patterns using peephole2s (if
+;; enabled), falling back on define_splits if that fails. See also
+;; mep_reuse_lo_p.
+(define_insn "maddsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "%0,r")
+ (match_operand:SI 2 "register_operand" "r,r"))
+ (match_operand:SI 3 "register_operand" "r,r")))
+ (clobber (match_scratch:SI 4 "=l,l"))
+ (clobber (match_scratch:SI 5 "=h,h"))]
+ "TARGET_OPT_MULT"
+ "#"
+ [(set_attr "length" "8")
+ (set_attr "stall" "mulr")])
+
+;; Implement maddsi3s using maddr if operand 3 is already available in $lo.
+(define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand" "")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "register_operand" ""))
+ (match_operand:SI 3 "register_operand" "")))
+ (clobber (match_scratch:SI 4 ""))
+ (clobber (match_scratch:SI 5 ""))])]
+ "TARGET_OPT_MULT
+ && reload_completed
+ && mep_reuse_lo_p (operands[4], operands[3], insn,
+ !rtx_equal_p (operands[1], operands[3])
+ && !rtx_equal_p (operands[2], operands[3])
+ && (rtx_equal_p (operands[0], operands[3])
+ || peep2_reg_dead_p (1, operands[3])))"
+ [(parallel
+ [(set (match_dup 4)
+ (plus:SI (mult:SI (match_dup 0)
+ (match_dup 2))
+ (match_dup 4)))
+ (set (match_dup 0)
+ (plus:SI (mult:SI (match_dup 0)
+ (match_dup 2))
+ (match_dup 4)))
+ (clobber (match_dup 5))])]
+ "operands[2] = mep_mulr_source (0, operands[0], operands[1], operands[2]);")
+
+;; This splitter implements maddsi3 as "mulr;add3". It only works if
+;; operands 0 and 3 are distinct, since operand 0 is clobbered before
+;; operand 3 is used.
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "register_operand" ""))
+ (match_operand:SI 3 "register_operand" "")))
+ (clobber (match_scratch:SI 4 ""))
+ (clobber (match_scratch:SI 5 ""))]
+ "TARGET_OPT_MULT
+ && reload_completed
+ && !rtx_equal_p (operands[0], operands[3])"
+ [(parallel [(set (match_dup 0)
+ (mult:SI (match_dup 0)
+ (match_dup 2)))
+ (clobber (match_dup 4))
+ (clobber (match_dup 5))])
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_dup 3)))]
+ "operands[2] = mep_mulr_source (0, operands[0], operands[1], operands[2]);")
+
+;; This is the fallback splitter for maddsi3. It moves operand 3 into
+;; $lo and then uses maddr.
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "register_operand" ""))
+ (match_operand:SI 3 "register_operand" "")))
+ (clobber (match_scratch:SI 4 ""))
+ (clobber (match_scratch:SI 5 ""))]
+ "TARGET_OPT_MULT
+ && reload_completed"
+ [(parallel [(set (match_dup 4)
+ (plus:SI (mult:SI (match_dup 0)
+ (match_dup 2))
+ (match_dup 4)))
+ (set (match_dup 0)
+ (plus:SI (mult:SI (match_dup 0)
+ (match_dup 2))
+ (match_dup 4)))
+ (clobber (match_dup 5))])]
+{
+ emit_move_insn (operands[4], operands[3]);
+ operands[2] = mep_mulr_source (0, operands[0], operands[1], operands[2]);
+})
+
+;; Remove unnecessary stcs to $lo. This cleans up the moves generated
+;; by earlier calls to mep_reuse_lo_p.
+(define_peephole2
+ [(set (match_operand:SI 0 "mep_lo_operand" "")
+ (match_operand:SI 1 "register_operand" ""))]
+ "TARGET_OPT_MULT
+ && mep_reuse_lo_p (operands[0], operands[1], insn,
+ peep2_reg_dead_p (1, operands[1]))"
+ [(const_int 0)]
+{
+ emit_note (NOTE_INSN_DELETED);
+ DONE;
+})
+
+(define_insn "maddsi3_lo"
+ [(set (match_operand:SI 0 "mep_lo_operand" "=l")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r"))
+ (match_operand:SI 3 "mep_lo_operand" "0")))
+ (clobber (match_scratch:SI 4 "=h"))]
+ "TARGET_OPT_MULT && reload_completed"
+ "madd\\t%1, %2"
+ [(set_attr "length" "4")
+ (set_attr "stall" "mul")])
+
+(define_insn "maddsi3r"
+ [(set (match_operand:SI 0 "mep_lo_operand" "=l")
+ (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "1")
+ (match_operand:SI 3 "register_operand" "r"))
+ (match_operand:SI 4 "register_operand" "0")))
+ (set (match_operand:SI 1 "register_operand" "=r")
+ (plus:SI (mult:SI (match_dup 2)
+ (match_dup 3))
+ (match_dup 4)))
+ (clobber (match_scratch:SI 5 "=h"))]
+ "TARGET_OPT_MULT && reload_completed"
+ "maddr\\t%2, %3"
+ [(set_attr "length" "4")
+ (set_attr "stall" "mulr")])
+
+(define_insn "*shift_1_or_2_and_add"
+ [(set (match_operand:SI 0 "mep_r0_operand" "=z")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "mep_slad_operand" "n"))
+ (match_operand:SI 3 "register_operand" "r")))]
+ ""
+ "sl%b2ad3\\t%0, %1, %3"
+ [(set_attr "length" "2")
+ (set_attr "stall" "int2")])
+
+(define_insn "divmodsi4"
+ [(set (match_operand:SI 0 "mep_lo_operand" "=l")
+ (div:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")))
+ (set (match_operand:SI 3 "mep_hi_operand" "=h")
+ (mod:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_OPT_DIV"
+ "div\\t%1, %2"
+ [(set_attr "length" "2")
+ (set_attr "stall" "div")
+ (set_attr "may_trap" "yes")])
+
+(define_insn "udivmodsi4"
+ [(set (match_operand:SI 0 "mep_lo_operand" "=l")
+ (udiv:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")))
+ (set (match_operand:SI 3 "mep_hi_operand" "=h")
+ (umod:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_OPT_DIV"
+ "divu\\t%1, %2"
+ [(set_attr "length" "2")
+ (set_attr "stall" "div")
+ (set_attr "may_trap" "yes")])
+
+(define_insn "negsi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (neg:SI (match_operand:SI 1 "register_operand" "r")))]
+ ""
+ "neg\\t%0, %1"
+ [(set_attr "length" "2")])
+
+;; We have "absolute difference between two regs" which isn't quite
+;; what gcc is expecting.
+(define_expand "abssi2"
+ [(set (match_dup 2) (const_int 0))
+ (set (match_operand:SI 0 "register_operand" "")
+ (abs:SI (minus:SI (match_operand:SI 1 "register_operand" "")
+ (match_dup 2))
+ ))]
+ "TARGET_OPT_ABSDIFF"
+ "operands[2] = gen_reg_rtx (SImode);")
+
+(define_insn "*absdiff"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (abs:SI (minus:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r"))))]
+ "TARGET_OPT_ABSDIFF"
+ "abs\\t%0, %2"
+ [(set_attr "length" "4")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (abs:SI (plus:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "immediate_operand" ""))))
+ (clobber (match_operand:SI 3 "register_operand" ""))]
+ "!reload_completed"
+ [(set (match_dup 3)
+ (match_dup 4))
+ (set (match_operand:SI 0 "register_operand" "")
+ (abs:SI (minus:SI (match_operand:SI 1 "register_operand" "")
+ (match_dup 3))))]
+ "operands[4] = GEN_INT (-INTVAL (operands[2]));")
+
+(define_insn "sminsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (smin:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "nonmemory_operand" "r")))]
+ "TARGET_OPT_MINMAX"
+ "min\\t%0, %2"
+ [(set_attr "length" "4")])
+
+(define_insn "smaxsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (smax:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "nonmemory_operand" "r")))]
+ "TARGET_OPT_MINMAX"
+ "max\\t%0, %2"
+ [(set_attr "length" "4")])
+
+(define_insn "uminsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (umin:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "nonmemory_operand" "r")))]
+ "TARGET_OPT_MINMAX"
+ "minu\\t%0, %2"
+ [(set_attr "length" "4")])
+
+(define_insn "umaxsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (umax:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "nonmemory_operand" "r")))]
+ "TARGET_OPT_MINMAX"
+ "maxu\\t%0, %2"
+ [(set_attr "length" "4")])
+
+;; Average: a = (b+c+1)>>1
+(define_insn "*averagesi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ashiftrt:SI (plus:SI (plus:SI
+ (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "r"))
+ (const_int 1))
+ (const_int 1)))]
+ "TARGET_OPT_AVERAGE"
+ "ave\\t%0, %2"
+ [(set_attr "length" "4")])
+
+;; clip support
+
+(define_insn "clip_maxmin"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (smax:SI (smin:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "immediate_operand" "n"))
+ (match_operand:SI 3 "immediate_operand" "n")))]
+ "mep_allow_clip (operands[2], operands[3], 1)"
+ "clip\\t%0, %B2"
+ [(set_attr "length" "4")])
+
+(define_insn "clip_minmax"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (smin:SI (smax:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "immediate_operand" "n"))
+ (match_operand:SI 3 "immediate_operand" "n")))]
+ "mep_allow_clip (operands[3], operands[2], 1)"
+ "clip\\t%0, %B3"
+ [(set_attr "length" "4")])
+
+(define_insn "clipu_maxmin"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (smax:SI (smin:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "immediate_operand" "n"))
+ (match_operand:SI 3 "immediate_operand" "n")))]
+ "mep_allow_clip (operands[2], operands[3], 0)"
+ "clipu\\t%0, %U2"
+ [(set_attr "length" "4")])
+
+(define_insn "clipu_minmax"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (smin:SI (smax:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "immediate_operand" "n"))
+ (match_operand:SI 3 "immediate_operand" "n")))]
+ "mep_allow_clip (operands[3], operands[2], 0)"
+ "clipu\\t%0, %U3"
+ [(set_attr "length" "4")])
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: 32 bit Integer Shifts and Rotates
+;; ::
+;; ::::::::::::::::::::
+
+(define_insn "ashlsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,z")
+ (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
+ (match_operand:SI 2 "nonmemory_operand" "rM,M")))]
+ ""
+ "@
+ sll\\t%0, %2
+ sll3\\t%0, %1, %2"
+ [(set_attr "length" "2,2")
+ (set_attr "shiftop" "operand2")])
+
+(define_insn "ashrsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "nonmemory_operand" "rM")))]
+ ""
+ "sra\\t%0, %2"
+ [(set_attr "length" "2")
+ (set_attr "shiftop" "operand2")])
+
+(define_insn "lshrsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "nonmemory_operand" "rM")))]
+ ""
+ "srl\\t%0, %2"
+ [(set_attr "length" "2")
+ (set_attr "shiftop" "operand2")])
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: 32 Bit Integer Logical operations
+;; ::
+;; ::::::::::::::::::::
+
+(define_insn "andsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (and:SI (match_operand:SI 1 "register_operand" "%0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,J")))]
+ ""
+ "@
+ and\\t%0, %2
+ and3\\t%0, %1, %J2"
+ [(set_attr "length" "2,4")])
+
+(define_insn "iorsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (ior:SI (match_operand:SI 1 "register_operand" "%0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,J")))]
+ ""
+ "@
+ or\\t%0, %2
+ or3\\t%0, %1, %J2"
+ [(set_attr "length" "2,4")])
+
+(define_insn "xorsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (xor:SI (match_operand:SI 1 "register_operand" "%0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,J")))]
+ ""
+ "@
+ xor\\t%0, %2
+ xor3\\t%0, %1, %J2"
+ [(set_attr "length" "2,4")])
+
+(define_expand "one_cmplsi2"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (not:SI (match_operand:SI 1 "register_operand" "")))]
+ ""
+ "operands[2] = operands[1];
+ ")
+
+;; No separate insn for this; use NOR
+(define_insn "*one_cmplsi3_internal"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (not:SI (match_operand:SI 1 "register_operand" "0")))]
+ ""
+ "nor\\t%0, %0"
+ [(set_attr "length" "2")])
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: Bit Manipulation
+;; ::
+;; ::::::::::::::::::::
+
+(define_insn "*bitop_be"
+ [(set (match_operand:QI 0 "mep_Y_operand" "=Y")
+ (subreg:QI (match_operator:SI 3 "mep_bit_operator"
+ [(subreg:SI (match_operand:QI 1 "mep_Y_operand" "0") 0)
+ (match_operand 2 "immediate_operand" "n")])
+ 3)
+ )]
+ "TARGET_BIG_ENDIAN && TARGET_OPT_BITOPS
+ && rtx_equal_p (operands[0], operands[1])"
+ "b%L3m\\t%0, %b2"
+ [(set_attr "length" "2")])
+
+(define_insn "*bitop_le"
+ [(set (match_operand:QI 0 "mep_Y_operand" "=Y")
+ (subreg:QI (match_operator:SI 3 "mep_bit_operator"
+ [(subreg:SI (match_operand:QI 1 "mep_Y_operand" "0") 0)
+ (match_operand 2 "immediate_operand" "n")])
+ 0)
+ )]
+ "!TARGET_BIG_ENDIAN && TARGET_OPT_BITOPS
+ && rtx_equal_p (operands[0], operands[1])"
+ "b%L3m\\t%0, %b2"
+ [(set_attr "length" "2")])
+
+(define_insn "btstm"
+ [(set (match_operand:SI 0 "mep_r0_operand" "=z")
+ (and:SI (subreg:SI (match_operand:QI 1 "mep_Y_operand" "Y") 0)
+ (match_operand 2 "immediate_operand" "n"))
+ )]
+ "TARGET_OPT_BITOPS && mep_bit_position_p (operands[2], 1)"
+ "btstm\\t%0, %1, %b2"
+ [(set_attr "length" "2")])
+
+(define_insn "tas"
+ [(parallel [(set (match_operand:SI 0 "mep_r0_operand" "=z")
+ (zero_extend:SI (match_operand:QI 1 "mep_Y_operand" "+Y")))
+ (set (match_dup 1)
+ (const_int 1))
+ ]
+ )]
+ "TARGET_OPT_BITOPS"
+ "tas\\t%0, %1"
+ [(set_attr "length" "2")])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "mep_r0_operand" "")
+ (zero_extend:SI (match_operand:QI 1 "mep_Y_operand" "")))
+ (set (match_operand:QI 2 "register_operand" "")
+ (const_int 1))
+ (set (match_dup 1)
+ (match_dup 2))
+ ]
+ "TARGET_OPT_BITOPS"
+ [(parallel [(set (match_dup 0)
+ (zero_extend:SI (match_dup 1)))
+ (set (match_dup 1)
+ (const_int 1))
+ ])]
+ "")
+
+(define_peephole2
+ [(set (match_operand:SI 0 "mep_r0_operand" "")
+ (sign_extend:SI (match_operand:QI 1 "mep_Y_operand" "")))
+ (set (match_operand:QI 2 "register_operand" "")
+ (const_int 1))
+ (set (match_dup 1)
+ (match_dup 2))
+ ]
+ "TARGET_OPT_BITOPS"
+ [(parallel [(set (match_dup 0)
+ (zero_extend:SI (match_dup 1)))
+ (set (match_dup 1)
+ (const_int 1))
+ ])
+ (set (match_dup 0)
+ (sign_extend:SI (match_dup 3)))]
+ "operands[3] = gen_lowpart (QImode, operands[0]);")
+
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: Conditional branches and stores
+;; ::
+;; ::::::::::::::::::::
+
+(define_expand "cbranchsi4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+ "emit_jump_insn (gen_branch_true (operands[3],
+ mep_expand_cbranch (operands)));
+ DONE;")
+
+(define_expand "branch_true"
+ [(set (pc)
+ (if_then_else (match_operand 1 "" "")
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "")
+
+(define_expand "cstoresi4"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (match_operator:SI 1 "ordered_comparison_operator"
+ [(match_operand:SI 2 "register_operand" "")
+ (match_operand:SI 3 "nonmemory_operand" "")]))]
+ ""
+ "if (mep_expand_setcc (operands)) DONE; else FAIL;")
+
+;; ------------------------------------------------------------
+
+(define_insn "*slt"
+ [(set (match_operand:SI 0 "register_operand" "=z,z,r")
+ (lt:SI (match_operand:SI 1 "register_operand" "r,r,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,M,I")))]
+ ""
+ "slt3\\t%0, %1, %2"
+ [(set_attr "length" "2,2,4")])
+
+(define_insn "*sltu"
+ [(set (match_operand:SI 0 "register_operand" "=z,z,r")
+ (ltu:SI (match_operand:SI 1 "register_operand" "r,r,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,M,J")))]
+ ""
+ "sltu3\\t%0, %1, %2"
+ [(set_attr "length" "2,2,4")])
+
+(define_insn "*bcpeq_true"
+ [(set (pc)
+ (if_then_else (eq:SI (reg:SI CBCR_REGNO)
+ (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "bcpeq\t0, %l0"
+ [(set_attr "length" "4")])
+
+(define_insn "*bcpeq_false"
+ [(set (pc)
+ (if_then_else (eq:SI (reg:SI CBCR_REGNO)
+ (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ ""
+ "bcpne\t0, %l0"
+ [(set_attr "length" "4")])
+
+(define_insn "*bcpne_true"
+ [(set (pc)
+ (if_then_else (ne:SI (reg:SI CBCR_REGNO)
+ (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "bcpne\t0, %l0"
+ [(set_attr "length" "4")])
+
+(define_insn "*bcpne_false"
+ [(set (pc)
+ (if_then_else (ne:SI (reg:SI CBCR_REGNO)
+ (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ ""
+ "bcpeq\t0, %l0"
+ [(set_attr "length" "4")])
+
+;; ??? The lengths here aren't correct, since no attempt it made to
+;; find "beqz" in the 256-byte range. However, this should not affect
+;; bundling, since we never run core branches in parallel.
+
+(define_insn "mep_beq_true"
+ [(set (pc)
+ (if_then_else (eq (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "mep_reg_or_imm4_operand" "rN"))
+ (label_ref (match_operand 2 "" ""))
+ (pc)))]
+ ""
+ "* return mep_emit_cbranch (operands, 0);"
+ [(set_attr "length" "4")] )
+
+(define_insn "*beq_false"
+ [(set (pc)
+ (if_then_else (eq (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "mep_reg_or_imm4_operand" "rN"))
+ (pc)
+ (label_ref (match_operand 2 "" ""))))]
+ ""
+ "* return mep_emit_cbranch (operands, 1);"
+ [(set_attr "length" "4")])
+
+(define_insn "mep_bne_true"
+ [(set (pc)
+ (if_then_else (ne (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "mep_reg_or_imm4_operand" "rN"))
+ (label_ref (match_operand 2 "" ""))
+ (pc)))]
+ ""
+ "* return mep_emit_cbranch (operands, 1); "
+ [(set_attr "length" "4")])
+
+(define_insn "*bne_false"
+ [(set (pc)
+ (if_then_else (ne (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "mep_reg_or_imm4_operand" "rN"))
+ (pc)
+ (label_ref (match_operand 2 "" ""))))]
+ ""
+ "* return mep_emit_cbranch (operands, 0); "
+ [(set_attr "length" "4")])
+
+(define_insn "mep_blti"
+ [(set (pc)
+ (if_then_else (lt (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "mep_imm4_operand" "N"))
+ (label_ref (match_operand 2 "" ""))
+ (pc)))]
+ ""
+ "blti\\t%0, %1, %l2"
+ [(set_attr "length" "4")])
+
+(define_insn "*bgei"
+ [(set (pc)
+ (if_then_else (ge (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "mep_imm4_operand" "N"))
+ (label_ref (match_operand 2 "" ""))
+ (pc)))]
+ ""
+ "bgei\\t%0, %1, %l2"
+ [(set_attr "length" "4")])
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: Call and branch instructions
+;; ::
+;; ::::::::::::::::::::
+
+(define_expand "call"
+ [(parallel [(call (match_operand:QI 0 "" "")
+ (match_operand:SI 1 "" ""))
+ (use (match_operand:SI 2 "" ""))
+ (clobber (reg:SI REGSAVE_CONTROL_TEMP))
+ ])]
+ ""
+ "
+{
+ mep_expand_call (operands, 0);
+ DONE;
+}")
+
+(define_insn "call_internal"
+ [(call (mem (match_operand:SI 0 "mep_call_address_operand" "R,r"))
+ (match_operand:SI 1 "" ""))
+ (use (match_operand:SI 2 "const_int_operand" ""))
+ (use (match_operand:SI 3 "mep_tp_operand" "b,b"))
+ (use (match_operand:SI 4 "mep_gp_operand" "v,v"))
+ (clobber (reg:SI LP_REGNO))
+ (clobber (reg:SI REGSAVE_CONTROL_TEMP))
+ ]
+ ""
+{
+ static char const pattern[2][2][8] =
+ {
+ { "bsrv\t%0", "jsrv\t%0" },
+ { "bsr\t%0", "jsr\t%0" }
+ };
+
+ return pattern[mep_vliw_mode_match (operands[2])][which_alternative];
+}
+ [(set_attr "length" "4,2")])
+
+(define_expand "sibcall"
+ [(parallel [(call (match_operand:QI 0 "" "")
+ (match_operand:SI 1 "" ""))
+ (use (match_operand:SI 2 "" ""))
+ (use (reg:SI LP_REGNO))
+ (clobber (reg:SI REGSAVE_CONTROL_TEMP))
+ ])]
+ ""
+ "")
+
+(define_insn "*sibcall_internal"
+ [(call (mem (match_operand:SI 0 "mep_nearsym_operand" "s"))
+ (match_operand:SI 1 "" ""))
+ (use (match_operand:SI 2 "const_int_operand" ""))
+ (use (reg:SI LP_REGNO))
+ (clobber (reg:SI REGSAVE_CONTROL_TEMP))
+ ]
+ "SIBLING_CALL_P (insn)"
+{
+ if (mep_vliw_mode_match (operands[2]))
+ return "jmp\t%0";
+ else
+ return
+ "ldc $12, $lp\n\
+ movh $11, %%hi(%0)\n\
+ xor3 $12, $12, 1\n\
+ add3 $11, $11, %%lo(%0+1)\n\
+ stc $12, $lp\n\
+ jmp $11";
+}
+ [(set_attr "length" "48")
+ (set_attr "slot" "multi")])
+
+(define_expand "call_value"
+ [(parallel [(set (match_operand 0 "" "")
+ (call (match_operand:QI 1 "" "")
+ (match_operand:SI 2 "" "")))
+ (use (match_operand:SI 3 "" ""))
+ (clobber (reg:SI REGSAVE_CONTROL_TEMP))
+ ])]
+ ""
+ "
+{
+ mep_expand_call (operands, 1);
+ DONE;
+}")
+
+(define_insn "call_value_internal"
+ [(set (match_operand 0 "register_operand" "=rx,rx")
+ (call (mem:SI (match_operand:SI 1 "mep_call_address_operand" "R,r"))
+ (match_operand:SI 2 "" "")))
+ (use (match_operand:SI 3 "const_int_operand" ""))
+ (use (match_operand:SI 4 "mep_tp_operand" "b,b"))
+ (use (match_operand:SI 5 "mep_gp_operand" "v,v"))
+ (clobber (reg:SI LP_REGNO))
+ (clobber (reg:SI REGSAVE_CONTROL_TEMP))
+ ]
+ ""
+{
+ static char const pattern[2][2][8] =
+ {
+ { "bsrv\t%1", "jsrv\t%1" },
+ { "bsr\t%1", "jsr\t%1" }
+ };
+
+ return pattern[mep_vliw_mode_match (operands[3])][which_alternative];
+}
+ [(set_attr "length" "4,2")])
+
+(define_expand "sibcall_value"
+ [(parallel [(set (match_operand 0 "" "")
+ (call (match_operand:QI 1 "" "")
+ (match_operand:SI 2 "" "")))
+ (use (match_operand:SI 3 "" ""))
+ (use (reg:SI LP_REGNO))
+ (clobber (reg:SI REGSAVE_CONTROL_TEMP))
+ ])]
+ ""
+ "")
+
+(define_insn "*sibcall_value_internal"
+ [(set (match_operand 0 "register_operand" "=rx")
+ (call (mem (match_operand:SI 1 "mep_nearsym_operand" "s"))
+ (match_operand:SI 2 "" "")))
+ (use (match_operand:SI 3 "const_int_operand" ""))
+ (use (reg:SI LP_REGNO))
+ (clobber (reg:SI REGSAVE_CONTROL_TEMP))
+ ]
+ "SIBLING_CALL_P (insn)"
+{
+ if (mep_vliw_mode_match (operands[3]))
+ return "jmp\t%1";
+ else
+ return
+ "ldc $12, $lp\n\
+ movh $11, %%hi(%1)\n\
+ xor3 $12, $12, 1\n\
+ add3 $11, $11, %%lo(%1+1)\n\
+ stc $12, $lp\n\
+ jmp $11";
+}
+ [(set_attr "length" "48")
+ (set_attr "slot" "multi")])
+
+(define_insn "return_internal"
+ [(return)
+ (use (match_operand:SI 0 "register_operand" ""))]
+ ""
+ "* return (REGNO (operands[0]) == LP_REGNO) ? \"ret\" : \"jmp\\t%0\";"
+ [(set_attr "length" "2")
+ (set_attr "stall" "ret")])
+
+(define_insn "eh_return_internal"
+ [(return)
+ (use (reg:SI 10))
+ (use (reg:SI 11))
+ (use (reg:SI LP_REGNO))
+ (clobber (reg:SI REGSAVE_CONTROL_TEMP))
+ ]
+ ""
+ "ret"
+ [(set_attr "length" "2")
+ (set_attr "stall" "ret")])
+
+;; The assembler replaces short jumps with long jumps as needed.
+(define_insn "jump"
+ [(set (pc) (label_ref (match_operand 0 "" "")))]
+ ""
+ "bra\\t%l0"
+ [(set_attr "length" "4")])
+
+(define_insn "indirect_jump"
+ [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
+ ""
+ "jmp\\t%0"
+ [(set_attr "length" "2")])
+
+(define_insn "tablejump"
+ [(set (pc) (match_operand:SI 0 "register_operand" "r"))
+ (use (label_ref (match_operand 1 "" "")))]
+ ""
+ "jmp\\t%0"
+ [(set_attr "length" "2")])
+
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: Low Overhead Looping
+;; ::
+;; ::::::::::::::::::::
+
+;; This insn is volatile because we'd like it to stay in its original
+;; position, just before the loop header. If it stays there, we might
+;; be able to convert it into a "repeat" insn.
+(define_insn "doloop_begin_internal"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "register_operand" "0")
+ (match_operand 2 "const_int_operand" "")] UNS_REPEAT_BEG))]
+ ""
+ { gcc_unreachable (); }
+ [(set_attr "length" "4")])
+
+(define_expand "doloop_begin"
+ [(use (match_operand 0 "register_operand" ""))
+ (use (match_operand:QI 1 "const_int_operand" ""))
+ (use (match_operand:QI 2 "const_int_operand" ""))
+ (use (match_operand:QI 3 "const_int_operand" ""))]
+ "!profile_arc_flag && TARGET_OPT_REPEAT"
+ "if (INTVAL (operands[3]) > 1)
+ FAIL;
+ mep_emit_doloop (operands, 0);
+ DONE;
+ ")
+
+(define_insn "doloop_end_internal"
+ [(set (pc)
+ (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+r,cxy,*m")
+ (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (const_int -1)))
+ (unspec [(match_operand 2 "const_int_operand" "")] UNS_REPEAT_END)
+ (clobber (match_scratch:SI 3 "=X,&r,&r"))]
+ ""
+ { gcc_unreachable (); }
+ ;; Worst case length:
+ ;;
+ ;; lw <op3>,<op0> 4
+ ;; add <op3>,-1 2
+ ;; sw <op3>,<op0> 4
+ ;; jmp <op1> 4
+ ;; 1f:
+ [(set_attr "length" "14")
+ (set_attr "slot" "multi")])
+
+(define_expand "doloop_end"
+ [(use (match_operand 0 "nonimmediate_operand" ""))
+ (use (match_operand:QI 1 "const_int_operand" ""))
+ (use (match_operand:QI 2 "const_int_operand" ""))
+ (use (match_operand:QI 3 "const_int_operand" ""))
+ (use (label_ref (match_operand 4 "" "")))]
+ "!profile_arc_flag && TARGET_OPT_REPEAT"
+ "if (INTVAL (operands[3]) > 1)
+ FAIL;
+ if (GET_CODE (operands[0]) == REG && GET_MODE (operands[0]) != SImode)
+ FAIL;
+ mep_emit_doloop (operands, 1);
+ DONE;
+ ")
+
+(define_insn "repeat"
+ [(set (reg:SI RPC_REGNO)
+ (unspec:SI [(match_operand:SI 0 "mep_r0_15_operand" "r")
+ (match_operand:SI 1 "" "")]
+ UNS_REPEAT_BEG))]
+ ""
+ "repeat\\t%0,%l1"
+ [(set_attr "length" "4")])
+
+(define_insn "repeat_end"
+ [(unspec [(const_int 0)] UNS_REPEAT_END)]
+ ""
+ "# repeat end"
+ [(set_attr "length" "0")])
+
+(define_insn "erepeat"
+ [(unspec [(match_operand 0 "" "")] UNS_EREPEAT_BEG)]
+ ""
+ "erepeat\\t%l0"
+ [(set_attr "length" "4")])
+
+(define_insn "erepeat_end"
+ [(unspec [(const_int 0)] UNS_EREPEAT_END)]
+ ""
+ "# erepeat end"
+ [(set_attr "length" "0")
+ (set_attr "slot" "multi")])
+
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: Prologue and Epilogue instructions
+;; ::
+;; ::::::::::::::::::::
+
+(define_expand "prologue"
+ [(const_int 1)]
+ ""
+ "
+{
+ mep_expand_prologue ();
+ DONE;
+}")
+
+(define_expand "epilogue"
+ [(return)]
+ ""
+ "
+{
+ mep_expand_epilogue ();
+ DONE;
+}")
+
+(define_expand "eh_return"
+ [(use (match_operand:SI 0 "register_operand" "r"))]
+ ""
+ "
+{
+ mep_expand_eh_return (operands);
+ DONE;
+}")
+
+(define_insn_and_split "eh_epilogue"
+ [(unspec [(match_operand:SI 0 "register_operand" "r")] UNS_EH_EPILOGUE)
+ (use (reg:SI LP_REGNO))]
+ ""
+ "#"
+ "reload_completed"
+ [(const_int 1)]
+ "mep_emit_eh_epilogue (operands); DONE;"
+ [(set_attr "slot" "multi")])
+
+(define_expand "sibcall_epilogue"
+ [(const_int 0)]
+ ""
+ "
+{
+ mep_expand_sibcall_epilogue ();
+ DONE;
+}")
+
+(define_insn "mep_bb_trace_ret"
+ [(unspec_volatile [(const_int 0)] UNS_BB_TRACE_RET)]
+ ""
+ "* return mep_emit_bb_trace_ret ();"
+ [(set_attr "slot" "multi")])
+
+(define_insn "mep_disable_int"
+ [(unspec_volatile [(const_int 0)] UNS_DISABLE_INT)]
+ ""
+ "di"
+ [(set_attr "length" "2")])
+
+(define_insn "mep_enable_int"
+ [(unspec_volatile [(const_int 0)] UNS_ENABLE_INT)]
+ ""
+ "ei"
+ [(set_attr "length" "2")])
+
+(define_insn "mep_reti"
+ [(return)
+ (unspec_volatile [(const_int 0)] UNS_RETI)]
+ ""
+ "reti"
+ [(set_attr "length" "2")])
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: Miscellaneous instructions
+;; ::
+;; ::::::::::::::::::::
+
+(define_insn "nop"
+ [(const_int 0)]
+ ""
+ "nop"
+ [(set_attr "length" "2")])
+
+(define_insn "nop32"
+ [(const_int 1)]
+ ""
+ "or3\\t$0, $0, 0"
+ [(set_attr "length" "4")])
+
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNS_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")
+ (set_attr "slot" "multi")])
+
+
+(define_insn "djmark"
+ [(unspec_volatile [(const_int 0)] 999)]
+ ""
+ "# dj"
+ [(set_attr "length" "0")
+ (set_attr "slot" "multi")])
+
--- /dev/null
+; Target specific command line options for the MEP port of the compiler.
+; Copyright (C) 2005, 2007, 2009 Free Software Foundation, Inc.
+; Contributed by Red Hat Inc.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 3, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+; for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING3. If not see
+; <http://www.gnu.org/licenses/>. */
+
+mabsdiff
+Target Mask(OPT_ABSDIFF)
+Enable absolute difference instructions
+
+mall-opts
+Target RejectNegative
+Enable all optional instructions
+
+maverage
+Target Mask(OPT_AVERAGE)
+Enable average instructions
+
+mbased=
+Target Joined Var(mep_based_cutoff) RejectNegative UInteger Init(0)
+Variables this size and smaller go in the based section. (default 0)
+
+mbitops
+Target Mask(OPT_BITOPS)
+Enable bit manipulation instructions
+
+mc=
+Target Joined Var(mep_const_section) RejectNegative
+Section to put all const variables in (tiny, near, far) (no default)
+
+mclip
+Target Mask(OPT_CLIP)
+Enable clip instructions
+
+mconfig=
+Target Joined Var(mep_config_string) RejectNegative
+Configuration name
+
+mcop
+Target Mask(COP)
+Enable MeP Coprocessor
+
+mcop32
+Target Mask(COP) MaskExists RejectNegative
+Enable MeP Coprocessor with 32-bit registers
+
+mcop64
+Target Mask(64BIT_CR_REGS) RejectNegative
+Enable MeP Coprocessor with 64-bit registers
+
+mivc2
+Target Mask(IVC2) RejectNegative
+Enable IVC2 scheduling
+
+mdc
+Target Mask(DC) RejectNegative
+Const variables default to the near section
+
+mdebug
+Target Disabled Undocumented
+
+mdiv
+Target Mask(OPT_DIV)
+Enable 32-bit divide instructions
+
+meb
+Target InverseMask(LITTLE_ENDIAN) RejectNegative
+Use big-endian byte order
+
+mel
+Target Mask(LITTLE_ENDIAN) RejectNegative
+Use little-endian byte order
+
+mfar
+Target RejectNegative
+Enable -ml, -mtf, and -mc=far
+
+mio-volatile
+Target Mask(IO_VOLATILE)
+__io vars are volatile by default
+
+ml
+Target Mask(L) RejectNegative
+All variables default to the far section
+
+mleadz
+Target Mask(OPT_LEADZ)
+Enable leading zero instructions
+
+mlibrary
+Target Mask(LIBRARY) RejectNegative Undocumented
+
+mm
+Target Mask(M) RejectNegative
+All variables default to the near section
+
+mminmax
+Target Mask(OPT_MINMAX)
+Enable min/max instructions
+
+mmult
+Target Mask(OPT_MULT)
+Enable 32-bit multiply instructions
+
+mno-opts
+Target RejectNegative
+Disable all optional instructions
+
+mrand-tpgp
+Target Mask(RAND_TPGP) RejectNegative Undocumented
+
+mrepeat
+Target Mask(OPT_REPEAT)
+Allow gcc to use the repeat/erepeat instructions
+
+ms
+Target Mask(S) RejectNegative
+All variables default to the tiny section
+
+msatur
+Target Mask(OPT_SATUR)
+Enable saturation instructions
+
+msdram
+Target
+Use sdram version of runtime
+
+msim
+Target RejectNegative
+Use simulator runtime
+
+msimnovec
+Target RejectNegative
+Use simulator runtime without vectors
+
+mtf
+Target Mask(TF) RejectNegative
+All functions default to the far section
+
+mtiny=
+Target Joined Var(mep_tiny_cutoff) RejectNegative UInteger Init(4)
+Variables this size and smaller go in the tiny section. (default 4)
+
+mvl32
+Target InverseMask(OPT_VL64) Undocumented RejectNegative
+
+mvl64
+Target Mask(OPT_VL64) Undocumented RejectNegative
+
+mvliw
+Target Mask(VLIW) Undocumented
--- /dev/null
+;; Toshiba Media Processor Machine predicates
+;; Copyright (C) 2009 Free Software Foundation, Inc.
+;; Contributed by Red Hat Inc.
+
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>. */
+
+;; (define_predicate "cgen_h_uint_7a1_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_6a2_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_22a4_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_sint_2a1_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_24a1_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_sint_6a1_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_5a4_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_2a1_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_16a1_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_3a1_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_5a1_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_sint_16a1_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_sint_5a8_immediate"
+;; (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_4a1_immediate"
+;; (match_code "const_int"))
+
+(define_predicate "cgen_h_sint_7a2_immediate"
+ (match_code "const_int")
+ { int i = INTVAL (op);
+ return ((i & 1) == 0 && i >= -128 && i < 128);
+ })
+
+(define_predicate "cgen_h_sint_6a4_immediate"
+ (match_code "const_int")
+ { int i = INTVAL (op);
+ return ((i & 3) == 0 && i >= -256 && i < 256);
+ })
+
+;; This is used below, to simplify things.
+(define_predicate "mep_subreg_operand"
+ (ior
+ (and (and (and (match_code "subreg")
+ (match_code "reg" "0"))
+ (match_test "REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER"))
+ (match_test "!(reload_completed || reload_in_progress)"))
+ (and (match_code "reg")
+ (match_test "REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
+
+(define_predicate "symbolic_operand"
+ (match_code "const,symbol_ref,label_ref"))
+
+(define_predicate "mep_farsym_operand"
+ (and (match_code "const,symbol_ref")
+ (match_test "mep_section_tag (op) == 'f'")))
+
+(define_predicate "mep_nearsym_operand"
+ (and (match_code "const,symbol_ref,label_ref")
+ (match_test "mep_section_tag (op) != 'f'")))
+
+(define_predicate "mep_movdest_operand"
+ (and (match_test "mep_section_tag (op) != 'f'")
+ (match_operand 0 "nonimmediate_operand")))
+
+(define_predicate "mep_r0_15_operand"
+ (ior (match_operand 0 "mep_subreg_operand")
+ (and (match_code "reg")
+ (match_test "GR_REGNO_P (REGNO (op))"))))
+
+(define_predicate "mep_r0_operand"
+ (and (match_code "reg")
+ (ior (match_test "REGNO (op) == 0")
+ (match_test "!(reload_completed || reload_in_progress)
+ && REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
+
+(define_predicate "mep_hi_operand"
+ (ior (match_operand 0 "mep_subreg_operand")
+ (and (match_code "reg")
+ (match_test "REGNO (op) == HI_REGNO"))))
+
+(define_predicate "mep_lo_operand"
+ (ior (match_operand 0 "mep_subreg_operand")
+ (and (match_code "reg")
+ (match_test "REGNO (op) == LO_REGNO"))))
+
+(define_predicate "mep_tp_operand"
+ (ior (match_operand 0 "mep_subreg_operand")
+ (and (match_code "reg")
+ (match_test "REGNO (op) == TP_REGNO"))))
+
+(define_predicate "mep_gp_operand"
+ (ior (match_operand 0 "mep_subreg_operand")
+ (and (match_code "reg")
+ (match_test "REGNO (op) == GP_REGNO"))))
+
+(define_predicate "mep_sp_operand"
+ (match_test "op == stack_pointer_rtx"))
+
+(define_predicate "mep_tprel_operand"
+ (ior (match_operand 0 "mep_subreg_operand")
+ (and (match_code "reg")
+ (match_test "REGNO (op) < 8"))))
+
+(define_predicate "mep_call_address_operand"
+ (and (match_test "mep_section_tag (op) != 'f'")
+ (and (ior (not (match_code "symbol_ref"))
+ (match_test "mep_section_tag (DECL_RTL (cfun->decl)) != 'f'
+ && !mep_lookup_pragma_call (XSTR (op, 0))"))
+ (match_code "symbol_ref,reg"))))
+
+(define_predicate "mep_Y_operand"
+ (and (match_code "mem")
+ (match_code "reg" "0")))
+
+(define_predicate "mep_imm4_operand"
+ (and (match_code "const_int")
+ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15")))
+
+(define_predicate "mep_reg_or_imm4_operand"
+ (ior (match_code "reg")
+ (and (match_code "const_int")
+ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15"))))
+
+(define_predicate "mep_imm7a4_operand"
+ (and (match_code "const_int")
+ (match_test "INTVAL (op) >= 0 && INTVAL (op) < 128 && INTVAL (op) % 4 == 0")))
+
+(define_predicate "mep_slad_operand"
+ (and (match_code "const_int")
+ (match_test "INTVAL (op) == 2 || INTVAL (op) == 4")))
+
+(define_predicate "mep_add_operand"
+ (ior (and (match_code "const")
+ (and (match_operand 0 "symbolic_operand")
+ (and (match_test "mep_section_tag(op) == 'b' || mep_section_tag(op) == 't'")
+ (ior (match_code "unspec" "0")
+ (and (match_code "plus" "0")
+ (match_code "unspec" "00"))))))
+ (match_code "const_int,reg")))
+
+;; Return true if OP is an integer in the range 0..7 inclusive.
+;; On the MeP-h1, shifts by such constants execute in a single stage
+;; and shifts by larger values execute in two.
+(define_predicate "mep_single_shift_operand"
+ (and (match_code "const_int")
+ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
+
+;; Return true if OP is an operation that can be performed using bsetm,
+;; bclrm or bnotm. The possibilities are:
+
+;; bsetm: (ior X Y), Y has one bit set
+;; bclrm: (and X Y), Y has one bit clear
+;; bnotm: (xor X Y), Y has one bit set.
+(define_predicate "mep_bit_operator"
+ (and (match_code "and,ior,xor")
+ (match_test "mep_bit_position_p (XEXP (op, 1), GET_CODE (op) != AND)")))
+
+(define_predicate "mep_reload_operand"
+ (ior (and (match_code "reg")
+ (match_test "!ANY_CONTROL_REGNO_P (REGNO (op))"))
+ (and (match_code "mem,symbol_ref")
+ (match_test "mep_section_tag (op) != 'f'"))))
--- /dev/null
+# -*- makefile -*-
+# GCC makefile fragment for MeP
+# Copyright (C) 2001, 2002, 2003, 2005, 2007, 2009
+# Free Software Foundation, Inc.
+# Contributed by Red Hat Inc
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>. */
+
+# Force genpreds to be rebuilt in case MeP-Integrator changed the predicates
+
+GTM_H = tm.h $(tm_file_list) $(srcdir)/config/mep/mep-intrin.h
+
+# Use -O0 instead of -O2 so we don't get complex relocations
+
+CRTSTUFF_CFLAGS = -O0 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \
+ -finhibit-size-directive -fno-inline-functions -fno-exceptions \
+ -fno-zero-initialized-in-bss -fno-unit-at-a-time
+
+TCFLAGS = -mlibrary
+
+mep-pragma.o: $(srcdir)/config/mep/mep-pragma.c $(CONFIG_H) $(SYSTEM_H) \
+ coretypes.h $(TM_H) $(TREE_H) $(RTL_H) toplev.h c-pragma.h \
+ $(CPPLIB_H) hard-reg-set.h output.h $(srcdir)/config/mep/mep-protos.h \
+ function.h insn-config.h reload.h $(TARGET_H)
+ $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
+
+# profiling support
+
+LIB1ASMSRC = mep/mep-lib1.asm
+
+LIB1ASMFUNCS = _mep_profile \
+ _mep_bb_init_trace \
+ _mep_bb_init \
+ _mep_bb_trace \
+ _mep_bb_increment
+
+# multiply and divide routines
+
+LIB2FUNCS_EXTRA = \
+ $(srcdir)/config/mep/mep-lib2.c \
+ $(srcdir)/config/mep/mep-tramp.c
+
+# floating point emulation libraries
+
+FPBIT = fp-bit.c
+DPBIT = dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+ echo '#define FLOAT' > fp-bit.c
+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+ cat $(srcdir)/config/fp-bit.c > dp-bit.c
+
+MULTILIB_OPTIONS = mel mall-opts mfar
+MULTILIB_DIRNAMES = el allopt far
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
+
+MD_INCLUDES = \
+ $(srcdir)/config/mep/intrinsics.md \
+ $(srcdir)/config/mep/predicates.md \
+ $(srcdir)/config/mep/constraints.md
+
+mep.o : $(srcdir)/config/mep/mep-intrin.h
+
+# begin-isas
+MEP_CORE = ext_core1
+MEP_COPRO = ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64
+# end-isas
+
+# To use this, you must have cgen and cgen/cpu in the same source tree as
+# gcc.
+cgen-maint :
+ S=`cd $(srcdir); pwd`; \
+ cd $$S/config/mep && \
+ guile -s $$S/../cgen/cgen-intrinsics.scm \
+ -s $$S/../cgen \
+ $(CGENFLAGS) \
+ -a $$S/../cgen/cpu/mep.cpu \
+ -m mep,c5 \
+ -i mep,$(MEP_CORE),$(MEP_COPRO) \
+ -K mep,$(MEP_CORE),$(MEP_COPRO) \
+ -M intrinsics.md \
+ -N mep-intrin.h \
+ -P intrinsics.h
+
+# start-extra-headers
+EXTRA_HEADERS = $(srcdir)/config/mep/intrinsics.h \
+ $(srcdir)/config/mep/default.h
+# end-extra-headers
simplify_while_replacing (loc, to, object, op0_mode);
}
+/* Try replacing every occurrence of FROM in subexpression LOC of INSN
+ with TO. After all changes have been made, validate by seeing
+ if INSN is still valid. */
+
+int
+validate_replace_rtx_subexp (rtx from, rtx to, rtx insn, rtx *loc)
+{
+ validate_replace_rtx_1 (loc, from, to, insn, true);
+ return apply_change_group ();
+}
+
/* Try replacing every occurrence of FROM in INSN with TO. After all
changes have been made, validate by seeing if INSN is still valid. */
extern int constrain_operands_cached (int);
extern int memory_address_p (enum machine_mode, rtx);
extern int strict_memory_address_p (enum machine_mode, rtx);
+extern int validate_replace_rtx_subexp (rtx, rtx, rtx, rtx *);
extern int validate_replace_rtx (rtx, rtx, rtx);
extern int validate_replace_rtx_part (rtx, rtx, rtx *, rtx);
extern int validate_replace_rtx_part_nosimplify (rtx, rtx, rtx *, rtx);
+2009-06-23 DJ Delorie <dj@redhat.com>
+
+ Add MeP port.
+ * lib/target-supports.exp: Add mep support (no profiling).
+
2009-06-23 Steve Ellcey <sje@cup.hp.com>
PR testsuite/39297
|| [istarget m32c-*-elf]
|| [istarget m68k-*-elf]
|| [istarget m68k-*-uclinux*]
+ || [istarget mep-*-elf]
|| [istarget mips*-*-elf*]
|| [istarget moxie-*-elf*]
|| [istarget xstormy16-*]
+2009-06-23 DJ Delorie <dj@redhat.com>
+
+ Add MeP port.
+ * config.host: Add mep support.
+
2009-06-22 Kai Tietz <kai.tietz@onevision.com>
* config.host: Add i386/${host_address}/t-fprules-softfp and
;;
m68k-*-*)
;;
+mep*-*-*)
+ ;;
mips*-*-*)
cpu_type=mips
;;
;;
m32c-*-elf*|m32c-*-rtems*)
;;
+mep*-*-*)
+ ;;
*)
echo "*** Configuration ${host} not supported" 1>&2
exit 1
+2009-06-23 DJ Delorie <dj@redhat.com>
+
+ Add MeP port.
+ * configure.host: Add mep support.
+
2009-06-23 Benjamin Kosnik <bkoz@redhat.com>
* doc/doxygen/user.cfg.in (PREDEFINED): Add _GLIBCXX_ATOMIC_BUILTINS_*.
hppa*)
try_cpu=hppa
;;
+ mep*)
+ EXTRA_CXX_FLAGS=-mm
+ try_cpu=generic
+ ;;
mips*)
try_cpu=mips
;;
projects / platform / upstream / linaro-gcc.git / commitdiff