return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START &&
Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
}
+
+/// Check whether the given Opcode is a target-specific opcode.
+static inline bool isTargetSpecificOpcode(unsigned Opcode) {
+ return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
+}
} // end namespace llvm
#endif
MII != End;) {
// MI might be invalidated by the assignment, so move the
// iterator before hand.
- assignInstr(*MII++);
+ MachineInstr &MI = *MII++;
+
+ // Ignore target-specific instructions: they should use proper regclasses.
+ if (isTargetSpecificOpcode(MI.getOpcode()))
+ continue;
+
+ assignInstr(MI);
}
}
OptMode = SaveOptMode;
entry:
ret void
}
+
+ define void @ignoreTargetSpecificInst() { ret void }
...
---
%1(64) = COPY %x1
%2(64) = G_OR <2 x s32> %0, %1
...
+
+---
+# CHECK-LABEL: name: ignoreTargetSpecificInst
+name: ignoreTargetSpecificInst
+isSSA: true
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+registers:
+ - { id: 0, class: gpr64 }
+ - { id: 1, class: gpr64 }
+body: |
+ bb.0:
+ liveins: %x0
+
+ ; CHECK: %0 = COPY %x0
+ ; CHECK-NEXT: %1 = ADDXrr %0, %0
+ ; CHECK-NEXT: %x0 = COPY %1
+ ; CHECK-NEXT: RET_ReallyLR implicit %x0
+
+ %0 = COPY %x0
+ %1 = ADDXrr %0, %0
+ %x0 = COPY %1
+ RET_ReallyLR implicit %x0
+...