Comment out peepholes that generate buggy code

From-SVN: r29858

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 06bebfc..29f7454 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+Thu Oct  7 15:23:28 1999  Michael Meissner  <meissner@cygnus.com>
+
+       * alpha.md (peephole2's): Comment out peephole2's that generate
+       buggy code.
+
 Thu Oct  7 12:00:53 1999  Richard Henderson  <rth@cygnus.com>
 
        * genrecog.c (add_to_sequence): Disable mode check for

diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index ab7dcb3..4fe909d 100644 (file)
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -5407,25 +5407,25 @@
 ;; Optimize sign-extension of SImode loads.  This shows up in the wake of
 ;; reload when converting fp->int.
 
-(define_peephole2
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (match_operand:SI 1 "memory_operand" "m"))
-   (set (match_operand:DI 2 "register_operand" "=r")
-        (sign_extend:DI (match_dup 0)))]
-  "rtx_equal_p (operands[0], operands[2])
-   || reg_dead_p (insn, operands[0])"
-  [(set (match_dup 2)
-       (sign_extend:DI (match_dup 1)))]
-  "")
-
-(define_peephole2
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (match_operand:SI 1 "hard_fp_register_operand" "f"))
-   (set (match_operand:DI 2 "register_operand" "=r")
-        (sign_extend:DI (match_dup 0)))]
-  "TARGET_FIX
-   && (rtx_equal_p (operands[0], operands[2])
-       || reg_dead_p (insn, operands[0]))"
-  [(set (match_dup 2)
-       (sign_extend:DI (match_dup 1)))]
-  "")
+;(define_peephole2
+;  [(set (match_operand:SI 0 "register_operand" "=r")
+;        (match_operand:SI 1 "memory_operand" "m"))
+;   (set (match_operand:DI 2 "register_operand" "=r")
+;        (sign_extend:DI (match_dup 0)))]
+;  "rtx_equal_p (operands[0], operands[2])
+;   || reg_dead_p (insn, operands[0])"
+;  [(set (match_dup 2)
+;      (sign_extend:DI (match_dup 1)))]
+;  "")
+;
+;(define_peephole2
+;  [(set (match_operand:SI 0 "register_operand" "=r")
+;        (match_operand:SI 1 "hard_fp_register_operand" "f"))
+;   (set (match_operand:DI 2 "register_operand" "=r")
+;        (sign_extend:DI (match_dup 0)))]
+;  "TARGET_FIX
+;   && (rtx_equal_p (operands[0], operands[2])
+;       || reg_dead_p (insn, operands[0]))"
+;  [(set (match_dup 2)
+;      (sign_extend:DI (match_dup 1)))]
+;  "")