DONE;
})
+(define_expand "vec_cmp<MSA:mode><mode_i>"
+ [(match_operand:<VIMODE> 0 "register_operand")
+ (match_operator 1 ""
+ [(match_operand:MSA 2 "register_operand")
+ (match_operand:MSA 3 "register_operand")])]
+ "ISA_HAS_MSA"
+{
+ mips_expand_vec_cmp_expr (operands);
+ DONE;
+})
+
+(define_expand "vec_cmpu<IMSA:mode><mode_i>"
+ [(match_operand:<VIMODE> 0 "register_operand")
+ (match_operator 1 ""
+ [(match_operand:IMSA 2 "register_operand")
+ (match_operand:IMSA 3 "register_operand")])]
+ "ISA_HAS_MSA"
+{
+ mips_expand_vec_cmp_expr (operands);
+ DONE;
+})
+
(define_insn "msa_insert_<msafmt_f>"
[(set (match_operand:MSA 0 "register_operand" "=f,f")
(vec_merge:MSA
extern void mips_register_frame_header_opt (void);
extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
+extern void mips_expand_vec_cmp_expr (rtx *);
/* Routines implemented in mips-d.c */
extern void mips_d_target_versions (void);
}
}
+void
+mips_expand_vec_cmp_expr (rtx *operands)
+{
+ rtx cond = operands[1];
+ rtx op0 = operands[2];
+ rtx op1 = operands[3];
+ rtx res = operands[0];
+
+ mips_expand_msa_cmp (res, GET_CODE (cond), op0, op1);
+}
+
/* Expand VEC_COND_EXPR, where:
MODE is mode of the result
VIMODE equivalent integer mode
--- /dev/null
+/* PR target/101132
+ This was triggering an ICE in do_store_flag when compiled with -mmsa -O3. */
+
+/* { dg-do compile } */
+/* { dg-options "-mmsa" } */
+
+int r_0, q_0;
+void bar() {
+ int i;
+ for (i = 0; i < 96; i++) {
+ r_0 = i << i ? 2 + i : -i;
+ q_0 = r_0 > 2 ?: i;
+ }
+}