dt-bindings: gpio: zynq: convert bindings to YAML

Convert gpio for Xilinx Zynq SoC bindings documentation to YAML.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>

diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.txt b/Documentation/devicetree/bindings/gpio/gpio-zynq.txt
deleted file mode 100644 (file)
index f693e82..0000000
--- a/Documentation/devicetree/bindings/gpio/gpio-zynq.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Xilinx Zynq GPIO controller Device Tree Bindings
--------------------------------------------
-
-Required properties:
-- #gpio-cells          : Should be two
-                         - First cell is the GPIO line number
-                         - Second cell is used to specify optional
-                           parameters (unused)
-- compatible           : Should be "xlnx,zynq-gpio-1.0" or
-                         "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
-                         or "xlnx,pmc-gpio-1.0
-- clocks               : Clock specifier (see clock bindings for details)
-- gpio-controller      : Marks the device node as a GPIO controller.
-- interrupts           : Interrupt specifier (see interrupt bindings for
-                         details)
-- interrupt-controller : Marks the device node as an interrupt controller.
-- #interrupt-cells     : Should be 2.  The first cell is the GPIO number.
-                         The second cell bits[3:0] is used to specify trigger type and level flags:
-                             1 = low-to-high edge triggered.
-                             2 = high-to-low edge triggered.
-                             4 = active high level-sensitive.
-                             8 = active low level-sensitive.
-- reg                  : Address and length of the register set for the device
-
-Example:
-       gpio@e000a000 {
-               #gpio-cells = <2>;
-               compatible = "xlnx,zynq-gpio-1.0";
-               clocks = <&clkc 42>;
-               gpio-controller;
-               interrupt-parent = <&intc>;
-               interrupts = <0 20 4>;
-               interrupt-controller;
-               #interrupt-cells = <2>;
-               reg = <0xe000a000 0x1000>;
-       };

diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
new file mode 100644 (file)
index 0000000..378da26
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/gpio-zynq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq GPIO controller Device Tree Bindings
+
+maintainers:
+  - Michal Simek <michal.simek@xilinx.com>
+
+properties:
+  compatible:
+    const: xlnx,zynq-gpio-1.0
+
+  reg:
+    maxItems: 1
+
+  "#gpio-cells":
+    const: 2
+
+  interrupts:
+    maxItems: 1
+
+  gpio-controller: true
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#gpio-cells"
+  - interrupts
+  - gpio-controller
+  - interrupt-controller
+  - "#interrupt-cells"
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio@e000a000 {
+      #gpio-cells = <2>;
+      compatible = "xlnx,zynq-gpio-1.0";
+      clocks = <&clkc 42>;
+      gpio-controller;
+      interrupt-parent = <&intc>;
+      interrupts = <0 20 4>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      reg = <0xe000a000 0x1000>;
+    };