crypto: hisilicon/qm - set the total number of queues
authorWeili Qian <qianweili@huawei.com>
Sat, 20 Mar 2021 11:27:43 +0000 (19:27 +0800)
committerHerbert Xu <herbert@gondor.apana.org.au>
Fri, 26 Mar 2021 09:15:57 +0000 (20:15 +1100)
Move the configuration of the total number of queues 'ctrl_qp_num'
from sec2/hpre/zip to qm.c. And get the total number of queues
from the hardware register for Kunpeng930.

Signed-off-by: Weili Qian <qianweili@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
drivers/crypto/hisilicon/hpre/hpre_main.c
drivers/crypto/hisilicon/qm.c
drivers/crypto/hisilicon/sec2/sec_main.c
drivers/crypto/hisilicon/zip/zip_main.c

index 87e8f4d..818e7f3 100644 (file)
@@ -13,7 +13,6 @@
 #include <linux/uacce.h>
 #include "hpre.h"
 
-#define HPRE_QUEUE_NUM_V2              1024
 #define HPRE_QM_ABNML_INT_MASK         0x100004
 #define HPRE_CTRL_CNT_CLR_CE_BIT       BIT(0)
 #define HPRE_COMM_CNT_CLR_CE           0x0
@@ -899,8 +898,6 @@ static int hpre_pf_probe_init(struct hpre *hpre)
        struct hisi_qm *qm = &hpre->qm;
        int ret;
 
-       qm->ctrl_qp_num = HPRE_QUEUE_NUM_V2;
-
        ret = hpre_set_user_domain_and_cache(qm);
        if (ret)
                return ret;
index e3688bf..d1d5137 100644 (file)
@@ -93,6 +93,8 @@
 #define QM_DB_PRIORITY_SHIFT_V1                48
 #define QM_DOORBELL_SQ_CQ_BASE_V2      0x1000
 #define QM_DOORBELL_EQ_AEQ_BASE_V2     0x2000
+#define QM_CAPBILITY                   0x100158
+#define QM_QP_NUN_MASK                 GENMASK(10, 0)
 #define QM_DB_CMD_SHIFT_V2             12
 #define QM_DB_RAND_SHIFT_V2            16
 #define QM_DB_INDEX_SHIFT_V2           32
@@ -4119,6 +4121,17 @@ void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
 }
 EXPORT_SYMBOL_GPL(hisi_qm_alg_unregister);
 
+static void qm_get_qp_num(struct hisi_qm *qm)
+{
+       if (qm->ver == QM_HW_V1)
+               qm->ctrl_qp_num = QM_QNUM_V1;
+       else if (qm->ver == QM_HW_V2)
+               qm->ctrl_qp_num = QM_QNUM_V2;
+       else
+               qm->ctrl_qp_num = readl(qm->io_base + QM_CAPBILITY) &
+                                       QM_QP_NUN_MASK;
+}
+
 static int hisi_qm_pci_init(struct hisi_qm *qm)
 {
        struct pci_dev *pdev = qm->pdev;
@@ -4146,6 +4159,9 @@ static int hisi_qm_pci_init(struct hisi_qm *qm)
                goto err_release_mem_regions;
        }
 
+       if (qm->fun_type == QM_HW_PF)
+               qm_get_qp_num(qm);
+
        ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
        if (ret < 0)
                goto err_iounmap;
index 78a6043..2360d31 100644 (file)
@@ -19,7 +19,6 @@
 
 #define SEC_VF_NUM                     63
 #define SEC_QUEUE_NUM_V1               4096
-#define SEC_QUEUE_NUM_V2               1024
 #define SEC_PF_PCI_DEVICE_ID           0xa255
 #define SEC_VF_PCI_DEVICE_ID           0xa256
 
@@ -784,11 +783,6 @@ static int sec_pf_probe_init(struct sec_dev *sec)
        struct hisi_qm *qm = &sec->qm;
        int ret;
 
-       if (qm->ver == QM_HW_V1)
-               qm->ctrl_qp_num = SEC_QUEUE_NUM_V1;
-       else
-               qm->ctrl_qp_num = SEC_QUEUE_NUM_V2;
-
        qm->err_ini = &sec_err_ini;
 
        ret = sec_set_user_domain_and_cache(qm);
index 02c4457..8f67d70 100644 (file)
@@ -18,7 +18,6 @@
 #define PCI_DEVICE_ID_ZIP_VF           0xa251
 
 #define HZIP_QUEUE_NUM_V1              4096
-#define HZIP_QUEUE_NUM_V2              1024
 
 #define HZIP_CLOCK_GATE_CTRL           0x301004
 #define COMP0_ENABLE                   BIT(0)
@@ -746,12 +745,6 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
 
        hisi_zip->ctrl = ctrl;
        ctrl->hisi_zip = hisi_zip;
-
-       if (qm->ver == QM_HW_V1)
-               qm->ctrl_qp_num = HZIP_QUEUE_NUM_V1;
-       else
-               qm->ctrl_qp_num = HZIP_QUEUE_NUM_V2;
-
        qm->err_ini = &hisi_zip_err_ini;
 
        hisi_zip_set_user_domain_and_cache(qm);