clk: zx: Add audio div clock method for zx296702

Add SPDIF/I2S divider clock method for zx296702

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/zte/Makefile b/drivers/clk/zte/Makefile
index 95b707c..74005aa 100644 (file)
--- a/drivers/clk/zte/Makefile
+++ b/drivers/clk/zte/Makefile
@@ -1,2 +1,2 @@
-obj-y := clk-pll.o
+obj-y := clk.o
 obj-$(CONFIG_SOC_ZX296702) += clk-zx296702.o

diff --git a/drivers/clk/zte/clk-pll.c b/drivers/clk/zte/clk.c
similarity index 55%
rename from drivers/clk/zte/clk-pll.c
rename to drivers/clk/zte/clk.c
index c3b221a..7c73c53 100644 (file)
--- a/drivers/clk/zte/clk-pll.c
+++ b/drivers/clk/zte/clk.c
@@ -13,10 +13,12 @@
 #include <linux/iopoll.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
+#include <asm/div64.h>
 
 #include "clk.h"
 
 #define to_clk_zx_pll(_hw) container_of(_hw, struct clk_zx_pll, hw)
+#define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw)
 
 #define CFG0_CFG1_OFFSET 4
 #define LOCK_FLAG BIT(30)
@@ -141,8 +143,9 @@ static const struct clk_ops zx_pll_ops = {
 };
 
 struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
-       unsigned long flags, void __iomem *reg_base,
-       const struct zx_pll_config *lookup_table, int count, spinlock_t *lock)
+                               unsigned long flags, void __iomem *reg_base,
+                               const struct zx_pll_config *lookup_table,
+                               int count, spinlock_t *lock)
 {
        struct clk_zx_pll *zx_pll;
        struct clk *clk;
@@ -170,3 +173,137 @@ struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
 
        return clk;
 }
+
+#define BPAR 1000000
+static u32 calc_reg(u32 parent_rate, u32 rate)
+{
+       u32 sel, integ, fra_div, tmp;
+       u64 tmp64 = (u64)parent_rate * BPAR;
+
+       do_div(tmp64, rate);
+       integ = (u32)tmp64 / BPAR;
+       integ = integ >> 1;
+
+       tmp = (u32)tmp64 % BPAR;
+       sel = tmp / BPAR;
+
+       tmp = tmp % BPAR;
+       fra_div = tmp * 0xff / BPAR;
+       tmp = (sel << 24) | (integ << 16) | (0xff << 8) | fra_div;
+
+       /* Set I2S integer divider as 1. This bit is reserved for SPDIF
+        * and do no harm.
+        */
+       tmp |= BIT(28);
+       return tmp;
+}
+
+static u32 calc_rate(u32 reg, u32 parent_rate)
+{
+       u32 sel, integ, fra_div, tmp;
+       u64 tmp64 = (u64)parent_rate * BPAR;
+
+       tmp = reg;
+       sel = (tmp >> 24) & BIT(0);
+       integ = (tmp >> 16) & 0xff;
+       fra_div = tmp & 0xff;
+
+       tmp = fra_div * BPAR;
+       tmp = tmp / 0xff;
+       tmp += sel * BPAR;
+       tmp += 2 * integ * BPAR;
+       do_div(tmp64, tmp);
+
+       return (u32)tmp64;
+}
+
+static unsigned long zx_audio_recalc_rate(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+       struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
+       u32 reg;
+
+       reg = readl_relaxed(zx_audio->reg_base);
+       return calc_rate(reg, parent_rate);
+}
+
+static long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *prate)
+{
+       u32 reg;
+
+       if (rate * 2 > *prate)
+               return -EINVAL;
+
+       reg = calc_reg(*prate, rate);
+       return calc_rate(reg, *prate);
+}
+
+static int zx_audio_set_rate(struct clk_hw *hw, unsigned long rate,
+                            unsigned long parent_rate)
+{
+       struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
+       u32 reg;
+
+       reg = calc_reg(parent_rate, rate);
+       writel_relaxed(reg, zx_audio->reg_base);
+
+       return 0;
+}
+
+#define ZX_AUDIO_EN BIT(25)
+static int zx_audio_enable(struct clk_hw *hw)
+{
+       struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
+       u32 reg;
+
+       reg = readl_relaxed(zx_audio->reg_base);
+       writel_relaxed(reg & ~ZX_AUDIO_EN, zx_audio->reg_base);
+       return 0;
+}
+
+static void zx_audio_disable(struct clk_hw *hw)
+{
+       struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
+       u32 reg;
+
+       reg = readl_relaxed(zx_audio->reg_base);
+       writel_relaxed(reg | ZX_AUDIO_EN, zx_audio->reg_base);
+}
+
+static const struct clk_ops zx_audio_ops = {
+       .recalc_rate = zx_audio_recalc_rate,
+       .round_rate = zx_audio_round_rate,
+       .set_rate = zx_audio_set_rate,
+       .enable = zx_audio_enable,
+       .disable = zx_audio_disable,
+};
+
+struct clk *clk_register_zx_audio(const char *name,
+                                 const char * const parent_name,
+                                 unsigned long flags,
+                                 void __iomem *reg_base)
+{
+       struct clk_zx_audio *zx_audio;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       zx_audio = kzalloc(sizeof(*zx_audio), GFP_KERNEL);
+       if (!zx_audio)
+               return ERR_PTR(-ENOMEM);
+
+       init.name = name;
+       init.ops = &zx_audio_ops;
+       init.flags = flags;
+       init.parent_names = parent_name ? &parent_name : NULL;
+       init.num_parents = parent_name ? 1 : 0;
+
+       zx_audio->reg_base = reg_base;
+       zx_audio->hw.init = &init;
+
+       clk = clk_register(NULL, &zx_audio->hw);
+       if (IS_ERR(clk))
+               kfree(zx_audio);
+
+       return clk;
+}

diff --git a/drivers/clk/zte/clk.h b/drivers/clk/zte/clk.h
index 0914a82..65ae08b 100644 (file)
--- a/drivers/clk/zte/clk.h
+++ b/drivers/clk/zte/clk.h
@@ -29,4 +29,13 @@ struct clk_zx_pll {
 struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
        unsigned long flags, void __iomem *reg_base,
        const struct zx_pll_config *lookup_table, int count, spinlock_t *lock);
+
+struct clk_zx_audio {
+       struct clk_hw hw;
+       void __iomem *reg_base;
+};
+
+struct clk *clk_register_zx_audio(const char *name,
+                                 const char * const parent_name,
+                                 unsigned long flags, void __iomem *reg_base);
 #endif