staging: comedi: plx9052.h: document the CNTRL register

Add defines for the PLX 9052 CNTRL register defines and use them
instead of the magic numbers in the me4000 driver

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/comedi/drivers/me4000.c b/drivers/staging/comedi/drivers/me4000.c
index 371df1d..641e693 100644 (file)
--- a/drivers/staging/comedi/drivers/me4000.c
+++ b/drivers/staging/comedi/drivers/me4000.c
@@ -170,19 +170,6 @@ broken.
 #define ME4000_AO_DEMUX_ADJUST_VALUE           0x4c
 #define ME4000_AI_SAMPLE_COUNTER_REG           0xc0
 
-/*
- * PLX Register map and bit defines
- */
-#define PLX_ICR                                        0x50
-#define PLX_ICR_BIT_EEPROM_CLOCK_SET           (1 << 24)
-#define PLX_ICR_BIT_EEPROM_CHIP_SELECT         (1 << 25)
-#define PLX_ICR_BIT_EEPROM_WRITE               (1 << 26)
-#define PLX_ICR_BIT_EEPROM_READ                        (1 << 27)
-#define PLX_ICR_BIT_EEPROM_VALID               (1 << 28)
-#define PLX_ICR_MASK_EEPROM                    (0x1f << 24)
-
-#define EEPROM_DELAY                           1
-
 #define ME4000_AI_FIFO_COUNT                   2048
 
 #define ME4000_AI_MIN_TICKS                    66
@@ -382,9 +369,9 @@ static int xilinx_download(struct comedi_device *dev)
        outl(PLX9052_INTCSR_LI2POL, info->plx_regbase + PLX9052_INTCSR);
 
        /* Set /CS and /WRITE of the Xilinx */
-       value = inl(info->plx_regbase + PLX_ICR);
-       value |= 0x100;
-       outl(value, info->plx_regbase + PLX_ICR);
+       value = inl(info->plx_regbase + PLX9052_CNTRL);
+       value |= PLX9052_CNTRL_UIO2_DATA;
+       outl(value, info->plx_regbase + PLX9052_CNTRL);
 
        /* Init Xilinx with CS1 */
        inb(xilinx_iobase + 0xC8);
@@ -398,9 +385,9 @@ static int xilinx_download(struct comedi_device *dev)
        }
 
        /* Reset /CS and /WRITE of the Xilinx */
-       value = inl(info->plx_regbase + PLX_ICR);
-       value &= ~0x100;
-       outl(value, info->plx_regbase + PLX_ICR);
+       value = inl(info->plx_regbase + PLX9052_CNTRL);
+       value &= ~PLX9052_CNTRL_UIO2_DATA;
+       outl(value, info->plx_regbase + PLX9052_CNTRL);
        if (FIRMWARE_NOT_AVAILABLE) {
                dev_err(dev->class_dev,
                        "xilinx firmware unavailable due to licensing, aborting");
@@ -416,7 +403,7 @@ static int xilinx_download(struct comedi_device *dev)
                        udelay(10);
 
                        /* Check if BUSY flag is low */
-                       if (inl(info->plx_regbase + PLX_ICR) & 0x20) {
+                       if (inl(info->plx_regbase + PLX9052_CNTRL) & PLX9052_CNTRL_UIO1_DATA) {
                                dev_err(dev->class_dev,
                                        "Xilinx is still busy (idx = %d)\n",
                                        idx);
@@ -426,7 +413,7 @@ static int xilinx_download(struct comedi_device *dev)
        }
 
        /* If done flag is high download was successful */
-       if (inl(info->plx_regbase + PLX_ICR) & 0x4) {
+       if (inl(info->plx_regbase + PLX9052_CNTRL) & PLX9052_CNTRL_UIO0_DATA) {
        } else {
                dev_err(dev->class_dev, "DONE flag is not set\n");
                dev_err(dev->class_dev, "Download not successful\n");
@@ -434,9 +421,9 @@ static int xilinx_download(struct comedi_device *dev)
        }
 
        /* Set /CS and /WRITE */
-       value = inl(info->plx_regbase + PLX_ICR);
-       value |= 0x100;
-       outl(value, info->plx_regbase + PLX_ICR);
+       value = inl(info->plx_regbase + PLX9052_CNTRL);
+       value |= PLX9052_CNTRL_UIO2_DATA;
+       outl(value, info->plx_regbase + PLX9052_CNTRL);
 
        return 0;
 }
@@ -448,11 +435,11 @@ static void me4000_reset(struct comedi_device *dev)
        int chan;
 
        /* Make a hardware reset */
-       val = inl(info->plx_regbase + PLX_ICR);
-       val |= 0x40000000;
-       outl(val, info->plx_regbase + PLX_ICR);
-       val &= ~0x40000000;
-       outl(val , info->plx_regbase + PLX_ICR);
+       val = inl(info->plx_regbase + PLX9052_CNTRL);
+       val |= PLX9052_CNTRL_PCI_RESET;
+       outl(val, info->plx_regbase + PLX9052_CNTRL);
+       val &= ~PLX9052_CNTRL_PCI_RESET;
+       outl(val , info->plx_regbase + PLX9052_CNTRL);
 
        /* 0x8000 to the DACs means an output voltage of 0V */
        for (chan = 0; chan < 4; chan++)

diff --git a/drivers/staging/comedi/drivers/plx9052.h b/drivers/staging/comedi/drivers/plx9052.h
index ab93b0b..ff76fbb 100644 (file)
--- a/drivers/staging/comedi/drivers/plx9052.h
+++ b/drivers/staging/comedi/drivers/plx9052.h
@@ -44,4 +44,41 @@
 #define PLX9052_INTCSR_LI2CLRINT       (1 << 11) /* LI2 clear int */
 #define PLX9052_INTCSR_ISAMODE         (1 << 12) /* ISA interface mode */
 
+/*
+ * CNTRL - User I/O, Direct Slave Response, Serial EEPROM, and
+ * Initialization Control register
+ */
+#define PLX9052_CNTRL                  0x50
+#define PLX9052_CNTRL_WAITO            (1 << 0)  /* UIO0 or WAITO# select */
+#define PLX9052_CNTRL_UIO0_DIR         (1 << 1)  /* UIO0 direction */
+#define PLX9052_CNTRL_UIO0_DATA                (1 << 2)  /* UIO0 data */
+#define PLX9052_CNTRL_LLOCKO           (1 << 3)  /* UIO1 or LLOCKo# select */
+#define PLX9052_CNTRL_UIO1_DIR         (1 << 4)  /* UIO1 direction */
+#define PLX9052_CNTRL_UIO1_DATA                (1 << 5)  /* UIO1 data */
+#define PLX9052_CNTRL_CS2              (1 << 6)  /* UIO2 or CS2# select */
+#define PLX9052_CNTRL_UIO2_DIR         (1 << 7)  /* UIO2 direction */
+#define PLX9052_CNTRL_UIO2_DATA                (1 << 8)  /* UIO2 data */
+#define PLX9052_CNTRL_CS3              (1 << 9)  /* UIO3 or CS3# select */
+#define PLX9052_CNTRL_UIO3_DIR         (1 << 10) /* UIO3 direction */
+#define PLX9052_CNTRL_UIO3_DATA                (1 << 11) /* UIO3 data */
+#define PLX9052_CNTRL_PCIBAR01         (0 << 12) /* bar 0 (mem) and 1 (I/O) */
+#define PLX9052_CNTRL_PCIBAR0          (1 << 12) /* bar 0 (mem) only */
+#define PLX9052_CNTRL_PCIBAR1          (2 << 12) /* bar 1 (I/O) only */
+#define PLX9052_CNTRL_PCI2_1_FEATURES  (1 << 14) /* PCI r2.1 features enabled */
+#define PLX9052_CNTRL_PCI_R_W_FLUSH    (1 << 15) /* read w/write flush mode */
+#define PLX9052_CNTRL_PCI_R_NO_FLUSH   (1 << 16) /* read no flush mode */
+#define PLX9052_CNTRL_PCI_R_NO_WRITE   (1 << 17) /* read no write mode */
+#define PLX9052_CNTRL_PCI_W_RELEASE    (1 << 18) /* write release bus mode */
+#define PLX9052_CNTRL_RETRY_CLKS(x)    (((x) & 0xf) << 19) /* slave retry clks */
+#define PLX9052_CNTRL_LOCK_ENAB                (1 << 23) /* slave LOCK# enable */
+#define PLX9052_CNTRL_EEPROM_MASK      (0x1f << 24) /* EEPROM bits */
+#define PLX9052_CNTRL_EEPROM_CLK       (1 << 24) /* EEPROM clock */
+#define PLX9052_CNTRL_EEPROM_CS                (1 << 25) /* EEPROM chip select */
+#define PLX9052_CNTRL_EEPROM_DOUT      (1 << 26) /* EEPROM write bit */
+#define PLX9052_CNTRL_EEPROM_DIN       (1 << 27) /* EEPROM read bit */
+#define PLX9052_CNTRL_EEPROM_PRESENT   (1 << 28) /* EEPROM present */
+#define PLX9052_CNTRL_RELOAD_CFG       (1 << 29) /* reload configuration */
+#define PLX9052_CNTRL_PCI_RESET                (1 << 30) /* PCI adapter reset */
+#define PLX9052_CNTRL_MASK_REV         (1 << 31) /* mask revision */
+
 #endif /* _PLX9052_H_ */