This patch decouples radv_shader.h from any LLVM dependency.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
--- /dev/null
+/*
+ * Copyright © 2016 Red Hat.
+ * Copyright © 2016 Bas Nieuwenhuizen
+ *
+ * based in part on anv driver which is:
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef RADV_CONSTANTS_H
+#define RADV_CONSTANTS_H
+
+#define ATI_VENDOR_ID 0x1002
+
+#define MAX_VBS 32
+#define MAX_VERTEX_ATTRIBS 32
+#define MAX_RTS 8
+#define MAX_VIEWPORTS 16
+#define MAX_SCISSORS 16
+#define MAX_DISCARD_RECTANGLES 4
+#define MAX_SAMPLE_LOCATIONS 32
+#define MAX_PUSH_CONSTANTS_SIZE 128
+#define MAX_PUSH_DESCRIPTORS 32
+#define MAX_DYNAMIC_UNIFORM_BUFFERS 16
+#define MAX_DYNAMIC_STORAGE_BUFFERS 8
+#define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
+#define MAX_SAMPLES_LOG2 4
+#define NUM_META_FS_KEYS 12
+#define RADV_MAX_DRM_DEVICES 8
+#define MAX_VIEWS 8
+#define MAX_SO_STREAMS 4
+#define MAX_SO_BUFFERS 4
+#define MAX_SO_OUTPUTS 64
+#define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
+#define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
+
+#define NUM_DEPTH_CLEAR_PIPELINES 3
+
+/*
+ * This is the point we switch from using CP to compute shader
+ * for certain buffer operations.
+ */
+#define RADV_BUFFER_OPS_CS_THRESHOLD 4096
+
+#define RADV_BUFFER_UPDATE_THRESHOLD 1024
+
+/* descriptor index into scratch ring offsets */
+#define RING_SCRATCH 0
+#define RING_ESGS_VS 1
+#define RING_ESGS_GS 2
+#define RING_GSVS_VS 3
+#define RING_GSVS_GS 4
+#define RING_HS_TESS_FACTOR 5
+#define RING_HS_TESS_OFFCHIP 6
+#define RING_PS_SAMPLE_POSITIONS 7
+
+/* max number of descriptor sets */
+#define MAX_SETS 32
+
+#define RADV_NUM_PHYSICAL_VGPRS 256
+
+#endif /* RADV_CONSTANTS_H */
+
#ifndef RADV_DESCRIPTOR_SET_H
#define RADV_DESCRIPTOR_SET_H
-#include <vulkan/vulkan.h>
+#include "radv_constants.h"
-#define MAX_SETS 32
+#include <vulkan/vulkan.h>
struct radv_descriptor_set_binding_layout {
VkDescriptorType type;
LLVMContextRef context;
LLVMValueRef main_function;
- LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
+ LLVMValueRef descriptor_sets[MAX_SETS];
LLVMValueRef ring_offsets;
LLVMValueRef vertex_buffers;
for(int i = 0; i < shader_count; ++i)
radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
- for (i = 0; i < RADV_UD_MAX_SETS; i++)
+ for (i = 0; i < MAX_SETS; i++)
shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
for (i = 0; i < AC_UD_MAX_UD; i++)
shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
#include "ac_surface.h"
#include "ac_llvm_build.h"
#include "ac_llvm_util.h"
+#include "radv_constants.h"
#include "radv_descriptor_set.h"
#include "radv_extensions.h"
#include "sid.h"
#include "gfx10_format_table.h"
-#define ATI_VENDOR_ID 0x1002
-
-#define MAX_VBS 32
-#define MAX_VERTEX_ATTRIBS 32
-#define MAX_RTS 8
-#define MAX_VIEWPORTS 16
-#define MAX_SCISSORS 16
-#define MAX_DISCARD_RECTANGLES 4
-#define MAX_SAMPLE_LOCATIONS 32
-#define MAX_PUSH_CONSTANTS_SIZE 128
-#define MAX_PUSH_DESCRIPTORS 32
-#define MAX_DYNAMIC_UNIFORM_BUFFERS 16
-#define MAX_DYNAMIC_STORAGE_BUFFERS 8
-#define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
-#define MAX_SAMPLES_LOG2 4
-#define NUM_META_FS_KEYS 12
-#define RADV_MAX_DRM_DEVICES 8
-#define MAX_VIEWS 8
-#define MAX_SO_STREAMS 4
-#define MAX_SO_BUFFERS 4
-#define MAX_SO_OUTPUTS 64
-#define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
-#define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
-
-#define NUM_DEPTH_CLEAR_PIPELINES 3
-
-/*
- * This is the point we switch from using CP to compute shader
- * for certain buffer operations.
- */
-#define RADV_BUFFER_OPS_CS_THRESHOLD 4096
-
-#define RADV_BUFFER_UPDATE_THRESHOLD 1024
-
enum radv_mem_heap {
RADV_MEM_HEAP_VRAM,
RADV_MEM_HEAP_VRAM_CPU_ACCESS,
.use_interpolated_input_intrinsics = true,
};
+bool
+radv_can_dump_shader(struct radv_device *device,
+ struct radv_shader_module *module,
+ bool is_gs_copy_shader)
+{
+ if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
+ return false;
+
+ /* Only dump non-meta shaders, useful for debugging purposes. */
+ return (module && !module->nir) || is_gs_copy_shader;
+}
+
+bool
+radv_can_dump_shader_stats(struct radv_device *device,
+ struct radv_shader_module *module)
+{
+ /* Only dump non-meta shader stats. */
+ return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
+ module && !module->nir;
+}
+
+unsigned shader_io_get_unique_index(gl_varying_slot slot)
+{
+ /* handle patch indices separate */
+ if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
+ return 0;
+ if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
+ return 1;
+ if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
+ return 2 + (slot - VARYING_SLOT_PATCH0);
+ if (slot == VARYING_SLOT_POS)
+ return 0;
+ if (slot == VARYING_SLOT_PSIZ)
+ return 1;
+ if (slot == VARYING_SLOT_CLIP_DIST0)
+ return 2;
+ if (slot == VARYING_SLOT_CLIP_DIST1)
+ return 3;
+ /* 3 is reserved for clip dist as well */
+ if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
+ return 4 + (slot - VARYING_SLOT_VAR0);
+ unreachable("illegal slot in get unique index\n");
+}
+
VkResult radv_CreateShaderModule(
VkDevice _device,
const VkShaderModuleCreateInfo* pCreateInfo,
#ifndef RADV_SHADER_H
#define RADV_SHADER_H
-#include "radv_debug.h"
-#include "radv_private.h"
+#include "ac_binary.h"
+#include "amd_family.h"
+#include "radv_constants.h"
#include "nir/nir.h"
+#include "vulkan/vulkan.h"
-/* descriptor index into scratch ring offsets */
-#define RING_SCRATCH 0
-#define RING_ESGS_VS 1
-#define RING_ESGS_GS 2
-#define RING_GSVS_VS 3
-#define RING_GSVS_GS 4
-#define RING_HS_TESS_FACTOR 5
-#define RING_HS_TESS_OFFCHIP 6
-#define RING_PS_SAMPLE_POSITIONS 7
-
-// Match MAX_SETS from radv_descriptor_set.h
-#define RADV_UD_MAX_SETS MAX_SETS
-
-#define RADV_NUM_PHYSICAL_VGPRS 256
+struct radv_device;
struct radv_shader_module {
struct nir_shader *nir;
};
struct radv_userdata_locations {
- struct radv_userdata_info descriptor_sets[RADV_UD_MAX_SETS];
+ struct radv_userdata_info descriptor_sets[MAX_SETS];
struct radv_userdata_info shader_data[AC_UD_MAX_UD];
uint32_t descriptor_sets_enabled;
};
gl_shader_stage stage,
FILE *file);
-static inline bool
+bool
radv_can_dump_shader(struct radv_device *device,
struct radv_shader_module *module,
- bool is_gs_copy_shader)
-{
- if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
- return false;
+ bool is_gs_copy_shader);
- /* Only dump non-meta shaders, useful for debugging purposes. */
- return (module && !module->nir) || is_gs_copy_shader;
-}
-
-static inline bool
+bool
radv_can_dump_shader_stats(struct radv_device *device,
- struct radv_shader_module *module)
-{
- /* Only dump non-meta shader stats. */
- return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
- module && !module->nir;
-}
-
-static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
-{
- /* handle patch indices separate */
- if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
- return 0;
- if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
- return 1;
- if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
- return 2 + (slot - VARYING_SLOT_PATCH0);
- if (slot == VARYING_SLOT_POS)
- return 0;
- if (slot == VARYING_SLOT_PSIZ)
- return 1;
- if (slot == VARYING_SLOT_CLIP_DIST0)
- return 2;
- if (slot == VARYING_SLOT_CLIP_DIST1)
- return 3;
- /* 3 is reserved for clip dist as well */
- if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
- return 4 + (slot - VARYING_SLOT_VAR0);
- unreachable("illegal slot in get unique index\n");
-}
+ struct radv_shader_module *module);
+
+unsigned
+shader_io_get_unique_index(gl_varying_slot slot);
#endif
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