mpc83xx: Size optimization of start.S

Currently there are in excess of 100 bytes located at the beginning of the image
built by start.S that are not being utilized.  This patch moves a few functions
into this part of the image.  This will create a greater number of *available*
bytes that can be used by board specific code in NAND builds and will decrease
the size of the assembled code in other builds.

Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index 792b2c8..beebc99 100644 (file)
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -109,6 +109,45 @@ version_string:
        .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
        .ascii " ", CONFIG_IDENT_STRING, "\0"
 
+       .align 2
+
+       .globl enable_addr_trans
+enable_addr_trans:
+       /* enable address translation */
+       mfmsr   r5
+       ori     r5, r5, (MSR_IR | MSR_DR)
+       mtmsr   r5
+       isync
+       blr
+
+       .globl disable_addr_trans
+disable_addr_trans:
+       /* disable address translation */
+       mflr    r4
+       mfmsr   r3
+       andi.   r0, r3, (MSR_IR | MSR_DR)
+       beqlr
+       andc    r3, r3, r0
+       mtspr   SRR0, r4
+       mtspr   SRR1, r3
+       rfi
+
+       .globl get_pvr
+get_pvr:
+       mfspr   r3, PVR
+       blr
+
+       .globl  ppcDWstore
+ppcDWstore:
+       lfd     1, 0(r4)
+       stfd    1, 0(r3)
+       blr
+
+       .globl  ppcDWload
+ppcDWload:
+       lfd     1, 0(r3)
+       stfd    1, 0(r4)
+       blr
 
 #ifndef CONFIG_DEFAULT_IMMR
 #error CONFIG_DEFAULT_IMMR must be defined
@@ -698,27 +737,6 @@ setup_bats:
 
        blr
 
-       .globl enable_addr_trans
-enable_addr_trans:
-       /* enable address translation */
-       mfmsr   r5
-       ori     r5, r5, (MSR_IR | MSR_DR)
-       mtmsr   r5
-       isync
-       blr
-
-       .globl disable_addr_trans
-disable_addr_trans:
-       /* disable address translation */
-       mflr    r4
-       mfmsr   r3
-       andi.   r0, r3, (MSR_IR | MSR_DR)
-       beqlr
-       andc    r3, r3, r0
-       mtspr   SRR0, r4
-       mtspr   SRR1, r3
-       rfi
-
 /* Cache functions.
  *
  * Note: requires that all cache bits in
@@ -796,23 +814,6 @@ flush_dcache:
        b       1b
 2:     blr
 
-       .globl get_pvr
-get_pvr:
-       mfspr   r3, PVR
-       blr
-
-       .globl  ppcDWstore
-ppcDWstore:
-       lfd     1, 0(r4)
-       stfd    1, 0(r3)
-       blr
-
-       .globl  ppcDWload
-ppcDWload:
-       lfd     1, 0(r3)
-       stfd    1, 0(r4)
-       blr
-
 /*-------------------------------------------------------------------*/
 
 /*