Revert "fix(c9xx): don't flush dcache when invalidating"

This reverts commit adec30ace4cebb0554bb246b52eebaf37c1545c4.

diff --git a/arch/riscv/cpu/c9xx/cpu.c b/arch/riscv/cpu/c9xx/cpu.c
index a93a3060e04abc2916fe75752ccd027c73a2ef02..e5eaed943f1cf36f4a54c7d2ea547f86e31196af 100644 (file)
--- a/arch/riscv/cpu/c9xx/cpu.c
+++ b/arch/riscv/cpu/c9xx/cpu.c
@@ -104,6 +104,16 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
 {
        register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
 
+       for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+               asm volatile(".long 0x02b5000b");  /* dcache.cipa a0 */
+
+       sync_is();
+}
+
+void invalid_dcache_range(unsigned long start, unsigned long end)
+{
+       register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+
        for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
                asm volatile(".long 0x02a5000b");  /* dcache.ipa a0 */
 

diff --git a/cmd/ddrscan.c b/cmd/ddrscan.c
index c550e03d31fdb6e1d411a95d7d80b4f15ea025a6..0f2b78c680b5741471f4d641de3111851854beb0 100644 (file)
--- a/cmd/ddrscan.c
+++ b/cmd/ddrscan.c
@@ -73,6 +73,7 @@ extern ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr,
 #endif
 extern void flush_dcache_range(unsigned long start, unsigned long end);
 extern void invalidate_dcache_range(unsigned long start, unsigned long end);
+extern void invalid_dcache_range(unsigned long start, unsigned long end);
 
 #ifdef CONFIG_CMD_MEMTEST
 int test_stuck_address(ulv *bufa, ulong count);

diff --git a/cmd/prbs.c b/cmd/prbs.c
index 594711697d2ff72d209b4f81e1fe670719a35ba9..2bbb68cfea6a28b439602636e5674d9c9bce02a7 100644 (file)
--- a/cmd/prbs.c
+++ b/cmd/prbs.c
@@ -50,6 +50,7 @@ u64 t_end;
 
 extern void flush_dcache_range(unsigned long start, unsigned long end);
 extern void invalidate_dcache_range(unsigned long start, unsigned long end);
+extern void invalid_dcache_range(unsigned long start, unsigned long end);
 
 extern unsigned long get_ddr_density(void);
 extern int riscv_get_time(u64 *time);
@@ -304,7 +305,7 @@ int prbs_test(struct PRBS_ELE *prbs, unsigned int *buf, int pos, bool random_dq,
     // compare result
     // invalid cache before read
     mdelay(100);
-    invalidate_dcache_range((ulong)buf, (ulong)buf+(bit_len*4*2*2));
+    invalid_dcache_range((ulong)buf, (ulong)buf+(bit_len*4*2*2));
     p1 = buf;
     bit_cnt = 0;
     for (i = 0; i < bit_len; i++) {

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 349e2bc172c99f2059409bc7ea168122159b57e6..5cc70cda5f74bdbc1579e33c6d236d777e97cb00 100644 (file)
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -247,9 +247,10 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
                }
        } while (!(stat & SDHCI_INT_DATA_END));
 #ifdef CONFIG_TARGET_LIGHT_C910        
+       extern void invalid_dcache_range(unsigned long start, unsigned long end);
        /*After read ,invalid dcache range again to avoid cache filled during read tranfer*/
        if(data->flags == MMC_DATA_READ){
-               invalidate_dcache_range(host->start_addr,host->start_addr+ROUND(data->blocks*data->blocksize, ARCH_DMA_MINALIGN));
+               invalid_dcache_range(host->start_addr,host->start_addr+ROUND(data->blocks*data->blocksize, ARCH_DMA_MINALIGN));
        }
 #endif
        return 0;

diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 1e07bdf817dc4dc3cf0c7b38231f147db786f34e..ea21f36d28eace5a3cb56034f30aa1ffed20dbc8 100644 (file)
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -906,7 +906,8 @@ static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
        dep->resource_index = 0;
        dwc->setup_packet_pending = false;
 #ifdef CONFIG_TARGET_LIGHT_C910
-       invalidate_dcache_range((unsigned long)dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
+       extern void invalid_dcache_range(unsigned long start, unsigned long end);
+       invalid_dcache_range((unsigned long)dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
 #endif
 
        switch (dwc->ep0state) {