drm/radeon: make vm_block_size a module parameter

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 5e0a41a..e4b2f2b 100644 (file)
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5446,7 +5446,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
               (u32)(rdev->dummy_page.addr >> 12));
        WREG32(VM_CONTEXT1_CNTL2, 4);
        WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
-                               PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) |
+                               PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
                                RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
                                RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
                                DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |

diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 8c3fbb1..c0fd8f6 100644 (file)
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1268,7 +1268,7 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
               (u32)(rdev->dummy_page.addr >> 12));
        WREG32(VM_CONTEXT1_CNTL2, 4);
        WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
-                               PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) |
+                               PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
                                RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
                                RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
                                DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 6f32f16..dd77111 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -101,6 +101,7 @@ extern int radeon_aspm;
 extern int radeon_runtime_pm;
 extern int radeon_hard_reset;
 extern int radeon_vm_size;
+extern int radeon_vm_block_size;
 
 /*
  * Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -838,13 +839,8 @@ struct radeon_mec {
 /* maximum number of VMIDs */
 #define RADEON_NUM_VM  16
 
-/* defines number of bits in page table versus page directory,
- * a page is 4KB so we have 12 bits offset, 9 bits in the page
- * table and the remaining 19 bits are in the page directory */
-#define RADEON_VM_BLOCK_SIZE   9
-
 /* number of entries in page table */
-#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
+#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
 
 /* PTBs (Page Table Blocks) need to be aligned to 32K */
 #define RADEON_VM_PTB_ALIGN_SIZE   32768

diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 3f1e306..03686fa 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1073,6 +1073,22 @@ static void radeon_check_arguments(struct radeon_device *rdev)
                         radeon_vm_size);
                radeon_vm_size = 4096;
        }
+
+       /* defines number of bits in page table versus page directory,
+        * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
+        * page table and the remaining bits are in the page directory */
+       if (radeon_vm_block_size < 9) {
+               dev_warn(rdev->dev, "VM page table size (%d) to small\n",
+                        radeon_vm_block_size);
+               radeon_vm_block_size = 9;
+       }
+
+       if (radeon_vm_block_size > 24 ||
+           radeon_vm_size < (1ull << radeon_vm_block_size)) {
+               dev_warn(rdev->dev, "VM page table size (%d) to large\n",
+                        radeon_vm_block_size);
+               radeon_vm_block_size = 9;
+       }
 }
 
 /**

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index a09426c..b7a2ec2 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -173,6 +173,7 @@ int radeon_aspm = -1;
 int radeon_runtime_pm = -1;
 int radeon_hard_reset = 0;
 int radeon_vm_size = 4096;
+int radeon_vm_block_size = 9;
 
 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
 module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -243,6 +244,9 @@ module_param_named(hard_reset, radeon_hard_reset, int, 0444);
 MODULE_PARM_DESC(vm_size, "VM address space size in megabytes (default 4GB)");
 module_param_named(vm_size, radeon_vm_size, int, 0444);
 
+MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)");
+module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
+
 static struct pci_device_id pciidlist[] = {
        radeon_PCI_IDS
 };

diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c
index d3c9161..899d912 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -59,7 +59,7 @@
  */
 static unsigned radeon_vm_num_pdes(struct radeon_device *rdev)
 {
-       return rdev->vm_manager.max_pfn >> RADEON_VM_BLOCK_SIZE;
+       return rdev->vm_manager.max_pfn >> radeon_vm_block_size;
 }
 
 /**
@@ -474,8 +474,10 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
        bo_va->valid = false;
        list_move(&bo_va->vm_list, head);
 
-       soffset = (soffset / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE;
-       eoffset = (eoffset / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE;
+       soffset = (soffset / RADEON_GPU_PAGE_SIZE) >> radeon_vm_block_size;
+       eoffset = (eoffset / RADEON_GPU_PAGE_SIZE) >> radeon_vm_block_size;
+
+       BUG_ON(eoffset >= radeon_vm_num_pdes(rdev));
 
        if (eoffset > vm->max_pde_used)
                vm->max_pde_used = eoffset;
@@ -583,10 +585,9 @@ static uint32_t radeon_vm_page_flags(uint32_t flags)
 int radeon_vm_update_page_directory(struct radeon_device *rdev,
                                    struct radeon_vm *vm)
 {
-       static const uint32_t incr = RADEON_VM_PTE_COUNT * 8;
-
        struct radeon_bo *pd = vm->page_directory;
        uint64_t pd_addr = radeon_bo_gpu_offset(pd);
+       uint32_t incr = RADEON_VM_PTE_COUNT * 8;
        uint64_t last_pde = ~0, last_pt = ~0;
        unsigned count = 0, pt_idx, ndw;
        struct radeon_ib ib;
@@ -757,8 +758,7 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev,
                                  uint64_t start, uint64_t end,
                                  uint64_t dst, uint32_t flags)
 {
-       static const uint64_t mask = RADEON_VM_PTE_COUNT - 1;
-
+       uint64_t mask = RADEON_VM_PTE_COUNT - 1;
        uint64_t last_pte = ~0, last_dst = ~0;
        unsigned count = 0;
        uint64_t addr;
@@ -768,7 +768,7 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev,
 
        /* walk over the address space and update the page tables */
        for (addr = start; addr < end; ) {
-               uint64_t pt_idx = addr >> RADEON_VM_BLOCK_SIZE;
+               uint64_t pt_idx = addr >> radeon_vm_block_size;
                struct radeon_bo *pt = vm->page_tables[pt_idx].bo;
                unsigned nptes;
                uint64_t pte;
@@ -873,13 +873,13 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
        /* padding, etc. */
        ndw = 64;
 
-       if (RADEON_VM_BLOCK_SIZE > 11)
+       if (radeon_vm_block_size > 11)
                /* reserve space for one header for every 2k dwords */
                ndw += (nptes >> 11) * 4;
        else
                /* reserve space for one header for
                    every (1 << BLOCK_SIZE) entries */
-               ndw += (nptes >> RADEON_VM_BLOCK_SIZE) * 4;
+               ndw += (nptes >> radeon_vm_block_size) * 4;
 
        /* reserve space for pte addresses */
        ndw += nptes * 2;

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 85d030e..ec13e8d 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -4095,7 +4095,7 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
               (u32)(rdev->dummy_page.addr >> 12));
        WREG32(VM_CONTEXT1_CNTL2, 4);
        WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
-                               PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) |
+                               PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
                                RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
                                RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
                                DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |