2005-05-08 Nathan Sidwell <nathan@codesourcery.com>
+ * config/frv/frv.c (frv_default_flags_for_cpu): Use gcc_assert and
+ gcc_unreachable, as appropriate.
+ (frv_function_prologue, frv_alloc_temp_reg,
+ frv_initial_elimination_offset, frv_expand_block_move,
+ frv_expand_block_clear, frv_print_operand_jump_hint,
+ frv_legitimize_tls_address, unspec_got_name, frv_emit_move,
+ frv_emit_movsi, frv_split_cond_move, frv_split_minmax,
+ frv_ifcvt_modify_insn, frv_ifcvt_modify_final,
+ frv_adjust_field_align, frv_insn_unit, frv_cond_flags,
+ frv_sort_insn_group, frv_reorder_packet, frv_matching_accg_mode,
+ frv_in_small_data_p, frv_asm_out_constructor,
+ frv_asm_out_destructor, frv_output_dwarf_dtprel): Likewise.
+ * config/frv/frv.md (reload_incc_fp, *cond_exec_si_binary1,
+ *cond_exec_si_binary2, *cond_exec_si_divide, *cond_exec_si_unary1,
+ *cond_exec_sf_conv, *cond_exec_sf_add, call, sibcall, call_value,
+ sibcall_value, casesi): Likewise.
+
* config/mn10300/mn10300.c (print_operand): Use gcc_assert and
gcc_unreachable as appropriate.
(print_operand_address, mn10300_print_reg_list, expand_prologue,
case FRV_CPU_FR300:
case FRV_CPU_SIMPLE:
return MASK_DEFAULT_SIMPLE;
+
+ default:
+ gcc_unreachable ();
}
- abort ();
}
/* Sometimes certain combinations of command options do not make
rtx insn;
/* Just to check that the above comment is true. */
- if (regs_ever_live[GPR_FIRST + 3])
- abort ();
+ gcc_assert (!regs_ever_live[GPR_FIRST + 3]);
/* Generate the instruction that saves the link register. */
fprintf (file, "\tmovsg lr,gr3\n");
regno = 0;
if (regno == orig_regno)
{
- if (no_abort)
- return NULL_RTX;
- else
- abort ();
+ gcc_assert (no_abort);
+ return NULL_RTX;
}
}
- info->pretend_size);
else
- abort ();
+ gcc_unreachable ();
if (TARGET_DEBUG_STACK)
fprintf (stderr, "Eliminate %s to %s by adding %d\n",
if (! constp)
return FALSE;
- /* If this is not a fixed size alignment, abort. */
- if (GET_CODE (align_rtx) != CONST_INT)
- abort ();
+ /* This should be a fixed size alignment. */
+ gcc_assert (GET_CODE (align_rtx) == CONST_INT);
align = INTVAL (align_rtx);
if (! constp)
return FALSE;
- /* If this is not a fixed size alignment, abort. */
- if (GET_CODE (align_rtx) != CONST_INT)
- abort ();
+ /* This should be a fixed size alignment. */
+ gcc_assert (GET_CODE (align_rtx) == CONST_INT);
align = INTVAL (align_rtx);
HOST_WIDE_INT prob = -1;
enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
- if (GET_CODE (insn) != JUMP_INSN)
- abort ();
+ gcc_assert (GET_CODE (insn) == JUMP_INSN);
/* Assume any non-conditional jump is likely. */
if (! any_condjump_p (insn))
break;
}
default:
- abort ();
+ gcc_unreachable ();
}
return dest;
case R_FRV_TLSDESCLO: return "tlsdesclo";
case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
- default: abort ();
+ default: gcc_unreachable ();
}
}
break;
default:
- abort ();
+ gcc_unreachable ();
}
emit_insn (gen_rtx_SET (VOIDmode, dest, src));
/* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
new uses of it once reload has begun. */
- if (reload_in_progress || reload_completed)
- abort ();
+ gcc_assert (!reload_in_progress && !reload_completed);
switch (unspec)
{
}
else
- abort ();
+ gcc_unreachable ();
}
else
{
switch (GET_CODE (minmax))
{
default:
- abort ();
+ gcc_unreachable ();
case SMIN: test_code = LT; break;
case SMAX: test_code = GT; break;
then do a conditional move of the other value. */
if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
{
- if (rtx_equal_p (dest, src1))
- abort ();
+ gcc_assert (!rtx_equal_p (dest, src1));
emit_move_insn (dest, src2);
emit_insn (gen_rtx_COND_EXEC (VOIDmode,
rtx op1;
rtx test;
- if (GET_CODE (pattern) != COND_EXEC)
- abort ();
+ gcc_assert (GET_CODE (pattern) == COND_EXEC);
test = COND_EXEC_TEST (pattern);
if (GET_CODE (test) == AND)
/* Loop inserting the check insns. The last check insn is the first test,
and is the appropriate place to insert constants. */
- if (! p)
- abort ();
+ gcc_assert (p);
do
{
prev = cur;
}
- if (!cur)
- abort ();
+ gcc_assert (cur);
/* If this isn't a :0 field and if the previous element is a bitfield
also, see if the type is different, if so, we will need to align the
if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
break;
- if (unit == ARRAY_SIZE (frv_unit_codes))
- abort ();
+ gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
frv_type_to_unit[type] = unit;
}
static int
frv_cond_flags (rtx cond)
{
- if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
- && GET_CODE (XEXP (cond, 0)) == REG
- && CR_P (REGNO (XEXP (cond, 0)))
- && XEXP (cond, 1) == const0_rtx)
- return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
- | (GET_CODE (cond) == NE
- ? REGSTATE_IF_TRUE
- : REGSTATE_IF_FALSE));
- abort ();
+ gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
+ && GET_CODE (XEXP (cond, 0)) == REG
+ && CR_P (REGNO (XEXP (cond, 0)))
+ && XEXP (cond, 1) == const0_rtx);
+ return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
+ | (GET_CODE (cond) == NE
+ ? REGSTATE_IF_TRUE
+ : REGSTATE_IF_FALSE));
}
return;
}
}
- abort ();
+ gcc_unreachable ();
}
\f
/* Sort the current packet into assembly-language order. Set packing
if (cursor[group] < packet_group->num_insns)
{
/* frv_reorg should have added nops for us. */
- if (packet_group->sorted[cursor[group]] == packet_group->nop)
- abort ();
+ gcc_assert (packet_group->sorted[cursor[group]]
+ != packet_group->nop);
insns[to++] = packet_group->sorted[cursor[group]++];
}
}
- if (to != frv_packet.num_insns)
- abort ();
+ gcc_assert (to == frv_packet.num_insns);
/* Clear the last instruction's packing flag, thus marking the end of
a packet. Reorder the other instructions relative to it. */
return QImode;
default:
- abort ();
+ gcc_unreachable ();
}
}
section_name = DECL_SECTION_NAME (decl);
if (section_name)
{
- if (TREE_CODE (section_name) != STRING_CST)
- abort ();
+ gcc_assert (TREE_CODE (section_name) == STRING_CST);
if (frv_string_begins_with (section_name, ".sdata"))
return true;
if (frv_string_begins_with (section_name, ".sbss"))
assemble_align (POINTER_SIZE);
if (TARGET_FDPIC)
{
- if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
- abort ();
+ int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
+
+ gcc_assert (ok);
return;
}
assemble_integer_with_op ("\t.picptr\t", symbol);
assemble_align (POINTER_SIZE);
if (TARGET_FDPIC)
{
- if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
- abort ();
+ int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
+
+ gcc_assert (ok);
return;
}
assemble_integer_with_op ("\t.picptr\t", symbol);
void
frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
{
- if (size != 4)
- abort ();
+ gcc_assert (size == 4);
fputs ("\t.picptr\ttlsmoff(", file);
/* We want the unbiased TLS offset, so add the bias to the
expression, such that the implicit biasing cancels out. */
rtx addr;
rtx temp3 = simplify_gen_subreg (SImode, operands[2], TImode, 12);
- if (GET_CODE (operands[1]) != MEM)
- abort ();
+ gcc_assert (GET_CODE (operands[1]) == MEM);
addr = XEXP (operands[1], 0);
- if (GET_CODE (addr) != PLUS)
- abort ();
+ gcc_assert (GET_CODE (addr) == PLUS);
emit_move_insn (temp3, XEXP (addr, 1));
case ASHIFT: return \"csll %4, %z5, %2, %1, %e0\";
case ASHIFTRT: return \"csra %4, %z5, %2, %1, %e0\";
case LSHIFTRT: return \"csrl %4, %z5, %2, %1, %e0\";
- default: abort ();
+ default: gcc_unreachable ();
}
}"
[(set_attr "length" "4")
case AND: return \"cmand %4, %5, %2, %1, %e0\";
case IOR: return \"cmor %4, %5, %2, %1, %e0\";
case XOR: return \"cmxor %4, %5, %2, %1, %e0\";
- default: abort ();
+ default: gcc_unreachable ();
}
}"
[(set_attr "length" "4")
{
case DIV: return \"csdiv %4, %z5, %2, %1, %e0\";
case UDIV: return \"cudiv %4, %z5, %2, %1, %e0\";
- default: abort ();
+ default: gcc_unreachable ();
}
}"
[(set_attr "length" "4")
{
case NOT: return \"cnot %4, %2, %1, %e0\";
case NEG: return \"csub %., %4, %2, %1, %e0\";
- default: abort ();
+ default: gcc_unreachable ();
}
}"
[(set_attr "length" "4")
{
case ABS: return \"cfabss %4, %2, %1, %e0\";
case NEG: return \"cfnegs %4, %2, %1, %e0\";
- default: abort ();
+ default: gcc_unreachable ();
}
}"
[(set_attr "length" "4")
{
case PLUS: return \"cfadds %4, %5, %2, %1, %e0\";
case MINUS: return \"cfsubs %4, %5, %2, %1, %e0\";
- default: abort ();
+ default: gcc_unreachable ();
}
}"
[(set_attr "length" "4")
rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
rtx addr;
- if (GET_CODE (operands[0]) != MEM)
- abort ();
+ gcc_assert (GET_CODE (operands[0]) == MEM);
addr = XEXP (operands[0], 0);
if (! call_operand (addr, Pmode))
{
rtx addr;
- if (GET_CODE (operands[0]) != MEM)
- abort ();
+ gcc_assert (GET_CODE (operands[0]) == MEM);
addr = XEXP (operands[0], 0);
if (! sibcall_operand (addr, Pmode))
rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
rtx addr;
- if (GET_CODE (operands[1]) != MEM)
- abort ();
+ gcc_assert (GET_CODE (operands[1]) == MEM);
addr = XEXP (operands[1], 0);
if (! call_operand (addr, Pmode))
{
rtx addr;
- if (GET_CODE (operands[1]) != MEM)
- abort ();
+ gcc_assert (GET_CODE (operands[1]) == MEM);
addr = XEXP (operands[1], 0);
if (! sibcall_operand (addr, Pmode))
rtx reg2;
rtx reg3;
- if (GET_CODE (operands[1]) != CONST_INT)
- abort ();
+ gcc_assert (GET_CODE (operands[1]) == CONST_INT);
- if (GET_CODE (operands[2]) != CONST_INT)
- abort ();
+ gcc_assert (GET_CODE (operands[2]) == CONST_INT);
/* If we can't generate an immediate instruction, promote to register. */
if (! IN_RANGE_P (INTVAL (range), -2048, 2047))
projects / platform / upstream / gcc.git / commitdiff