return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
case VK_DYNAMIC_STATE_FRAGMENT_SHADING_RATE_KHR:
return RADV_DYNAMIC_FRAGMENT_SHADING_RATE;
+ case VK_DYNAMIC_STATE_PATCH_CONTROL_POINTS_EXT:
+ return RADV_DYNAMIC_PATCH_CONTROL_POINTS;
+ case VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE_EXT:
+ return RADV_DYNAMIC_RASTERIZER_DISCARD_ENABLE;
+ case VK_DYNAMIC_STATE_DEPTH_BIAS_ENABLE_EXT:
+ return RADV_DYNAMIC_DEPTH_BIAS_ENABLE;
+ case VK_DYNAMIC_STATE_LOGIC_OP_EXT:
+ return RADV_DYNAMIC_LOGIC_OP;
+ case VK_DYNAMIC_STATE_PRIMITIVE_RESTART_ENABLE_EXT:
+ return RADV_DYNAMIC_PRIMITIVE_RESTART_ENABLE;
default:
unreachable("Unhandled dynamic state");
}
RADV_DYNAMIC_STENCIL_OP = 1ull << 20,
RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1ull << 21,
RADV_DYNAMIC_FRAGMENT_SHADING_RATE = 1ull << 22,
- RADV_DYNAMIC_ALL = (1ull << 23) - 1,
+ RADV_DYNAMIC_PATCH_CONTROL_POINTS = 1ull << 23,
+ RADV_DYNAMIC_RASTERIZER_DISCARD_ENABLE = 1ull << 24,
+ RADV_DYNAMIC_DEPTH_BIAS_ENABLE = 1ull << 25,
+ RADV_DYNAMIC_LOGIC_OP = 1ull << 26,
+ RADV_DYNAMIC_PRIMITIVE_RESTART_ENABLE = 1ull << 27,
+ RADV_DYNAMIC_ALL = (1ull << 28) - 1,
};
enum radv_cmd_dirty_bits {
RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1ull << 20,
RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1ull << 21,
RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE = 1ull << 22,
- RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 23) - 1,
- RADV_CMD_DIRTY_PIPELINE = 1ull << 23,
- RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 24,
- RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 25,
- RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 26,
- RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 27,
+ RADV_CMD_DIRTY_DYNAMIC_PATCH_CONTROL_POINTS = 1ull << 23,
+ RADV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE = 1ull << 24,
+ RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE = 1ull << 25,
+ RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP = 1ull << 26,
+ RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE = 1ull << 27,
+ RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 28) - 1,
+ RADV_CMD_DIRTY_PIPELINE = 1ull << 28,
+ RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 29,
+ RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 30,
+ RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 31,
+ RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 32,
};
enum radv_cmd_flush_bits {