static int mv88e6171_switch_reset(struct dsa_switch *ds)
{
+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
int i;
int ret;
unsigned long timeout;
/* Set all ports to the disabled state. */
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < ps->num_ports; i++) {
ret = REG_READ(REG_PORT(i), 0x04);
REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
}
return -ETIMEDOUT;
/* Enable ports not under DSA, e.g. WAN port */
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < ps->num_ports; i++) {
if (dsa_is_cpu_port(ds, i) || ds->phys_port_mask & (1 << i))
continue;
static int mv88e6171_setup_global(struct dsa_switch *ds)
{
+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
int ret;
int i;
}
/* Clear all trunk masks. */
- for (i = 0; i < 8; i++)
+ for (i = 0; i < ps->num_ports; i++)
REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff);
/* Clear all trunk mappings. */
static int mv88e6171_setup(struct dsa_switch *ds)
{
+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
int i;
int ret;
if (ret < 0)
return ret;
+ ps->num_ports = 7;
+
ret = mv88e6171_switch_reset(ds);
if (ret < 0)
return ret;
if (ret < 0)
return ret;
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < ps->num_ports; i++) {
if (!(dsa_is_cpu_port(ds, i) || ds->phys_port_mask & (1 << i)))
continue;
return 0;
}
-static int mv88e6171_port_to_phy_addr(int port)
+static int mv88e6171_port_to_phy_addr(struct dsa_switch *ds, int port)
{
- if (port >= 0 && port <= 4)
+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
+
+ if (port >= 0 && port < ps->num_ports)
return port;
return -1;
}
mv88e6171_phy_read(struct dsa_switch *ds, int port, int regnum)
{
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
- int addr = mv88e6171_port_to_phy_addr(port);
+ int addr = mv88e6171_port_to_phy_addr(ds, port);
int ret;
mutex_lock(&ps->phy_mutex);
int port, int regnum, u16 val)
{
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
- int addr = mv88e6171_port_to_phy_addr(port);
+ int addr = mv88e6171_port_to_phy_addr(ds, port);
int ret;
mutex_lock(&ps->phy_mutex);
static int mv88e6352_switch_reset(struct dsa_switch *ds)
{
+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
unsigned long timeout;
int ret;
int i;
/* Set all ports to the disabled state. */
- for (i = 0; i < 7; i++) {
+ for (i = 0; i < ps->num_ports; i++) {
ret = REG_READ(REG_PORT(i), 0x04);
REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
}
static int mv88e6352_setup_global(struct dsa_switch *ds)
{
+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
int ret;
int i;
/* Disable ingress rate limiting by resetting all ingress
* rate limit registers to their initial state.
*/
- for (i = 0; i < 7; i++)
+ for (i = 0; i < ps->num_ports; i++)
REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));
/* Initialise cross-chip port VLAN table to reset defaults. */
if (ret < 0)
return ret;
+ ps->num_ports = 7;
+
mutex_init(&ps->eeprom_mutex);
ret = mv88e6352_switch_reset(ds);
if (ret < 0)
return ret;
- for (i = 0; i < 7; i++) {
+ for (i = 0; i < ps->num_ports; i++) {
ret = mv88e6352_setup_port(ds, i);
if (ret < 0)
return ret;