+2010-10-21 Paul Koning <ni1d@arrl.net>
+
+ * config/pdp11/pdp11-protos.md (arith_operand,
+ const_immediate_operand, expand_shift_operand,
+ immediate15_operand): Delete
+ * config/pdp11/pdp11.c: Ditto.
+ * config/pdp11/pdp11.h (REG_CLASS_FROM_LETTER,
+ CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P,
+ EXTRA_CONSTRAINT): Delete.
+ * config/pdp11/pdp11.md (various): Use standard constraints
+ instead of removed ones.
+ * config/pdp11/constraints.md: New file.
+ * config/pdp11/predicates.md: New file.
+
2010-10-21 Bingfeng Mei <bmei@broadcom.com>
PR c/45834
--- /dev/null
+;;- Constraint definitions for the pdp11 for GNU C compiler
+;; Copyright (C) 2010 Free Software Foundation, Inc.
+;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_register_constraint "f" "FPU_REGS"
+ "Any FPU register")
+
+(define_register_constraint "a" "LOAD_FPU_REGS"
+ "FPU register that can be directly loaded from memory")
+
+(define_register_constraint "d" "MUL_REGS"
+ "General register that can be used for 16-bit multiply (odd numbered)")
+
+(define_constraint "I"
+ "Integer constant that fits in 16 bits unsigned"
+ (and (match_code "const_int")
+ (match_test "(ival & 0xffff0000) == 0")))
+
+(define_constraint "J"
+ "Integer constant whose low 16 bits are zero"
+ (and (match_code "const_int")
+ (match_test "(ival & 0xffff) == 0")))
+
+(define_constraint "K"
+ "Integer constant whose lower and upper 16 bit half are both non-zero"
+ (and (match_code "const_int")
+ (match_test "(ival & 0xffff) != 0 && (ival & 0xffff0000) != 0")))
+
+(define_constraint "L"
+ "Integer constant 1"
+ (and (match_code "const_int")
+ (match_test "ival == 1")))
+
+(define_constraint "M"
+ "Integer constant -1"
+ (and (match_code "const_int")
+ (match_test "ival == -1")))
+
+(define_constraint "N"
+ "Integer constant 0"
+ (and (match_code "const_int")
+ (match_test "ival == 0")))
+
+(define_constraint "O"
+ "Integer constant for which several individual shifts are better than one big one"
+ (and (match_code "const_int")
+ (match_test "abs (ival) > 1 && abs (ival) <= 4")))
+
+(define_constraint "G"
+ "Defines a real zero constant."
+ (and (match_code "const_double")
+ (match_test "op == CONST0_RTX (GET_MODE (op))")))
+
+(define_constraint "Q"
+ "Memory reference that requires an additional word after the opcode"
+ (and (match_code "mem")
+ (match_test "memory_address_p (GET_MODE (op), XEXP (op, 0))
+ && !simple_memory_operand (op, GET_MODE (op))")))
+
+(define_constraint "R"
+ "Memory reference that is encoded within the opcode"
+ (and (match_code "mem")
+ (match_test "memory_address_p (GET_MODE (op), XEXP (op, 0))
+ && simple_memory_operand (op, GET_MODE (op))")))
+
/* declarations */
#ifdef RTX_CODE
-extern int arith_operand (rtx, enum machine_mode);
-extern int const_immediate_operand (rtx, enum machine_mode);
-extern int expand_shift_operand (rtx, enum machine_mode);
-extern int immediate15_operand (rtx, enum machine_mode);
extern int simple_memory_operand (rtx, enum machine_mode);
extern int legitimate_const_double_p (rtx);
opts->x_flag_signaling_nans = 0;
}
-/* Nonzero if OP is a valid second operand for an arithmetic insn. */
-
-int
-arith_operand (rtx op, enum machine_mode mode)
-{
- return (register_operand (op, mode) || GET_CODE (op) == CONST_INT);
-}
-
-int
-const_immediate_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return (GET_CODE (op) == CONST_INT);
-}
-
-int
-immediate15_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return (GET_CODE (op) == CONST_INT && ((INTVAL (op) & 0x8000) == 0x0000));
-}
-
-int
-expand_shift_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return (GET_CODE (op) == CONST_INT
- && abs (INTVAL(op)) > 1
- && abs (INTVAL(op)) <= 4);
-}
-
/*
stream is a stdio stream to output the code to.
size is an int: how many units of temporary storage to allocate.
#define INDEX_REG_CLASS GENERAL_REGS
#define BASE_REG_CLASS GENERAL_REGS
-/* Get reg_class from a letter such as appears in the machine description. */
-
-#define REG_CLASS_FROM_LETTER(C) \
-((C) == 'f' ? FPU_REGS : \
- ((C) == 'd' ? MUL_REGS : \
- ((C) == 'a' ? LOAD_FPU_REGS : NO_REGS)))
-
-
-/* The letters I, J, K, L and M in a register constraint string
- can be used to stand for particular ranges of immediate operands.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C.
-
- I bits 31-16 0000
- J bits 15-00 0000
- K completely random 32 bit
- L,M,N -1,1,0 respectively
- O where doing shifts in sequence is faster than
- one big shift
-*/
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? ((VALUE) & 0xffff0000) == 0 \
- : (C) == 'J' ? ((VALUE) & 0x0000ffff) == 0 \
- : (C) == 'K' ? (((VALUE) & 0xffff0000) != 0 \
- && ((VALUE) & 0x0000ffff) != 0) \
- : (C) == 'L' ? ((VALUE) == 1) \
- : (C) == 'M' ? ((VALUE) == -1) \
- : (C) == 'N' ? ((VALUE) == 0) \
- : (C) == 'O' ? (abs(VALUE) >1 && abs(VALUE) <= 4) \
- : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
- Here VALUE is the CONST_DOUBLE rtx itself. */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'G' && XINT (VALUE, 0) == 0 && XINT (VALUE, 1) == 0)
-
-
-/* Letters in the range `Q' through `U' may be defined in a
- machine-dependent fashion to stand for arbitrary operand types.
- The machine description macro `EXTRA_CONSTRAINT' is passed the
- operand as its first argument and the constraint letter as its
- second operand.
-
- `Q' is for memory references that require an extra word after the opcode.
- `R' is for memory references which are encoded within the opcode. */
-
-#define EXTRA_CONSTRAINT(OP,CODE) \
- ((GET_CODE (OP) != MEM) ? 0 \
- : !memory_address_p (GET_MODE (OP), XEXP (OP, 0)) ? 0 \
- : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \
- : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
- : 0)
-
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
In general this is just CLASS; but on some machines
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-;; Match CONST_DOUBLE zero for tstd/tstf.
-(define_predicate "register_or_const0_operand"
- (ior (match_operand 0 "register_operand")
- (match_test "op == CONST0_RTX (GET_MODE (op))")))
+(include "predicates.md")
+(include "constraints.md")
;; HI is 16 bit
(define_expand "movmemhi"
[(parallel [(set (match_operand:BLK 0 "general_operand" "=g,g")
(match_operand:BLK 1 "general_operand" "g,g"))
- (use (match_operand:HI 2 "arith_operand" "n,&mr"))
+ (use (match_operand:HI 2 "general_operand" "n,&mr"))
(use (match_operand:HI 3 "immediate_operand" "i,i"))
(clobber (match_scratch:HI 4 "=&r,X"))
(clobber (match_dup 5))
(define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(xor:SI (match_operand:SI 1 "register_operand" "%0")
- (match_operand:SI 2 "arith_operand" "r")))]
+ (match_operand:SI 2 "register_operand" "r")))]
"TARGET_40_PLUS"
"*
{ /* Here we trust that operands don't overlap */
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=r,o")
(ashift:QI (match_operand:QI 1 "general_operand" "0,0")
- (match_operand:HI 2 "const_immediate_operand" "n,n")))]
+ (match_operand:HI 2 "const_int_operand" "n,n")))]
""
"*
{ /* allowing predec or post_inc is possible, but hairy! */
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=r,o")
(ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0")
- (match_operand:HI 2 "const_immediate_operand" "n,n")))]
+ (match_operand:HI 2 "const_int_operand" "n,n")))]
""
"*
{ /* allowing predec or post_inc is possible, but hairy! */
;;(define_insn "lshrsi3"
;; [(set (match_operand:HI 0 "register_operand" "=r")
;; (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
-;; (match_operand:HI 2 "arith_operand" "rI")))]
+;; (match_operand:HI 2 "general_operand" "rI")))]
;; ""
;; "srl %0,%2")
--- /dev/null
+;;- Predicate definitions for the pdp11 for GNU C compiler
+;; Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2004, 2005
+;; 2007, 2008, 2010 Free Software Foundation, Inc.
+;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Match CONST_DOUBLE zero for tstd/tstf.
+(define_predicate "register_or_const0_operand"
+ (ior (match_operand 0 "register_operand")
+ (match_test "op == CONST0_RTX (GET_MODE (op))")))
+
+;; Accept integer arguments in the range -4..-2 and 2..4, which are the
+;; shift counts for which we unroll a shift. This matches the rule for
+;; the "O" constraint.
+(define_predicate "expand_shift_operand"
+ (match_code "const_int")
+{
+ int sh;
+
+ sh = INTVAL (op);
+ return (abs (sh) > 1 && abs (sh) <= 4);
+})
projects / platform / upstream / linaro-gcc.git / commitdiff