(V2DI "wa,v,r,0,0")
(V2DF "wa,v,r,0,0")
(V1TI "wa,v,r,0,0")])
-
-;; Mode attribute for the clobber of CC0 for AND expansion.
-;; For the 128-bit types, we never do AND immediate, but we need to
-;; get the correct number of X's for the number of operands.
-(define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")
- (PTI "X,X,X")
- (V16QI "X,X,X,X,X")
- (V8HI "X,X,X,X,X")
- (V4SI "X,X,X,X,X")
- (V4SF "X,X,X,X,X")
- (V2DI "X,X,X,X,X")
- (V2DF "X,X,X,X,X")
- (V1TI "X,X,X,X,X")])
\f
;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later.
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
{
- rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
+ rs6000_split_logical (operands, NOT, false, false, false);
DONE;
}
})
(define_expand "ctz<mode>2"
[(set (match_dup 2)
(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
- (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
- (match_dup 2)))
- (clobber (scratch:CC))])
- (set (match_dup 4) (clz:GPR (match_dup 3)))
+ (set (match_dup 3)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 4)
+ (clz:GPR (match_dup 3)))
(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (minus:GPR (match_dup 5) (match_dup 4)))]
+ (minus:GPR (match_dup 5)
+ (match_dup 4)))]
""
{
operands[2] = gen_reg_rtx (<MODE>mode);
(define_expand "ffs<mode>2"
[(set (match_dup 2)
(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
- (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
- (match_dup 2)))
- (clobber (scratch:CC))])
- (set (match_dup 4) (clz:GPR (match_dup 3)))
+ (set (match_dup 3)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 4)
+ (clz:GPR (match_dup 3)))
(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (minus:GPR (match_dup 5) (match_dup 4)))]
+ (minus:GPR (match_dup 5)
+ (match_dup 4)))]
""
{
operands[2] = gen_reg_rtx (<MODE>mode);
;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
;; those rotate-and-mask operations. Thus, the AND insns come first.
-(define_expand "andsi3"
- [(parallel
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "and_operand" "")))
- (clobber (match_scratch:CC 3 ""))])]
+(define_expand "and<mode>3"
+ [(set (match_operand:SDI 0 "gpc_reg_operand" "")
+ (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
+ (match_operand:SDI 2 "reg_or_cint_operand" "")))]
""
- "")
-
-(define_insn "andsi3_mc"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
- (match_operand:SI 2 "and_operand" "?r,T,K,L")))
- (clobber (match_scratch:CC 3 "=X,X,x,x"))]
- "rs6000_gen_cell_microcode"
- "@
- and %0,%1,%2
- rlwinm %0,%1,0,%m2,%M2
- andi. %0,%1,%b2
- andis. %0,%1,%u2"
- [(set_attr "type" "*,shift,logical,logical")
- (set_attr "dot" "no,no,yes,yes")])
+{
+ if (<MODE>mode == DImode && !TARGET_POWERPC64)
+ {
+ rs6000_split_logical (operands, AND, false, false, false);
+ DONE;
+ }
-(define_insn "andsi3_nomc"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "and_operand" "?r,T")))
- (clobber (match_scratch:CC 3 "=X,X"))]
- "!rs6000_gen_cell_microcode"
- "@
- and %0,%1,%2
- rlwinm %0,%1,0,%m2,%M2"
- [(set_attr "type" "logical,shift")])
+ if (logical_const_operand (operands[2], <MODE>mode)
+ && !any_mask_operand (operands[2], <MODE>mode))
+ {
+ emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
+ DONE;
+ }
-(define_insn "andsi3_internal0_nomc"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "and_operand" "?r,T")))]
- "!rs6000_gen_cell_microcode"
- "@
- and %0,%1,%2
- rlwinm %0,%1,0,%m2,%M2"
- [(set_attr "type" "logical,shift")])
+ if ((<MODE>mode == DImode && !and64_2_operand (operands[2], <MODE>mode))
+ || (<MODE>mode != DImode && !and_operand (operands[2], <MODE>mode)))
+ operands[2] = force_reg (<MODE>mode, operands[2]);
+})
-;; Note to set cr's other than cr0 we do the and immediate and then
-;; the test again -- this avoids a mfcr which on the higher end
-;; machines causes an execution serialization
+(define_insn "*and<mode>3"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r")))]
+ ""
+ "and %0,%1,%2"
+ [(set_attr "type" "logical")])
-(define_insn "*andsi3_internal2_mc"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
+(define_insn_and_split "*and<mode>3_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
- (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
- "TARGET_32BIT && rs6000_gen_cell_microcode"
+ (clobber (match_scratch:GPR 0 "=r,r"))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- and. %3,%1,%2
- andi. %3,%1,%b2
- andis. %3,%1,%u2
- rlwinm. %3,%1,0,%m2,%M2
- #
- #
- #
+ and. %0,%1,%2
#"
- [(set_attr "type" "logical,logical,logical,shift,\
- compare,compare,compare,compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "logical")
(set_attr "dot" "yes")
- (set_attr "length" "4,4,4,4,8,8,8,8")])
+ (set_attr "length" "4,8")])
-(define_insn "*andsi3_internal3_mc"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
+(define_insn_and_split "*and<mode>3_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
- (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
- "TARGET_64BIT && rs6000_gen_cell_microcode"
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (and:GPR (match_dup 1)
+ (match_dup 2)))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- #
- andi. %3,%1,%b2
- andis. %3,%1,%u2
- rlwinm. %3,%1,0,%m2,%M2
- #
- #
- #
+ and. %0,%1,%2
#"
- [(set_attr "type" "compare,logical,logical,shift,compare,\
- compare,compare,compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "logical")
(set_attr "dot" "yes")
- (set_attr "length" "8,4,4,4,8,8,8,8")])
+ (set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "and_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:GPR 3 ""))
- (clobber (match_scratch:CC 4 ""))]
- "reload_completed"
- [(parallel [(set (match_dup 3)
- (and:<MODE> (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
-;; whole 64 bit reg, and we don't know what is in the high 32 bits.
+(define_insn "and<mode>3_imm"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
+ (match_operand:GPR 2 "logical_const_operand" "n")))
+ (clobber (match_scratch:CC 3 "=x"))]
+ "rs6000_gen_cell_microcode
+ && !any_mask_operand (operands[2], <MODE>mode)"
+ "andi%e2. %0,%1,%u2"
+ [(set_attr "type" "logical")
+ (set_attr "dot" "yes")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_operand" "")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
+(define_insn_and_split "*and<mode>3_imm_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+ (match_operand:GPR 2 "logical_const_operand" "n,n"))
(const_int 0)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:CC 4 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(parallel [(set (match_dup 3)
- (and:SI (match_dup 1)
- (match_dup 2)))
+ (clobber (match_scratch:GPR 0 "=r,r"))
+ (clobber (match_scratch:CC 4 "=X,x"))]
+ "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
+ && rs6000_gen_cell_microcode"
+ "@
+ andi%e2. %0,%1,%u2
+ #"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(parallel [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
(clobber (match_dup 4))])
- (set (match_dup 0)
- (compare:CC (match_dup 3)
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "logical")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_insn "*andsi3_internal4"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
+(define_insn_and_split "*and<mode>3_imm_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+ (match_operand:GPR 2 "logical_const_operand" "n,n"))
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
- "TARGET_32BIT && rs6000_gen_cell_microcode"
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_scratch:CC 4 "=X,x"))]
+ "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
+ && rs6000_gen_cell_microcode"
"@
- and. %0,%1,%2
- andi. %0,%1,%b2
- andis. %0,%1,%u2
- rlwinm. %0,%1,0,%m2,%M2
- #
- #
- #
+ andi%e2. %0,%1,%u2
#"
- [(set_attr "type" "logical,logical,logical,shift,\
- compare,compare,compare,compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(parallel [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 4))])
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "logical")
(set_attr "dot" "yes")
- (set_attr "length" "4,4,4,4,8,8,8,8")])
+ (set_attr "length" "4,8")])
-(define_insn "*andsi3_internal5_mc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
+
+(define_insn "*and<mode>3_mask"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+ (match_operand:GPR 2 "any_mask_operand" "S,T")))]
+ ""
+ "@
+ rldic%B2 %0,%1,0,%S2
+ rlwinm %0,%1,0,%m2,%M2"
+ [(set_attr "type" "shift")])
+
+(define_insn_and_split "*and<mode>3_mask_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
+ (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
- "TARGET_64BIT && rs6000_gen_cell_microcode"
+ (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
+ "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
+ && rs6000_gen_cell_microcode
+ && !logical_const_operand (operands[2], <MODE>mode)"
"@
- #
- andi. %0,%1,%b2
- andis. %0,%1,%u2
+ rldic%B2. %0,%1,0,%S2
rlwinm. %0,%1,0,%m2,%M2
#
- #
- #
#"
- [(set_attr "type" "compare,logical,logical,shift,compare,\
- compare,compare,compare")
- (set_attr "dot" "yes")
- (set_attr "length" "8,4,4,4,8,8,8,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "and_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:CC 4 ""))]
- "reload_completed"
- [(parallel [(set (match_dup 0)
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 4))])
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,4,8,8")])
-(define_split
- [(set (match_operand:CC 3 "cc_reg_operand" "")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
+(define_insn_and_split "*and<mode>3_mask_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
+ (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:CC 4 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(parallel [(set (match_dup 0)
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 4))])
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
+ (and:GPR (match_dup 1)
+ (match_dup 2)))]
+ "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
+ && rs6000_gen_cell_microcode
+ && !logical_const_operand (operands[2], <MODE>mode)"
+ "@
+ rldic%B2. %0,%1,0,%S2
+ rlwinm. %0,%1,0,%m2,%M2
+ #
+ #"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,4,8,8")])
+
+
+
+(define_insn "andsi3_internal0_nomc"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:SI 2 "and_operand" "?r,T")))]
+ "!rs6000_gen_cell_microcode"
+ "@
+ and %0,%1,%2
+ rlwinm %0,%1,0,%m2,%M2"
+ [(set_attr "type" "logical,shift")])
+
;; Handle the PowerPC64 rlwinm corner case
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
{
- rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);
+ rs6000_split_logical (operands, IOR, false, false, false);
DONE;
}
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
{
- rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);
+ rs6000_split_logical (operands, XOR, false, false, false);
DONE;
}
(define_expand "floatdisf2_internal2"
[(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
(const_int 53)))
- (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
- (const_int 2047)))
- (clobber (scratch:CC))])
+ (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
+ (const_int 2047)))
(set (match_dup 3) (plus:DI (match_dup 3)
(const_int 1)))
(set (match_dup 0) (plus:DI (match_dup 0)
(const_int 2)))
(set (match_dup 0) (ior:DI (match_dup 0)
(match_dup 1)))
- (parallel [(set (match_dup 0) (and:DI (match_dup 0)
- (const_int -2048)))
- (clobber (scratch:CC))])
+ (set (match_dup 0) (and:DI (match_dup 0)
+ (const_int -2048)))
(set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
(label_ref (match_operand:DI 2 "" ""))
(pc)))
(const_int 0)))]
"")
-(define_expand "anddi3"
- [(parallel
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")))
- (clobber (match_scratch:CC 3 ""))])]
- ""
-{
- if (!TARGET_POWERPC64)
- {
- rtx cc = gen_rtx_SCRATCH (CCmode);
- rs6000_split_logical (operands, AND, false, false, false, cc);
- DONE;
- }
- else if (!and64_2_operand (operands[2], DImode))
- operands[2] = force_reg (DImode, operands[2]);
-})
-
-(define_insn "anddi3_mc"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
- (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
- (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
- (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
- "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
- "@
- and %0,%1,%2
- rldic%B2 %0,%1,0,%S2
- rlwinm %0,%1,0,%m2,%M2
- andi. %0,%1,%b2
- andis. %0,%1,%u2
- #"
- [(set_attr "type" "*,shift,shift,logical,logical,*")
- (set_attr "dot" "no,no,no,yes,yes,no")
- (set_attr "length" "4,4,4,4,4,8")])
-
-(define_insn "anddi3_nomc"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
- (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
- (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
- (clobber (match_scratch:CC 3 "=X,X,X,X"))]
- "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
- "@
- and %0,%1,%2
- rldic%B2 %0,%1,0,%S2
- rlwinm %0,%1,0,%m2,%M2
- #"
- [(set_attr "type" "*,shift,shift,*")
- (set_attr "length" "4,4,4,8")])
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "mask64_2_operand" "")))
- (clobber (match_scratch:CC 3 ""))]
- "TARGET_POWERPC64
- && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
- && !mask_operand (operands[2], DImode)
- && !mask64_operand (operands[2], DImode)"
+(define_insn_and_split "*anddi3_2rld"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+ (match_operand:DI 2 "and_2rld_operand" "n")))]
+ "TARGET_POWERPC64"
+ "#"
+ ""
[(set (match_dup 0)
(and:DI (rotate:DI (match_dup 1)
(match_dup 4))
(match_dup 7)))]
{
build_mask64_2_operands (operands[2], &operands[4]);
-})
+}
+ [(set_attr "length" "8")])
-(define_insn "*anddi3_internal2_mc"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
- (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
- (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
+(define_insn_and_split "*anddi3_2rld_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:DI 2 "and_2rld_operand" "n,n"))
(const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
- (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
+ (clobber (match_scratch:DI 0 "=r,r"))]
"TARGET_64BIT && rs6000_gen_cell_microcode"
"@
- and. %3,%1,%2
- rldic%B2. %3,%1,0,%S2
- rlwinm. %3,%1,0,%m2,%M2
- andi. %3,%1,%b2
- andis. %3,%1,%u2
- #
- #
- #
- #
- #
#
#"
- [(set_attr "type" "logical,shift,shift,logical,\
- logical,compare,compare,compare,compare,compare,\
- compare,compare")
- (set_attr "dot" "yes")
- (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_operand" "")
- (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "mask64_2_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))
- (clobber (match_scratch:CC 4 ""))]
- "TARGET_64BIT && reload_completed
- && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
- && !mask_operand (operands[2], DImode)
- && !mask64_operand (operands[2], DImode)"
- [(set (match_dup 3)
+ "&& reload_completed"
+ [(set (match_dup 0)
(and:DI (rotate:DI (match_dup 1)
- (match_dup 5))
- (match_dup 6)))
- (parallel [(set (match_dup 0)
- (compare:CC (and:DI (rotate:DI (match_dup 3)
- (match_dup 7))
- (match_dup 8))
+ (match_dup 4))
+ (match_dup 5)))
+ (parallel [(set (match_dup 3)
+ (compare:CC (and:DI (rotate:DI (match_dup 0)
+ (match_dup 6))
+ (match_dup 7))
(const_int 0)))
- (clobber (match_dup 3))])]
- "
+ (clobber (match_dup 0))])]
{
- build_mask64_2_operands (operands[2], &operands[5]);
-}")
+ build_mask64_2_operands (operands[2], &operands[4]);
+}
+ [(set_attr "type" "compare")
+ (set_attr "dot" "yes")
+ (set_attr "length" "8,12")])
-(define_insn "*anddi3_internal3_mc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
- (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
- (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
+(define_insn_and_split "*anddi3_2rld_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:DI 2 "and_2rld_operand" "n,n"))
(const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
- (and:DI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (and:DI (match_dup 1)
+ (match_dup 2)))]
"TARGET_64BIT && rs6000_gen_cell_microcode"
"@
- and. %0,%1,%2
- rldic%B2. %0,%1,0,%S2
- rlwinm. %0,%1,0,%m2,%M2
- andi. %0,%1,%b2
- andis. %0,%1,%u2
- #
- #
- #
- #
- #
#
#"
- [(set_attr "type" "logical,shift,shift,logical,\
- logical,compare,compare,compare,compare,compare,\
- compare,compare")
- (set_attr "dot" "yes")
- (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "and64_2_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:CC 4 ""))]
- "TARGET_64BIT && reload_completed"
- [(parallel [(set (match_dup 0)
- (and:DI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_operand" "")
- (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "mask64_2_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:CC 4 ""))]
- "TARGET_64BIT && reload_completed
- && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
- && !mask_operand (operands[2], DImode)
- && !mask64_operand (operands[2], DImode)"
+ "&& reload_completed"
[(set (match_dup 0)
(and:DI (rotate:DI (match_dup 1)
- (match_dup 5))
- (match_dup 6)))
+ (match_dup 4))
+ (match_dup 5)))
(parallel [(set (match_dup 3)
(compare:CC (and:DI (rotate:DI (match_dup 0)
- (match_dup 7))
- (match_dup 8))
+ (match_dup 6))
+ (match_dup 7))
(const_int 0)))
(set (match_dup 0)
(and:DI (rotate:DI (match_dup 0)
- (match_dup 7))
- (match_dup 8)))])]
- "
+ (match_dup 6))
+ (match_dup 7)))])]
{
- build_mask64_2_operands (operands[2], &operands[5]);
-}")
+ build_mask64_2_operands (operands[2], &operands[4]);
+}
+ [(set_attr "type" "compare")
+ (set_attr "dot" "yes")
+ (set_attr "length" "8,12")])
\f
;; 128-bit logical operations expanders
(define_expand "and<mode>3"
- [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
- (and:BOOL_128
- (match_operand:BOOL_128 1 "vlogical_operand" "")
- (match_operand:BOOL_128 2 "vlogical_operand" "")))
- (clobber (match_scratch:CC 3 ""))])]
+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
+ (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
+ (match_operand:BOOL_128 2 "vlogical_operand" "")))]
""
"")
[(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
(and:BOOL_128
(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
- (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))
- (clobber (match_scratch:CC 3 "<BOOL_REGS_AND_CR0>"))]
+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))]
""
{
if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
"reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, AND, false, false, false, operands[3]);
+ rs6000_split_logical (operands, AND, false, false, false);
DONE;
}
[(set (attr "type")
"reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false,
- NULL_RTX);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false);
DONE;
}
[(set (attr "type")
&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
- NULL_RTX);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
DONE;
}
[(set (attr "type")
"reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
- NULL_RTX);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
DONE;
}
[(set_attr "type" "integer")
&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
- NULL_RTX);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
DONE;
}
[(set (attr "type")
"reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
- NULL_RTX);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
DONE;
}
[(set_attr "type" "integer")
&& int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
+ rs6000_split_logical (operands, XOR, true, false, false);
DONE;
}
[(set (attr "type")
"reload_completed && !TARGET_P8_VECTOR"
[(const_int 0)]
{
- rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
+ rs6000_split_logical (operands, XOR, true, false, false);
DONE;
}
[(set_attr "type" "integer")
"reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
+ rs6000_split_logical (operands, NOT, false, false, false);
DONE;
}
[(set (attr "type")