ARM: EXYNOS: Add clock register addresses for EXYNOS4X12 bus devfreq driver

EXYNOS4212/4412 memory bus devfreq driver requires some register
addresses that were not defined with EXYNOS4210 support.
This patch adds the required register addresses and shift/mask data.

Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index b1a2aeb..1e4abd6 100644 (file)
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -77,6 +77,7 @@
 #define EXYNOS4_CLKDIV2_RATIO                  EXYNOS_CLKREG(0x0C580)
 
 #define EXYNOS4_CLKDIV_STAT_TOP                        EXYNOS_CLKREG(0x0C610)
+#define EXYNOS4_CLKDIV_STAT_MFC                        EXYNOS_CLKREG(0x0C628)
 
 #define EXYNOS4_CLKGATE_SCLKCAM                        EXYNOS_CLKREG(0x0C820)
 #define EXYNOS4_CLKGATE_IP_CAM                 EXYNOS_CLKREG(0x0C920)
@@ -104,8 +105,12 @@
 #define EXYNOS4_CLKDIV_DMC0                    EXYNOS_CLKREG(0x10500)
 #define EXYNOS4_CLKDIV_DMC1                    EXYNOS_CLKREG(0x10504)
 #define EXYNOS4_CLKDIV_STAT_DMC0               EXYNOS_CLKREG(0x10600)
+#define EXYNOS4_CLKDIV_STAT_DMC1               EXYNOS_CLKREG(0x10604)
 #define EXYNOS4_CLKGATE_IP_DMC                 EXYNOS_CLKREG(0x10900)
 
+#define EXYNOS4_DMC_PAUSE_CTRL                 EXYNOS_CLKREG(0x11094)
+#define EXYNOS4_DMC_PAUSE_ENABLE               (1 << 0)
+
 #define EXYNOS4_APLL_LOCK                      EXYNOS_CLKREG(0x14000)
 #define EXYNOS4_MPLL_LOCK                      (soc_is_exynos4210() ? \
                                                EXYNOS_CLKREG(0x14004) :  \
@@ -187,6 +192,22 @@
 #define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT       (28)
 #define EXYNOS4_CLKDIV_DMC0_CORETI_MASK                (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
 
+#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT      (0)
+#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK       (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT          (4)
+#define EXYNOS4_CLKDIV_DMC1_C2C_MASK           (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT          (8)
+#define EXYNOS4_CLKDIV_DMC1_PWI_MASK           (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT      (12)
+#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK       (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT                (16)
+#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK         (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT          (24)
+#define EXYNOS4_CLKDIV_DMC1_DPM_MASK           (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
+
+#define EXYNOS4_CLKDIV_MFC_SHIFT               (0)
+#define EXYNOS4_CLKDIV_MFC_MASK                        (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
+
 #define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT       (0)
 #define EXYNOS4_CLKDIV_TOP_ACLK200_MASK                (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
 #define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT       (4)
@@ -197,12 +218,25 @@
 #define EXYNOS4_CLKDIV_TOP_ACLK133_MASK                (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
 #define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT       (16)
 #define EXYNOS4_CLKDIV_TOP_ONENAND_MASK                (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT   (20)
+#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK    (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT        (24)
+#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
 
 #define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT          (0)
 #define EXYNOS4_CLKDIV_BUS_GDLR_MASK           (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
 #define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT          (4)
 #define EXYNOS4_CLKDIV_BUS_GPLR_MASK           (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
 
+#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT         (0)
+#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK          (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT         (4)
+#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK          (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT         (8)
+#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK          (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT         (12)
+#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK          (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
+
 /* Only for EXYNOS4210 */
 
 #define EXYNOS4210_CLKSRC_LCD1                 EXYNOS_CLKREG(0x0C238)
@@ -210,6 +244,15 @@
 #define EXYNOS4210_CLKDIV_LCD1                 EXYNOS_CLKREG(0x0C538)
 #define EXYNOS4210_CLKGATE_IP_LCD1             EXYNOS_CLKREG(0x0C938)
 
+/* Only for EXYNOS4212 */
+
+#define EXYNOS4_CLKDIV_CAM1                    EXYNOS_CLKREG(0x0C568)
+
+#define EXYNOS4_CLKDIV_STAT_CAM1               EXYNOS_CLKREG(0x0C668)
+
+#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT         (0)
+#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK          (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
+
 /* Compatibility defines and inclusion */
 
 #include <mach/regs-pmu.h>