[
- {
- "BriefDescription": "Early Branch Prediciton Unit clears",
- "Counter": "0,1,2,3",
- "EventCode": "0xE8",
- "EventName": "BPU_CLEARS.EARLY",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Late Branch Prediction Unit clears",
- "Counter": "0,1,2,3",
- "EventCode": "0xE8",
- "EventName": "BPU_CLEARS.LATE",
- "SampleAfterValue": "2000000",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Branch prediction unit missed call or return",
- "Counter": "0,1,2,3",
- "EventCode": "0xE5",
- "EventName": "BPU_MISSED_CALL_RET",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
{
"BriefDescription": "ES segment renames",
"Counter": "0,1,2,3",
"SampleAfterValue": "200000",
"UMask": "0x1"
},
- {
- "BriefDescription": "All RAT stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.ANY",
- "SampleAfterValue": "2000000",
- "UMask": "0xf"
- },
- {
- "BriefDescription": "Flag stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.FLAGS",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Partial register stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.REGISTERS",
- "SampleAfterValue": "2000000",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "ROB read port stalls cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.ROB_READ_PORT",
- "SampleAfterValue": "2000000",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "Scoreboard stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.SCOREBOARD",
- "SampleAfterValue": "2000000",
- "UMask": "0x8"
- },
{
"BriefDescription": "All Store buffer stall cycles",
"Counter": "0,1,2,3",
"SampleAfterValue": "2000000",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Early Branch Prediciton Unit clears",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE8",
+ "EventName": "BPU_CLEARS.EARLY",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Late Branch Prediction Unit clears",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE8",
+ "EventName": "BPU_CLEARS.LATE",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Branch prediction unit missed call or return",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE5",
+ "EventName": "BPU_MISSED_CALL_RET",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Branch instructions decoded",
"Counter": "0,1,2,3",
"SampleAfterValue": "20000",
"UMask": "0x4"
},
+ {
+ "BriefDescription": "All RAT stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.ANY",
+ "SampleAfterValue": "2000000",
+ "UMask": "0xf"
+ },
+ {
+ "BriefDescription": "Flag stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.FLAGS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Partial register stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.REGISTERS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "ROB read port stalls cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.ROB_READ_PORT",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "Scoreboard stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.SCOREBOARD",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x8"
+ },
{
"BriefDescription": "Resource related stall cycles",
"Counter": "0,1,2,3",
"SampleAfterValue": "2000000",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]