[AMDGPU] Add a bit more gfx90a test coverage

Update the GlobalISel version of llvm.amdgcn.workitem.id.ll to mostly
match the SelctionDAG version.

Differential Revision: https://reviews.llvm.org/D97377

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
index 860b86b..ece9304 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
@@ -4,6 +4,7 @@
 ; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=ALL,MESA %s
 ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=+flat-for-global -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2 %s
+; RUN: llc -global-isel -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,PACKED-TID %s
 
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 declare i32 @llvm.amdgcn.workitem.id.y() #0
@@ -17,7 +18,9 @@ declare i32 @llvm.amdgcn.workitem.id.z() #0
 ; CO-V2: enable_vgpr_workitem_id = 0
 
 ; ALL-NOT: v0
-; ALL: {{buffer|flat}}_store_dword {{.*}}v0
+; ALL: {{buffer|flat|global}}_store_dword {{.*}}v0
+
+; PACKED-TID: .amdhsa_system_vgpr_workitem_id 0
 define amdgpu_kernel void @test_workitem_id_x(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workitem.id.x()
   store i32 %id, i32 addrspace(1)* %out
@@ -30,9 +33,13 @@ define amdgpu_kernel void @test_workitem_id_x(i32 addrspace(1)* %out) #1 {
 
 ; ALL-LABEL: {{^}}test_workitem_id_y:
 ; CO-V2: enable_vgpr_workitem_id = 1
+; CO-V2-NOT: v1
+; CO-V2: {{buffer|flat}}_store_dword {{.*}}v1
 
-; ALL-NOT: v1
-; ALL: {{buffer|flat}}_store_dword {{.*}}v1
+; PACKED-TID: v_lshrrev_b32_e32 [[ID:v[0-9]+]], 10, v0
+; PACKED-TID: v_and_b32_e32 [[ID]], 0x3ff, [[ID]]
+; PACKED-TID: {{buffer|flat|global}}_store_dword {{.*}}[[ID]]
+; PACKED-TID: .amdhsa_system_vgpr_workitem_id 1
 define amdgpu_kernel void @test_workitem_id_y(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workitem.id.y()
   store i32 %id, i32 addrspace(1)* %out
@@ -45,9 +52,13 @@ define amdgpu_kernel void @test_workitem_id_y(i32 addrspace(1)* %out) #1 {
 
 ; ALL-LABEL: {{^}}test_workitem_id_z:
 ; CO-V2: enable_vgpr_workitem_id = 2
+; CO-V2-NOT: v2
+; CO-V2: {{buffer|flat}}_store_dword {{.*}}v2
 
-; ALL-NOT: v2
-; ALL: {{buffer|flat}}_store_dword {{.*}}v2
+; PACKED-TID: v_lshrrev_b32_e32 [[ID:v[0-9]+]], 20, v0
+; PACKED-TID: v_and_b32_e32 [[ID]], 0x3ff, [[ID]]
+; PACKED-TID: {{buffer|flat|global}}_store_dword {{.*}}[[ID]]
+; PACKED-TID: .amdhsa_system_vgpr_workitem_id 2
 define amdgpu_kernel void @test_workitem_id_z(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workitem.id.z()
   store i32 %id, i32 addrspace(1)* %out
@@ -56,9 +67,9 @@ define amdgpu_kernel void @test_workitem_id_z(i32 addrspace(1)* %out) #1 {
 
 ; ALL-LABEL: {{^}}test_workitem_id_x_usex2:
 ; ALL-NOT: v0
-; ALL: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
+; ALL: {{flat|global}}_store_dword v{{.*}}, v0
 ; ALL-NOT: v0
-; ALL: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
+; ALL: {{flat|global}}_store_dword v{{.*}}, v0
 define amdgpu_kernel void @test_workitem_id_x_usex2(i32 addrspace(1)* %out) #1 {
   %id0 = call i32 @llvm.amdgcn.workitem.id.x()
   store volatile i32 %id0, i32 addrspace(1)* %out
@@ -70,9 +81,9 @@ define amdgpu_kernel void @test_workitem_id_x_usex2(i32 addrspace(1)* %out) #1 {
 
 ; ALL-LABEL: {{^}}test_workitem_id_x_use_outside_entry:
 ; ALL-NOT: v0
-; ALL: flat_store_dword
+; ALL: {{flat|global}}_store_dword
 ; ALL-NOT: v0
-; ALL: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
+; ALL: {{flat|global}}_store_dword v{{.*}}, v0
 define amdgpu_kernel void @test_workitem_id_x_use_outside_entry(i32 addrspace(1)* %out, i32 %arg) #1 {
 bb0:
   store volatile i32 0, i32 addrspace(1)* %out