drm/i915/pvc: add initial Ponte Vecchio definitions
authorStuart Summers <stuart.summers@intel.com>
Mon, 2 May 2022 16:34:07 +0000 (09:34 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Tue, 3 May 2022 17:34:36 +0000 (10:34 -0700)
Additional blitter and media engines will be enabled later.

Bspec: 44481, 44482
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220502163417.2635462-2-matthew.d.roper@intel.com
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_pci.c
drivers/gpu/drm/i915/intel_device_info.c
drivers/gpu/drm/i915/intel_device_info.h

index a6cf9716d6aa97bb12609763e595c8cc14517543..3ed9021c615d2e60228c1810e03ca8e1e17fff56 100644 (file)
@@ -1059,6 +1059,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
 #define IS_DG2(dev_priv)       IS_PLATFORM(dev_priv, INTEL_DG2)
+#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
+
 #define IS_DG2_G10(dev_priv) \
        IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 #define IS_DG2_G11(dev_priv) \
index 2efd2201359eaae8c969d4b3850ebcaf5f870244..987bdeb090a51c574eb3d05581eaa3252954c858 100644 (file)
@@ -1076,6 +1076,27 @@ static const struct intel_device_info ats_m_info = {
        .require_force_probe = 1,
 };
 
+#define XE_HPC_FEATURES \
+       XE_HP_FEATURES, \
+       .dma_mask_size = 52
+
+__maybe_unused
+static const struct intel_device_info pvc_info = {
+       XE_HPC_FEATURES,
+       XE_HPM_FEATURES,
+       DGFX_FEATURES,
+       .graphics.rel = 60,
+       .media.rel = 60,
+       PLATFORM(INTEL_PONTEVECCHIO),
+       .display = { 0 },
+       .has_flat_ccs = 0,
+       .platform_engine_mask =
+               BIT(BCS0) |
+               BIT(VCS0) |
+               BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
+       .require_force_probe = 1,
+};
+
 #undef PLATFORM
 
 /*
index 41a5b98d13422ad2bc91acc0a59f11ed61ce45a0..b0e62a411534a9c18ee5a14dc9f97627ceb6892a 100644 (file)
@@ -72,6 +72,7 @@ static const char * const platform_names[] = {
        PLATFORM_NAME(ALDERLAKE_P),
        PLATFORM_NAME(XEHPSDV),
        PLATFORM_NAME(DG2),
+       PLATFORM_NAME(PONTEVECCHIO),
 };
 #undef PLATFORM_NAME
 
index 576d15a04c9e2a6cdd9379e96c2b64420fcd6679..ec0b8095e7fa3c7d9c8900b5df32e22879477c56 100644 (file)
@@ -88,6 +88,7 @@ enum intel_platform {
        INTEL_ALDERLAKE_P,
        INTEL_XEHPSDV,
        INTEL_DG2,
+       INTEL_PONTEVECCHIO,
        INTEL_MAX_PLATFORMS
 };