arm: dts: mt7623: add spi nodes to the mt7623.dtsi file

Add spi controller nodes to the mt7623.dtsi file

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 31a7364..85b2d6d 100644 (file)
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -286,6 +286,48 @@
                status = "disabled";
        };
 
+       spi0: spi@1100a000 {
+               compatible = "mediatek,mt7623-spi",
+                            "mediatek,mt2701-spi";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0 0x1100a000 0 0x100>;
+               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+                        <&topckgen CLK_TOP_SPI0_SEL>,
+                        <&pericfg CLK_PERI_SPI0>;
+               clock-names = "parent-clk", "sel-clk", "spi-clk";
+               status = "disabled";
+       };
+
+       spi1: spi@11016000 {
+               compatible = "mediatek,mt7623-spi",
+                            "mediatek,mt2701-spi";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0 0x11016000 0 0x100>;
+               interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+                        <&topckgen CLK_TOP_SPI1_SEL>,
+                        <&pericfg CLK_PERI_SPI1>;
+               clock-names = "parent-clk", "sel-clk", "spi-clk";
+               status = "disabled";
+       };
+
+       spi2: spi@11017000 {
+               compatible = "mediatek,mt7623-spi",
+                            "mediatek,mt2701-spi";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0 0x11017000 0 0x1000>;
+               interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+                        <&topckgen CLK_TOP_SPI2_SEL>,
+                        <&pericfg CLK_PERI_SPI2>;
+               clock-names = "parent-clk", "sel-clk", "spi-clk";
+               status = "disabled";
+       };
+
        hifsys: syscon@1a000000 {
                compatible = "mediatek,mt7623-hifsys",
                             "mediatek,mt2701-hifsys",