}
}
-void timer_init(void)
+int timer_init(void)
{
volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
/* set a period of 1us, set timer mode to restart and
enable timer and interrupt */
timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN;
+ return 0;
}
ulong get_timer(ulong base)
extern ulong __init_end;
extern ulong __bss_end__;
-extern void timer_init(void);
-
#if defined(CONFIG_WATCHDOG)
# define INIT_FUNC_WATCHDOG_INIT watchdog_init,
# define WATCHDOG_DISABLE watchdog_disable
}
}
-void timer_init(void)
+int timer_init(void)
{
volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
+
+ return 0;
}
ulong get_timer(ulong base)
timerp->pcsr = PIT_PCSR_OVW;
timerp->pmr = lastinc = 0;
timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
+
+ return 0;
}
ulong get_timer(ulong base)