riscv: Fix clear bss loop in the start-up code

For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 0a2ce6d6913ed96868af9dbb6d1614fbbf9ada8a..ee6d4717da52a6057994af553501b9af18c7f2c4 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -174,7 +174,7 @@ spl_clear_bss:
 spl_clear_bss_loop:
        SREG    zero, 0(t0)
        addi    t0, t0, REGBYTES
-       bne     t0, t1, spl_clear_bss_loop
+       blt     t0, t1, spl_clear_bss_loop
 
 spl_stack_gd_setup:
        jal     spl_relocate_stack_gd
@@ -324,7 +324,7 @@ clear_bss:
 clbss_l:
        SREG    zero, 0(t0)             /* clear loop... */
        addi    t0, t0, REGBYTES
-       bne     t0, t1, clbss_l
+       blt     t0, t1, clbss_l
 
 relocate_secondary_harts:
 #ifdef CONFIG_SMP

diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 32255d58deba9ab6f6f0f1b98ce8e831f2ede6c6..955dd3106dcd7049f496e87824252a9ac5a4c47b 100644 (file)
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -76,7 +76,7 @@ SECTIONS
        .bss : {
                __bss_start = .;
                *(.bss*)
-               . = ALIGN(4);
+               . = ALIGN(8);
                __bss_end = .;
        } > .bss_mem
 }

diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index 11bc4a738b676a6fdfe868c48e87e204373e53ef..838a8443999cda6c450a37b5bf7f99d7671d6942 100644 (file)
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -82,7 +82,7 @@ SECTIONS
        .bss : {
                __bss_start = .;
                *(.bss*)
-               . = ALIGN(4);
+               . = ALIGN(8);
                __bss_end = .;
        }
 }