parisc: Add memory clobber to TLB purges

The pdtlb and pitlb instructions are strongly ordered. The asms invoking
these instructions should be compiler memory barriers to ensure the
compiler doesn't reorder memory operations around these instructions.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
CC: stable@vger.kernel.org # v4.20+
Fixes: 3847dab77421 ("parisc: Add alternative coding infrastructure")
Signed-off-by: Helge Deller <deller@gmx.de>

diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h
index 006fb93..c18351c 100644 (file)
--- a/arch/parisc/include/asm/cache.h
+++ b/arch/parisc/include/asm/cache.h
@@ -44,14 +44,14 @@ void parisc_setup_cache_timing(void);
 
 #define pdtlb(addr)    asm volatile("pdtlb 0(%%sr1,%0)" \
                        ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
-                       : : "r" (addr))
+                       : : "r" (addr) : "memory")
 #define pitlb(addr)    asm volatile("pitlb 0(%%sr1,%0)" \
                        ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
                        ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \
-                       : : "r" (addr))
+                       : : "r" (addr) : "memory")
 #define pdtlb_kernel(addr)  asm volatile("pdtlb 0(%0)"   \
                        ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
-                       : : "r" (addr))
+                       : : "r" (addr) : "memory")
 
 #define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
                        ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \