for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
- if ( status == MGA_ENDPRDMASTS ) return 0;
+ if ( status == MGA_ENDPRDMASTS ) {
+ MGA_WRITE8( MGA_CRTC_INDEX, 0 );
+ return 0;
+ }
udelay( 1 );
}
DRM_INFO( "\n" );
DRM_INFO( "current dispatch: last=0x%x done=0x%x\n",
dev_priv->sarea_priv->last_dispatch,
- *dev_priv->prim.head - dev_priv->primary->offset );
+ (unsigned int)(*dev_priv->prim.head -
+ dev_priv->primary->offset) );
DRM_INFO( "current freelist:\n" );
for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) {
static void mga_freelist_reset( drm_device_t *dev )
{
drm_device_dma_t *dma = dev->dma;
- drm_mga_private_t *dev_priv = dev->dev_private;
drm_buf_t *buf;
drm_mga_buf_priv_t *buf_priv;
int i;
dev_priv->primary->offset,
buf_priv->list_entry->age.wrap );
- if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) {
- SET_AGE( &next->age, MGA_BUFFER_FREE, 0 );
- }
-
/* Put buffer on the head + 1, as the head is a sentinal.
*/
+
next = buf_priv->list_entry;
head = dev_priv->head;
prev = head->next;
+
+ if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) {
+ SET_AGE( &next->age, MGA_BUFFER_FREE, 0 );
+ }
+
head->next = next;
prev->prev = next;
next->prev = head;
#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg )
#define MGA_READ( reg ) MGA_DEREF( reg )
#define MGA_WRITE( reg, val ) do { MGA_DEREF( reg ) = val; } while (0)
-
+#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg )
+#define MGA_WRITE8( reg, val ) do { MGA_DEREF8( reg ) = val; } while (0)
#define DWGREG0 0x1c00
#define DWGREG0_END 0x1dff
/* A reduced set of the mga registers.
*/
+#define MGA_CRTC_INDEX 0x1fd4
#define MGA_ALPHACTRL 0x2c7c
#define MGA_AR0 0x1c60