Add PCI IDs for Haswell

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

diff --git a/src/intel_driver.h b/src/intel_driver.h
index d4115b4..2791a68 100644 (file)
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -170,6 +170,46 @@ struct intel_region
 #define PCI_CHIP_IVYBRIDGE_S_GT1        0x015a  /* Server */
 #define PCI_CHIP_IVYBRIDGE_S_GT2        0x016a
 
+#define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
+#define PCI_CHIP_HASWELL_GT2            0x0412
+#define PCI_CHIP_HASWELL_GT2_PLUS       0x0422
+#define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
+#define PCI_CHIP_HASWELL_M_GT2          0x0416
+#define PCI_CHIP_HASWELL_M_GT2_PLUS     0x0426
+#define PCI_CHIP_HASWELL_S_GT1          0x040a /* Server */
+#define PCI_CHIP_HASWELL_S_GT2          0x041a
+#define PCI_CHIP_HASWELL_S_GT2_PLUS     0x042a
+
+#define        PCI_CHIP_HASWELL_SDV_GT1                0x0c02 /* Desktop */
+#define        PCI_CHIP_HASWELL_SDV_GT2                0x0c12
+#define        PCI_CHIP_HASWELL_SDV_GT2_PLUS           0x0c22
+#define        PCI_CHIP_HASWELL_SDV_M_GT1              0x0c06 /* Mobile */
+#define        PCI_CHIP_HASWELL_SDV_M_GT2              0x0c16
+#define        PCI_CHIP_HASWELL_SDV_M_GT2_PLUS         0x0c26
+#define        PCI_CHIP_HASWELL_SDV_S_GT1              0x0c0a /* Server */
+#define        PCI_CHIP_HASWELL_SDV_S_GT2              0x0c1a
+#define        PCI_CHIP_HASWELL_SDV_S_GT2_PLUS         0x0c2a
+
+#define        PCI_CHIP_HASWELL_ULT_GT1                0x0A02 /* Desktop */
+#define        PCI_CHIP_HASWELL_ULT_GT2                0x0A12
+#define        PCI_CHIP_HASWELL_ULT_GT2_PLUS           0x0A22
+#define        PCI_CHIP_HASWELL_ULT_M_GT1              0x0A06 /* Mobile */
+#define        PCI_CHIP_HASWELL_ULT_M_GT2              0x0A16
+#define        PCI_CHIP_HASWELL_ULT_M_GT2_PLUS         0x0A26
+#define        PCI_CHIP_HASWELL_ULT_S_GT1              0x0A0A /* Server */
+#define        PCI_CHIP_HASWELL_ULT_S_GT2              0x0A1A
+#define        PCI_CHIP_HASWELL_ULT_S_GT2_PLUS         0x0A2A
+
+#define        PCI_CHIP_HASWELL_CRW_GT1                0x0D12 /* Desktop */
+#define        PCI_CHIP_HASWELL_CRW_GT2                0x0D22
+#define        PCI_CHIP_HASWELL_CRW_GT2_PLUS           0x0D32
+#define        PCI_CHIP_HASWELL_CRW_M_GT1              0x0D16 /* Mobile */
+#define        PCI_CHIP_HASWELL_CRW_M_GT2              0x0D26
+#define        PCI_CHIP_HASWELL_CRW_M_GT2_PLUS         0x0D36
+#define        PCI_CHIP_HASWELL_CRW_S_GT1              0x0D1A /* Server */
+#define        PCI_CHIP_HASWELL_CRW_S_GT2              0x0D2A
+#define        PCI_CHIP_HASWELL_CRW_S_GT2_PLUS         0x0D3A
+
 #define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G ||   \
                                  devid == PCI_CHIP_Q45_G ||     \
                                  devid == PCI_CHIP_G45_G ||     \
@@ -184,6 +224,51 @@ struct intel_region
 #define IS_IRONLAKE_M(devid)    (devid == PCI_CHIP_IRONLAKE_M_G)
 #define IS_IRONLAKE(devid)      (IS_IRONLAKE_D(devid) || IS_IRONLAKE_M(devid))
 
+#define IS_HASWELL_ULT(devid)   (devid == PCI_CHIP_HASWELL_ULT_GT1     || \
+                                devid == PCI_CHIP_HASWELL_ULT_GT2      || \
+                                devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
+                                devid == PCI_CHIP_HASWELL_ULT_M_GT1    || \
+                                devid == PCI_CHIP_HASWELL_ULT_M_GT2    || \
+                                devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS       || \
+                                devid == PCI_CHIP_HASWELL_ULT_S_GT1    || \
+                                devid == PCI_CHIP_HASWELL_ULT_S_GT2    || \
+                                devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS)
+
+#define IS_HSW_GT1(devid)      (devid == PCI_CHIP_HASWELL_GT1          || \
+                                 devid == PCI_CHIP_HASWELL_M_GT1       || \
+                                 devid == PCI_CHIP_HASWELL_S_GT1       || \
+                                 devid == PCI_CHIP_HASWELL_SDV_GT1     || \
+                                 devid == PCI_CHIP_HASWELL_SDV_M_GT1   || \
+                                 devid == PCI_CHIP_HASWELL_SDV_S_GT1   || \
+                                 devid == PCI_CHIP_HASWELL_CRW_GT1     || \
+                                 devid == PCI_CHIP_HASWELL_CRW_M_GT1   || \
+                                 devid == PCI_CHIP_HASWELL_CRW_S_GT1)
+
+#define IS_HSW_GT2(devid)      (devid == PCI_CHIP_HASWELL_GT2          || \
+                                 devid == PCI_CHIP_HASWELL_M_GT2       || \
+                                 devid == PCI_CHIP_HASWELL_S_GT2       || \
+                                 devid == PCI_CHIP_HASWELL_SDV_GT2     || \
+                                 devid == PCI_CHIP_HASWELL_SDV_M_GT2   || \
+                                 devid == PCI_CHIP_HASWELL_SDV_S_GT2   || \
+                                 devid == PCI_CHIP_HASWELL_CRW_GT2     || \
+                                 devid == PCI_CHIP_HASWELL_CRW_M_GT2   || \
+                                 devid == PCI_CHIP_HASWELL_CRW_S_GT2)
+
+#define IS_HSW_GT2_PLUS(devid) (devid == PCI_CHIP_HASWELL_GT2_PLUS             || \
+                                 devid == PCI_CHIP_HASWELL_M_GT2_PLUS          || \
+                                 devid == PCI_CHIP_HASWELL_S_GT2_PLUS          || \
+                                 devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS                || \
+                                 devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS      || \
+                                 devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS      || \
+                                 devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS                || \
+                                 devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS      || \
+                                 devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
+
+#define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
+                                IS_HSW_GT2(devid) || \
+                                IS_HSW_GT2_PLUS(devid) || \
+                                IS_HASWELL_ULT(devid))
+
 #define IS_GEN6(devid)          (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
                                  devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
                                  devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS ||\
@@ -197,6 +282,7 @@ struct intel_region
                                  devid == PCI_CHIP_IVYBRIDGE_M_GT1 ||   \
                                  devid == PCI_CHIP_IVYBRIDGE_M_GT2 ||   \
                                  devid == PCI_CHIP_IVYBRIDGE_S_GT1 ||   \
-                                 devid == PCI_CHIP_IVYBRIDGE_S_GT2)
+                                 devid == PCI_CHIP_IVYBRIDGE_S_GT2 ||   \
+                                 IS_HASWELL(devid))
 
 #endif /* _INTEL_DRIVER_H_ */