vdin/sr: add vdin/viu/sr support for g12b
authorDezhi Kong <dezhi.kong@amlogic.com>
Sat, 26 May 2018 06:32:53 +0000 (14:32 +0800)
committerYixun Lan <yixun.lan@amlogic.com>
Fri, 29 Jun 2018 07:09:05 +0000 (00:09 -0700)
PD#165090: vdin/viu/sr: add vdin/viu/sr support for g12b

Change-Id: I74e3d879774cddba531498612d88d0642b4ac915
Signed-off-by: Dezhi Kong <dezhi.kong@amlogic.com>
arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts
drivers/amlogic/media/video_sink/video.c
drivers/amlogic/media/video_sink/vpp.c
drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c
drivers/amlogic/media/vin/tvin/viu/viuin.c

index f30c9e7..066e849 100644 (file)
 
        deinterlace {
                compatible = "amlogic, deinterlace";
-               status = "disabled";
+               status = "okay";
                /* 0:use reserved; 1:use cma; 2:use cma as reserved */
                flag_cma = <1>;
                //memory-region = <&di_reserved>;
        amlvecm {
                compatible = "amlogic, vecm";
                dev_name = "aml_vecm";
-               status = "disabled";
+               status = "okay";
                gamma_en = <0>;/*1:enabel ;0:disable*/
                wb_en = <0>;/*1:enabel ;0:disable*/
                cm_en = <0>;/*1:enabel ;0:disable*/
 /*if you want to use vdin just modify status to "ok"*/
 &vdin0 {
        memory-region = <&vdin0_cma_reserved>;
-       status = "disabled";
+       status = "okay";
        /*vdin write mem color depth support:
         *bit0:support 8bit
         *bit1:support 9bit
 };
 &vdin1 {
        memory-region = <&vdin1_cma_reserved>;
-       status = "disabled";
+       status = "okay";
        /*vdin write mem color depth support:
         *bit0:support 8bit
         *bit1:support 9bit
index bcc6c98..34fb82b 100644 (file)
@@ -6138,6 +6138,9 @@ SET_FILTER:
                        if (process_3d_type)
                                vpp_misc_set &= ~(VPP_VD2_PREBLEND |
                                        VPP_VD2_POSTBLEND | VPP_PREBLEND_EN);
+                       /*auto disable sr when video off*/
+                       VSYNC_WR_MPEG_REG(VPP_SRSHARP0_CTRL, 0);
+                       VSYNC_WR_MPEG_REG(VPP_SRSHARP1_CTRL, 0);
                        video_onoff_state = VIDEO_ENABLE_STATE_IDLE;
                        vpu_delay_work_flag |=
                                VPU_VIDEO_LAYER1_CHANGED;
index a0107a5..42819b1 100644 (file)
@@ -1774,7 +1774,7 @@ int vpp_set_super_scaler_regs(int scaler_path_sel,
        }
 
        /*ve input size setting*/
-       if (is_meson_txhd_cpu() || is_meson_g12a_cpu())
+       if (is_meson_txhd_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu())
                tmp_data = ((reg_srscl0_hsize & 0x1fff) << 16) |
                        (reg_srscl0_vsize & 0x1fff);
        else
@@ -1784,7 +1784,8 @@ int vpp_set_super_scaler_regs(int scaler_path_sel,
        if (tmp_data != tmp_data2)
                VSYNC_WR_MPEG_REG(VPP_VE_H_V_SIZE, tmp_data);
        /*chroma blue stretch size setting*/
-       if (is_meson_txlx_cpu() || is_meson_txhd_cpu() || is_meson_g12a_cpu()) {
+       if (is_meson_txlx_cpu() || is_meson_txhd_cpu() || is_meson_g12a_cpu() ||
+               is_meson_g12b_cpu()) {
                tmp_data = (((vpp_postblend_out_width & 0x1fff) << 16) |
                        (vpp_postblend_out_height & 0x1fff));
                VSYNC_WR_MPEG_REG(VPP_OUT_H_V_SIZE, tmp_data);
@@ -1816,13 +1817,13 @@ int vpp_set_super_scaler_regs(int scaler_path_sel,
        if ((scaler_path_sel == CORE0_PPS_CORE1) ||
                (scaler_path_sel == CORE1_BEFORE_PPS) ||
                (scaler_path_sel == CORE0_BEFORE_PPS)) {
-               if (is_meson_g12a_cpu())
+               if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
                        VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 1, 1, 1);
                else
                        VSYNC_WR_MPEG_REG_BITS(VPP_VE_ENABLE_CTRL,
                                0, data_path_chose, 1);
        } else {
-               if (is_meson_g12a_cpu()) {
+               if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) {
                        if (scaler_path_sel == CORE0_AFTER_PPS)
                                VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 0, 1, 1);
                        else
@@ -1958,7 +1959,8 @@ static void vpp_set_super_scaler(const struct vinfo_s *vinfo,
                                next_frame_par->supscl_path = CORE1_BEFORE_PPS;
                        else
                                next_frame_par->supscl_path = CORE1_AFTER_PPS;
-               } else if (is_meson_txhd_cpu() || is_meson_g12a_cpu()) {
+               } else if (is_meson_txhd_cpu() || is_meson_g12a_cpu() ||
+                       is_meson_g12b_cpu()) {
                        next_frame_par->supscl_path = CORE0_BEFORE_PPS;
                } else
                        next_frame_par->supscl_path = CORE0_PPS_CORE1;
@@ -2641,7 +2643,8 @@ void vpp_super_scaler_support(void)
        if (is_meson_gxlx_cpu()) {
                sr_support &= ~SUPER_CORE0_SUPPORT;
                sr_support |= SUPER_CORE1_SUPPORT;
-       } else if (is_meson_txhd_cpu() || is_meson_g12a_cpu()) {
+       } else if (is_meson_txhd_cpu() || is_meson_g12a_cpu() ||
+               is_meson_g12b_cpu()) {
                sr_support |= SUPER_CORE0_SUPPORT;
                sr_support &= ~SUPER_CORE1_SUPPORT;
        } else if (is_meson_gxtvbb_cpu() || is_meson_txl_cpu() ||
@@ -2657,10 +2660,9 @@ void vpp_super_scaler_support(void)
                sr_support &= ~SUPER_CORE1_SUPPORT;
        }
        scaler_path_sel = SCALER_PATH_MAX;
-       if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) {
+       if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
                sr_reg_offt = 0xc00;
-               super_scaler = false;
-       } else
+       else
                sr_reg_offt = 0;
 }
 /*for gxlx only have core1 which will affact pip line*/
index fcf8931..8164258 100644 (file)
@@ -582,7 +582,7 @@ static void vdin_set_meas_mux(unsigned int offset, enum tvin_port_e port_,
                        (bt_path == BT_PATH_GPIO_B))
                        meas_mux = MEAS_MUX_656_B;
                else if ((is_meson_gxl_cpu() || is_meson_gxm_cpu() ||
-                       is_meson_g12a_cpu()) &&
+                       is_meson_g12a_cpu() || is_meson_g12b_cpu()) &&
                        (bt_path == BT_PATH_GPIO))
                        meas_mux = MEAS_MUX_656;
                else
@@ -693,7 +693,7 @@ void vdin_set_top(unsigned int offset,
                        wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xe4,
                                VDI9_ASFIFO_CTRL_BIT, VDI9_ASFIFO_CTRL_WID);
                } else if ((is_meson_gxm_cpu() || is_meson_gxl_cpu() ||
-                       is_meson_g12a_cpu()) &&
+                       is_meson_g12a_cpu() || is_meson_g12b_cpu()) &&
                        (bt_path == BT_PATH_GPIO)) {
                        vdin_mux = VDIN_MUX_656;
                        wr_bits(offset, VDIN_ASFIFO_CTRL0, 0xe4,
@@ -1478,7 +1478,7 @@ void vdin_set_matrix(struct vdin_dev_s *devp)
                 */
                wr_bits(offset, VDIN_MATRIX_CTRL, 0,
                                VDIN_MATRIX1_EN_BIT, VDIN_MATRIX1_EN_WID);
-               if (is_meson_g12a_cpu())
+               if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
                        vdin_set_color_matrix0_g12a(devp->addr_offset,
                                devp->fmt_info_p,
                                devp->format_convert,
@@ -1511,7 +1511,7 @@ void vdin_set_matrix(struct vdin_dev_s *devp)
                                devp->prop.color_fmt_range,
                                devp->prop.vdin_hdr_Flag,
                                devp->color_range_mode);
-               if (is_meson_g12a_cpu())
+               if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
                        vdin_set_color_matrix0_g12a(devp->addr_offset,
                                devp->fmt_info_p,
                                devp->format_convert,
@@ -1546,7 +1546,7 @@ void vdin_set_matrixs(struct vdin_dev_s *devp, unsigned char id,
 {
        switch (id) {
        case 0:
-               if (is_meson_g12a_cpu())
+               if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
                        vdin_set_color_matrix0_g12a(devp->addr_offset,
                                devp->fmt_info_p,
                                devp->format_convert,
@@ -1596,7 +1596,7 @@ void vdin_set_prob_xy(unsigned int offset,
                        devp->prop.color_fmt_range,
                        devp->prop.vdin_hdr_Flag,
                        devp->color_range_mode);
-       if (is_meson_g12a_cpu())
+       if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
                vdin_set_color_matrix0_g12a(devp->addr_offset,
                        devp->fmt_info_p,
                        devp->format_convert,
@@ -2017,7 +2017,7 @@ void vdin_set_canvas_id(struct vdin_dev_s *devp, unsigned int rdma_enable,
 {
 #ifdef CONFIG_AML_RDMA
        if (rdma_enable) {
-               if (is_meson_g12a_cpu()) {
+               if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) {
                        rdma_write_reg_bits(devp->rdma_handle,
                                VDIN_COM_CTRL0+devp->addr_offset, 1,
                                VDIN_FORCEGOLINE_EN_BIT, 1);
index 9971360..0cc514f 100644 (file)
@@ -2447,12 +2447,12 @@ static int vdin_drv_probe(struct platform_device *pdev)
        /* @todo vdin_addr_offset */
        if (is_meson_gxbb_cpu() && vdevp->index)
                vdin_addr_offset[vdevp->index] = 0x70;
-       else if (is_meson_g12a_cpu() && vdevp->index)
+       else if ((is_meson_g12a_cpu() || is_meson_g12b_cpu()) && vdevp->index)
                vdin_addr_offset[vdevp->index] = 0x100;
        vdevp->addr_offset = vdin_addr_offset[vdevp->index];
        vdevp->flags = 0;
        /*canvas align number*/
-       if (is_meson_g12a_cpu())
+       if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
                vdevp->canvas_align = 64;
        else
                vdevp->canvas_align = 32;
index 7378d1a..51d3958 100644 (file)
@@ -208,7 +208,7 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
                        wr_viu(VPU_VIU2VDIN_HDN_CTRL, 0x40f00);
        } else
                wr_bits_viu(VPU_VIU2VDIN_HDN_CTRL, devp->parm.h_active, 0, 14);
-       if (is_meson_g12a_cpu()) {
+       if (is_meson_g12a_cpu()  || is_meson_g12b_cpu()) {
                if (((port >= TVIN_PORT_VIU1_WB0_VD1) &&
                        (port <= TVIN_PORT_VIU1_WB0_POST_BLEND)) ||
                        ((port >= TVIN_PORT_VIU2_WB0_VD1) &&
@@ -303,7 +303,7 @@ static void viuin_close(struct tvin_frontend_s *fe)
        if (open_cnt)
                open_cnt--;
        if (open_cnt == 0) {
-               if (is_meson_g12a_cpu()) {
+               if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) {
                        wr_viu(VPU_VIU_VDIN_IF_MUX_CTRL, 0);
                        wr_viu(VPP_WRBAK_CTRL, 0);