gallium/radeon: fix the ADDRESS_HI mask for EVENT_WRITE CIK packets
authorMarek Olšák <marek.olsak@amd.com>
Sun, 23 Aug 2015 10:57:09 +0000 (12:57 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Sat, 29 Aug 2015 21:03:08 +0000 (23:03 +0200)
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
src/gallium/drivers/radeon/r600_query.c

index 7057aa1..65339bb 100644 (file)
@@ -197,7 +197,7 @@ static void r600_emit_query_begin(struct r600_common_context *ctx, struct r600_q
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
                radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
                radeon_emit(cs, va);
-               radeon_emit(cs, (va >> 32UL) & 0xFF);
+               radeon_emit(cs, (va >> 32) & 0xFFFF);
                break;
        case PIPE_QUERY_PRIMITIVES_EMITTED:
        case PIPE_QUERY_PRIMITIVES_GENERATED:
@@ -206,13 +206,13 @@ static void r600_emit_query_begin(struct r600_common_context *ctx, struct r600_q
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
                radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
                radeon_emit(cs, va);
-               radeon_emit(cs, (va >> 32UL) & 0xFF);
+               radeon_emit(cs, (va >> 32) & 0xFFFF);
                break;
        case PIPE_QUERY_TIME_ELAPSED:
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
                radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
                radeon_emit(cs, va);
-               radeon_emit(cs, (3 << 29) | ((va >> 32UL) & 0xFF));
+               radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
                radeon_emit(cs, 0);
                radeon_emit(cs, 0);
                break;
@@ -220,7 +220,7 @@ static void r600_emit_query_begin(struct r600_common_context *ctx, struct r600_q
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
                radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
                radeon_emit(cs, va);
-               radeon_emit(cs, (va >> 32UL) & 0xFF);
+               radeon_emit(cs, (va >> 32) & 0xFFFF);
                break;
        default:
                assert(0);
@@ -254,7 +254,7 @@ static void r600_emit_query_end(struct r600_common_context *ctx, struct r600_que
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
                radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
                radeon_emit(cs, va);
-               radeon_emit(cs, (va >> 32UL) & 0xFF);
+               radeon_emit(cs, (va >> 32) & 0xFFFF);
                break;
        case PIPE_QUERY_PRIMITIVES_EMITTED:
        case PIPE_QUERY_PRIMITIVES_GENERATED:
@@ -264,7 +264,7 @@ static void r600_emit_query_end(struct r600_common_context *ctx, struct r600_que
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
                radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
                radeon_emit(cs, va);
-               radeon_emit(cs, (va >> 32UL) & 0xFF);
+               radeon_emit(cs, (va >> 32) & 0xFFFF);
                break;
        case PIPE_QUERY_TIME_ELAPSED:
                va += query->buffer.results_end + query->result_size/2;
@@ -273,7 +273,7 @@ static void r600_emit_query_end(struct r600_common_context *ctx, struct r600_que
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
                radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
                radeon_emit(cs, va);
-               radeon_emit(cs, (3 << 29) | ((va >> 32UL) & 0xFF));
+               radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
                radeon_emit(cs, 0);
                radeon_emit(cs, 0);
                break;
@@ -282,7 +282,7 @@ static void r600_emit_query_end(struct r600_common_context *ctx, struct r600_que
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
                radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
                radeon_emit(cs, va);
-               radeon_emit(cs, (va >> 32UL) & 0xFF);
+               radeon_emit(cs, (va >> 32) & 0xFFFF);
                break;
        default:
                assert(0);