powercap: Add AMD Fam17h RAPL support

Enable AMD Fam17h RAPL support for the power capping framework.

The support is as per AMD Fam17h Model31h (Zen2) and model 00-ffh
(Zen1) PPR.

Tested by comparing the results of following two sysfs entries and the
values directly read from corresponding MSRs via /dev/cpu/[x]/msr:
  /sys/class/powercap/intel-rapl/intel-rapl:0/energy_uj
  /sys/class/powercap/intel-rapl/intel-rapl:0/intel-rapl:0:0/energy_uj

Signed-off-by: Victor Ding <victording@google.com>
Acked-by: Kim Phillips <kim.phillips@amd.com>
[ rjw: Changelog edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 21917e1..c36a083 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -327,6 +327,7 @@
 #define MSR_PP1_POLICY                 0x00000642
 
 #define MSR_AMD_RAPL_POWER_UNIT                0xc0010299
+#define MSR_AMD_CORE_ENERGY_STATUS             0xc001029a
 #define MSR_AMD_PKG_ENERGY_STATUS      0xc001029b
 
 /* Config TDP MSRs */

diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index 70d6d52..1ecd094 100644 (file)
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -1011,6 +1011,10 @@ static const struct rapl_defaults rapl_defaults_cht = {
        .compute_time_window = rapl_compute_time_window_atom,
 };
 
+static const struct rapl_defaults rapl_defaults_amd = {
+       .check_unit = rapl_check_unit_core,
+};
+
 static const struct x86_cpu_id rapl_ids[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE,         &rapl_defaults_core),
        X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X,       &rapl_defaults_core),
@@ -1061,6 +1065,8 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
 
        X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL,        &rapl_defaults_hsw_server),
        X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM,        &rapl_defaults_hsw_server),
+
+       X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd),
        {}
 };
 MODULE_DEVICE_TABLE(x86cpu, rapl_ids);

diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rapl_msr.c
index a819b3b..78213d4 100644 (file)
--- a/drivers/powercap/intel_rapl_msr.c
+++ b/drivers/powercap/intel_rapl_msr.c
@@ -49,6 +49,14 @@ static struct rapl_if_priv rapl_msr_priv_intel = {
        .limits[RAPL_DOMAIN_PLATFORM] = 2,
 };
 
+static struct rapl_if_priv rapl_msr_priv_amd = {
+       .reg_unit = MSR_AMD_RAPL_POWER_UNIT,
+       .regs[RAPL_DOMAIN_PACKAGE] = {
+               0, MSR_AMD_PKG_ENERGY_STATUS, 0, 0, 0 },
+       .regs[RAPL_DOMAIN_PP0] = {
+               0, MSR_AMD_CORE_ENERGY_STATUS, 0, 0, 0 },
+};
+
 /* Handles CPU hotplug on multi-socket systems.
  * If a CPU goes online as the first CPU of the physical package
  * we add the RAPL package to the system. Similarly, when the last
@@ -138,7 +146,17 @@ static int rapl_msr_probe(struct platform_device *pdev)
        const struct x86_cpu_id *id = x86_match_cpu(pl4_support_ids);
        int ret;
 
-       rapl_msr_priv = &rapl_msr_priv_intel;
+       switch (boot_cpu_data.x86_vendor) {
+       case X86_VENDOR_INTEL:
+               rapl_msr_priv = &rapl_msr_priv_intel;
+               break;
+       case X86_VENDOR_AMD:
+               rapl_msr_priv = &rapl_msr_priv_amd;
+               break;
+       default:
+               pr_err("intel-rapl does not support CPU vendor %d\n", boot_cpu_data.x86_vendor);
+               return -ENODEV;
+       }
        rapl_msr_priv->read_raw = rapl_msr_read_raw;
        rapl_msr_priv->write_raw = rapl_msr_write_raw;