arm64: dts: renesas: r8a7796: Fix register mappings on VSPs

The VSPD includes a CLUT on RPF2. Ensure that the register space is
mapped correctly to support this.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index f8e9313..157bd28 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -1903,7 +1903,7 @@
 
                vspd0: vsp@fea20000 {
                        compatible = "renesas,vsp2";
-                       reg = <0 0xfea20000 0 0x4000>;
+                       reg = <0 0xfea20000 0 0x8000>;
                        interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 623>;
                        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1923,7 +1923,7 @@
 
                vspd1: vsp@fea28000 {
                        compatible = "renesas,vsp2";
-                       reg = <0 0xfea28000 0 0x4000>;
+                       reg = <0 0xfea28000 0 0x8000>;
                        interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 622>;
                        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1943,7 +1943,7 @@
 
                vspd2: vsp@fea30000 {
                        compatible = "renesas,vsp2";
-                       reg = <0 0xfea30000 0 0x4000>;
+                       reg = <0 0xfea30000 0 0x8000>;
                        interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 621>;
                        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;