module_param(cur_hdr_support, uint, 0664);
MODULE_PARM_DESC(cur_hdr_support, "\n cur_hdr_support\n");
+static uint cur_output_mode;
+module_param(cur_output_mode, uint, 0664);
+MODULE_PARM_DESC(cur_output_mode, "\n cur_output_mode\n");
+
static uint range_control;
module_param(range_control, uint, 0664);
MODULE_PARM_DESC(range_control, "\n range_control 0:limit 1:full\n");
#define SIG_HDR_MODE 0x10
#define SIG_HDR_SUPPORT 0x20
#define SIG_WB_CHG 0x40
+#define SIG_OP_CHG 0x200
int signal_type_changed(struct vframe_s *vf, struct vinfo_s *vinfo)
{
change_flag |= SIG_HDR_SUPPORT;
cur_hdr_support = vinfo->hdr_info.hdr_support & 0x4;
}
-
+ if (cur_output_mode != vinfo->viu_color_fmt) {
+ pr_csc("output mode changed.\n");
+ change_flag |= SIG_OP_CHG;
+ cur_output_mode = vinfo->viu_color_fmt;
+ }
if ((cur_eye_protect_mode != wb_val[0]) ||
(cur_eye_protect_mode == 1)) {
pr_csc(" eye protect mode changed.\n");
if ((cur_csc_type != csc_type)
|| (signal_change_flag
& (SIG_PRI_INFO | SIG_KNEE_FACTOR | SIG_HDR_MODE |
- SIG_HDR_SUPPORT))) {
+ SIG_HDR_SUPPORT | SIG_OP_CHG))) {
/* decided by edid or panel info or user setting */
if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) &&
hdr_process_mode) {
}
}
}
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) {
+ if (vinfo->viu_color_fmt != COLOR_FMT_RGB444)
+ mtx_setting(POST2_MTX, MATRIX_NULL, MTX_OFF);
+ else
+ mtx_setting(POST2_MTX,
+ MATRIX_YUV709_RGB, MTX_ON);
+ }
+
if (cur_hdr_process_mode != hdr_process_mode) {
cur_hdr_process_mode = hdr_process_mode;
pr_csc("hdr_process_mode changed to %d",
static int last_vf_signal_type;
static int null_vf_cnt;
static int prev_hdr_support;
+static int prev_output_mode;
static unsigned int fg_vf_sw_dbg;
unsigned int null_vf_max = 1;
module_param(null_vf_max, uint, 0664);
MODULE_PARM_DESC(null_vf_max, "\n null_vf_max\n");
+
int amvecm_matrix_process(
struct vframe_s *vf, struct vframe_s *vf_rpt, int flags)
{
null_vf_cnt = 0;
prev_hdr_support = vinfo->hdr_info.hdr_support;
}
+ /* handle change between output mode*/
+ if (prev_output_mode != vinfo->viu_color_fmt) {
+ null_vf_cnt = 0;
+ prev_output_mode = vinfo->viu_color_fmt;
+ }
/* handle eye protect mode */
if (cur_eye_protect_mode != wb_val[0])
null_vf_cnt = 0;
#define VI_HIST_PIC_HEIGHT_WID 13
#define VI_HIST_PIC_WIDTH_BIT 0
#define VI_HIST_PIC_WIDTH_WID 13
+
+/*G12A Matrix reg*/
+#define VPP_VD1_MATRIX_COEF00_01 0x3290
+#define VPP_VD1_MATRIX_COEF02_10 0x3291
+#define VPP_VD1_MATRIX_COEF11_12 0x3292
+#define VPP_VD1_MATRIX_COEF20_21 0x3293
+#define VPP_VD1_MATRIX_COEF22 0x3294
+#define VPP_VD1_MATRIX_COEF13_14 0x3295
+#define VPP_VD1_MATRIX_COEF23_24 0x3296
+#define VPP_VD1_MATRIX_COEF15_25 0x3297
+#define VPP_VD1_MATRIX_CLIP 0x3298
+#define VPP_VD1_MATRIX_OFFSET0_1 0x3299
+#define VPP_VD1_MATRIX_OFFSET2 0x329a
+#define VPP_VD1_MATRIX_PRE_OFFSET0_1 0x329b
+#define VPP_VD1_MATRIX_PRE_OFFSET2 0x329c
+#define VPP_VD1_MATRIX_EN_CTRL 0x329d
+
+#define VPP_POST_MATRIX_COEF00_01 0x32b0
+#define VPP_POST_MATRIX_COEF02_10 0x32b1
+#define VPP_POST_MATRIX_COEF11_12 0x32b2
+#define VPP_POST_MATRIX_COEF20_21 0x32b3
+#define VPP_POST_MATRIX_COEF22 0x32b4
+#define VPP_POST_MATRIX_COEF13_14 0x32b5
+#define VPP_POST_MATRIX_COEF23_24 0x32b6
+#define VPP_POST_MATRIX_COEF15_25 0x32b7
+#define VPP_POST_MATRIX_CLIP 0x32b8
+#define VPP_POST_MATRIX_OFFSET0_1 0x32b9
+#define VPP_POST_MATRIX_OFFSET2 0x32ba
+#define VPP_POST_MATRIX_PRE_OFFSET0_1 0x32bb
+#define VPP_POST_MATRIX_PRE_OFFSET2 0x32bc
+#define VPP_POST_MATRIX_EN_CTRL 0x32bd
+
+#define VPP_POST2_MATRIX_COEF00_01 0x39a0
+#define VPP_POST2_MATRIX_COEF02_10 0x39a1
+#define VPP_POST2_MATRIX_COEF11_12 0x39a2
+#define VPP_POST2_MATRIX_COEF20_21 0x39a3
+#define VPP_POST2_MATRIX_COEF22 0x39a4
+#define VPP_POST2_MATRIX_COEF13_14 0x39a5
+#define VPP_POST2_MATRIX_COEF23_24 0x39a6
+#define VPP_POST2_MATRIX_COEF15_25 0x39a7
+#define VPP_POST2_MATRIX_CLIP 0x39a8
+#define VPP_POST2_MATRIX_OFFSET0_1 0x39a9
+#define VPP_POST2_MATRIX_OFFSET2 0x39aa
+#define VPP_POST2_MATRIX_PRE_OFFSET0_1 0x39ab
+#define VPP_POST2_MATRIX_PRE_OFFSET2 0x39ac
+#define VPP_POST2_MATRIX_EN_CTRL 0x39ad
#endif
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
+#include <linux/amlogic/media/amvecm/amvecm.h>
#include "set_hdr2_v0.h"
#include "arch/vpp_hdr_regs.h"
-#include <linux/amlogic/media/amvecm/amvecm.h>
-
-
+#include "arch/vpp_regs.h"
//#define HDR2_MODULE
//#define HDR2_PRINT
set_c_gain(module_sel, cgain_lut, LUT_ON);
}
+/*G12A matrix setting*/
+void mtx_setting(enum vpp_matrix_e mtx_sel,
+ enum mtx_csc_e mtx_csc,
+ int mtx_on)
+{
+ unsigned int matrix_coef00_01 = 0;
+ unsigned int matrix_coef02_10 = 0;
+ unsigned int matrix_coef11_12 = 0;
+ unsigned int matrix_coef20_21 = 0;
+ unsigned int matrix_coef22 = 0;
+ unsigned int matrix_coef13_14 = 0;
+ unsigned int matrix_coef23_24 = 0;
+ unsigned int matrix_coef15_25 = 0;
+ unsigned int matrix_clip = 0;
+ unsigned int matrix_offset0_1 = 0;
+ unsigned int matrix_offset2 = 0;
+ unsigned int matrix_pre_offset0_1 = 0;
+ unsigned int matrix_pre_offset2 = 0;
+ unsigned int matrix_en_ctrl = 0;
+
+ if (mtx_sel & VD1_MTX) {
+ matrix_coef00_01 = VPP_VD1_MATRIX_COEF00_01;
+ matrix_coef02_10 = VPP_VD1_MATRIX_COEF02_10;
+ matrix_coef11_12 = VPP_VD1_MATRIX_COEF11_12;
+ matrix_coef20_21 = VPP_VD1_MATRIX_COEF20_21;
+ matrix_coef22 = VPP_VD1_MATRIX_COEF22;
+ matrix_coef13_14 = VPP_VD1_MATRIX_COEF13_14;
+ matrix_coef23_24 = VPP_VD1_MATRIX_COEF23_24;
+ matrix_coef15_25 = VPP_VD1_MATRIX_COEF15_25;
+ matrix_clip = VPP_VD1_MATRIX_CLIP;
+ matrix_offset0_1 = VPP_VD1_MATRIX_OFFSET0_1;
+ matrix_offset2 = VPP_VD1_MATRIX_OFFSET2;
+ matrix_pre_offset0_1 = VPP_VD1_MATRIX_PRE_OFFSET0_1;
+ matrix_pre_offset2 = VPP_VD1_MATRIX_PRE_OFFSET2;
+ matrix_en_ctrl = VPP_VD1_MATRIX_EN_CTRL;
+
+ WRITE_VPP_REG_BITS(VPP_VD1_MATRIX_EN_CTRL, mtx_on, 0, 1);
+ } else if (mtx_sel & POST2_MTX) {
+ matrix_coef00_01 = VPP_POST2_MATRIX_COEF00_01;
+ matrix_coef02_10 = VPP_POST2_MATRIX_COEF02_10;
+ matrix_coef11_12 = VPP_POST2_MATRIX_COEF11_12;
+ matrix_coef20_21 = VPP_POST2_MATRIX_COEF20_21;
+ matrix_coef22 = VPP_POST2_MATRIX_COEF22;
+ matrix_coef13_14 = VPP_POST2_MATRIX_COEF13_14;
+ matrix_coef23_24 = VPP_POST2_MATRIX_COEF23_24;
+ matrix_coef15_25 = VPP_POST2_MATRIX_COEF15_25;
+ matrix_clip = VPP_POST2_MATRIX_CLIP;
+ matrix_offset0_1 = VPP_POST2_MATRIX_OFFSET0_1;
+ matrix_offset2 = VPP_POST2_MATRIX_OFFSET2;
+ matrix_pre_offset0_1 = VPP_POST2_MATRIX_PRE_OFFSET0_1;
+ matrix_pre_offset2 = VPP_POST2_MATRIX_PRE_OFFSET2;
+ matrix_en_ctrl = VPP_POST2_MATRIX_EN_CTRL;
+
+ WRITE_VPP_REG_BITS(VPP_POST2_MATRIX_EN_CTRL, mtx_on, 0, 1);
+ } else if (mtx_sel & POST_MTX) {
+ matrix_coef00_01 = VPP_POST_MATRIX_COEF00_01;
+ matrix_coef02_10 = VPP_POST_MATRIX_COEF02_10;
+ matrix_coef11_12 = VPP_POST_MATRIX_COEF11_12;
+ matrix_coef20_21 = VPP_POST_MATRIX_COEF20_21;
+ matrix_coef22 = VPP_POST_MATRIX_COEF22;
+ matrix_coef13_14 = VPP_POST_MATRIX_COEF13_14;
+ matrix_coef23_24 = VPP_POST_MATRIX_COEF23_24;
+ matrix_coef15_25 = VPP_POST_MATRIX_COEF15_25;
+ matrix_clip = VPP_POST_MATRIX_CLIP;
+ matrix_offset0_1 = VPP_POST_MATRIX_OFFSET0_1;
+ matrix_offset2 = VPP_POST_MATRIX_OFFSET2;
+ matrix_pre_offset0_1 = VPP_POST_MATRIX_PRE_OFFSET0_1;
+ matrix_pre_offset2 = VPP_POST_MATRIX_PRE_OFFSET2;
+ matrix_en_ctrl = VPP_POST_MATRIX_EN_CTRL;
+
+ WRITE_VPP_REG_BITS(VPP_POST_MATRIX_EN_CTRL, mtx_on, 0, 1);
+ }
+
+ if (!mtx_on)
+ return;
+
+ switch (mtx_csc) {
+ case MATRIX_RGB_YUV709:
+ WRITE_VPP_REG(matrix_coef00_01, 0x00bb0275);
+ WRITE_VPP_REG(matrix_coef02_10, 0x003f1f99);
+ WRITE_VPP_REG(matrix_coef11_12, 0x1ea601c2);
+ WRITE_VPP_REG(matrix_coef20_21, 0x01c21e67);
+ WRITE_VPP_REG(matrix_coef22, 0x00001fd7);
+ WRITE_VPP_REG(matrix_offset0_1, 0x00400200);
+ WRITE_VPP_REG(matrix_offset2, 0x00000200);
+ WRITE_VPP_REG(matrix_pre_offset0_1, 0x0);
+ WRITE_VPP_REG(matrix_pre_offset2, 0x0);
+ break;
+ case MATRIX_YUV709_RGB:
+ WRITE_VPP_REG(matrix_coef00_01, 0x04A80000);
+ WRITE_VPP_REG(matrix_coef02_10, 0x072C04A8);
+ WRITE_VPP_REG(matrix_coef11_12, 0x1F261DDD);
+ WRITE_VPP_REG(matrix_coef20_21, 0x04A80876);
+ WRITE_VPP_REG(matrix_coef22, 0x0);
+ WRITE_VPP_REG(matrix_offset0_1, 0x0);
+ WRITE_VPP_REG(matrix_offset2, 0x0);
+ WRITE_VPP_REG(matrix_pre_offset0_1, 0x7c00600);
+ WRITE_VPP_REG(matrix_pre_offset2, 0x00000600);
+ break;
+ default:
+ break;
+ }
+}
extern void hdrbypass_func(enum hdr_module_sel module_sel);
extern void hdr2sdr_func(enum hdr_module_sel module_sel);
extern void sdr2hdr_func(enum hdr_module_sel module_sel);
+/*G12A vpp matrix*/
+enum vpp_matrix_e {
+ VD1_MTX = 0x1,
+ POST2_MTX = 0x2,
+ POST_MTX = 0x4
+};
+
+enum mtx_csc_e {
+ MATRIX_NULL = 0,
+ MATRIX_RGB_YUV601 = 0x1,
+ MATRIX_RGB_YUV601F = 0x2,
+ MATRIX_RGB_YUV709 = 0x3,
+ MATRIX_RGB_YUV709F = 0x4,
+ MATRIX_YUV601_RGB = 0x10,
+ MATRIX_YUV601_YUV601F = 0x11,
+ MATRIX_YUV601_YUV709 = 0x12,
+ MATRIX_YUV601_YUV709F = 0x13,
+ MATRIX_YUV601F_RGB = 0x14,
+ MATRIX_YUV601F_YUV601 = 0x15,
+ MATRIX_YUV601F_YUV709 = 0x16,
+ MATRIX_YUV601F_YUV709F = 0x17,
+ MATRIX_YUV709_RGB = 0x20,
+ MATRIX_YUV709_YUV601 = 0x21,
+ MATRIX_YUV709_YUV601F = 0x22,
+ MATRIX_YUV709_YUV709F = 0x23,
+ MATRIX_YUV709F_RGB = 0x24,
+ MATRIX_YUV709F_YUV601 = 0x25,
+ MATRIX_YUV709F_YUV709 = 0x26,
+ MATRIX_BT2020YUV_BT2020RGB = 0x40,
+ MATRIX_BT2020RGB_709RGB,
+ MATRIX_BT2020RGB_CUSRGB,
+};
+extern void mtx_setting(enum vpp_matrix_e mtx_sel,
+ enum mtx_csc_e mtx_csc,
+ int mtx_on);
projects / platform / kernel / linux-amlogic.git / commitdiff