markAllChildren(dag);
}
- const uint32_t simdWidth = sel.ctx.getSimdWidth();
const Register pred = insn.getPredicate();
sel.push();
sel.curr.predicate = GEN_PREDICATE_NONE;
/* All user events complete, now wait enqueue events */
ret = cl_event_wait_events(enqueue_cb->num_events, enqueue_cb->wait_list,
enqueue_cb->event->queue);
+ ret = ret;
assert(ret != CL_ENQUEUE_EXECUTE_DEFER);
cb = enqueue_cb;
cl_gpgpu_event_get_exec_timestamp(event->gpgpu_event, 1, &ret_val);
event->timestamp[param_name - CL_PROFILING_COMMAND_QUEUED] = ret_val;
return CL_SUCCESS;
- } else {
- return CL_INVALID_VALUE;
}
+ return CL_INVALID_VALUE;
}
cl_image_format fmt,
size_t row_pitch,
cl_int *errcode);
+extern cl_int cl_mem_get_fd(cl_mem mem, int* fd);
+
#endif /* __CL_MEM_H__ */
static int intel_buffer_set_tiling(cl_buffer bo,
cl_image_tiling_t tiling, size_t stride)
{
- uint32_t intel_tiling, required_tiling;
+ uint32_t intel_tiling;
int ret;
if (UNLIKELY((get_intel_tiling(tiling, &intel_tiling)) < 0))
return -1;
+#ifndef NDEBUG
+ uint32_t required_tiling;
required_tiling = intel_tiling;
+#endif
ret = drm_intel_bo_set_tiling((drm_intel_bo*)bo, &intel_tiling, stride);
assert(intel_tiling == required_tiling);
return ret;
char magic[2];
int ret;
ret = fread(&magic[0], 1, 2, fp);
+ ret = ret;
assert(2 == ret);
assert(magic[0] == 'B' && magic[1] == 'M');