Make FlushICache NOP for Nvidia Denver 1.0 only

FlushICache should be NOP for Denver with part numbers 0x0, 0x1 and 0x2 only.
Instruction cache needs to flushed for future versions of denver.

Review URL: https://codereview.chromium.org/1287173004

Cr-Commit-Position: refs/heads/master@{#30262}

diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
index 862748c..633b5d1 100644 (file)
--- a/src/arm/assembler-arm.cc
+++ b/src/arm/assembler-arm.cc
@@ -126,7 +126,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   if (FLAG_enable_32dregs && cpu.has_vfp3_d32()) supported_ |= 1u << VFP32DREGS;
 
   if (cpu.implementer() == base::CPU::NVIDIA &&
-      cpu.variant() == base::CPU::NVIDIA_DENVER) {
+      cpu.variant() == base::CPU::NVIDIA_DENVER &&
+      cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
     supported_ |= 1u << COHERENT_CACHE;
   }
 #endif

diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc
index 8db7126..235b5ee 100644 (file)
--- a/src/arm64/assembler-arm64.cc
+++ b/src/arm64/assembler-arm64.cc
@@ -52,7 +52,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   // Probe for runtime features
   base::CPU cpu;
   if (cpu.implementer() == base::CPU::NVIDIA &&
-      cpu.variant() == base::CPU::NVIDIA_DENVER) {
+      cpu.variant() == base::CPU::NVIDIA_DENVER &&
+      cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
     supported_ |= 1u << COHERENT_CACHE;
   }
 }

diff --git a/src/base/cpu.h b/src/base/cpu.h
index f6c5a85..1dc0a91 100644 (file)
--- a/src/base/cpu.h
+++ b/src/base/cpu.h
@@ -59,6 +59,9 @@ class CPU final {
   static const int ARM_CORTEX_A12 = 0xc0c;
   static const int ARM_CORTEX_A15 = 0xc0f;
 
+  // Denver-specific part code
+  static const int NVIDIA_DENVER_V10 = 0x002;
+
   // PPC-specific part codes
   enum {
     PPC_POWER5,