arm64: dts: sdm845: add Inline Crypto Engine registers and clock

Add the vendor-specific registers and clock for Qualcomm ICE (Inline
Crypto Engine) to the device tree node for the UFS host controller on
sdm845, so that the ufs-qcom driver will be able to use inline crypto.

Use a separate register range rather than extending the main UFS range
because there's a gap between the two, and the ICE registers are
vendor-specific.  (Actually, the hardware claims that the ICE range also
includes the array of standard crypto configuration registers; however,
on this SoC the Linux kernel isn't permitted to access them directly.)

Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20200710072013.177481-4-ebiggers@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index c7bbb29..759cdd0 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2060,7 +2060,9 @@
                ufs_mem_hc: ufshc@1d84000 {
                        compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
                                     "jedec,ufs-2.0";
-                       reg = <0 0x01d84000 0 0x2500>;
+                       reg = <0 0x01d84000 0 0x2500>,
+                             <0 0x01d90000 0 0x8000>;
+                       reg-names = "std", "ice";
                        interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
                        phys = <&ufs_mem_phy_lanes>;
                        phy-names = "ufsphy";
@@ -2080,7 +2082,8 @@
                                "ref_clk",
                                "tx_lane0_sync_clk",
                                "rx_lane0_sync_clk",
-                               "rx_lane1_sync_clk";
+                               "rx_lane1_sync_clk",
+                               "ice_core_clk";
                        clocks =
                                <&gcc GCC_UFS_PHY_AXI_CLK>,
                                <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
@@ -2089,7 +2092,8 @@
                                <&rpmhcc RPMH_CXO_CLK>,
                                <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
                                <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
-                               <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+                               <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
+                               <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
                        freq-table-hz =
                                <50000000 200000000>,
                                <0 0>,
@@ -2098,7 +2102,8 @@
                                <0 0>,
                                <0 0>,
                                <0 0>,
-                               <0 0>;
+                               <0 0>,
+                               <0 300000000>;
 
                        status = "disabled";
                };