net: dwc_eth_qos: Fully rewrite RX descriptor field 3

The RX descriptor field 3 should contain only OWN and BUF1V bits before
being used for receiving data by the DMA engine. However, right now, if
the descriptor was already used for receiving data and is being cleared,
the field 3 is only modified and the aforementioned two bits are ORRed
into the field. This could lead to a residual dirty bits being left in
the field 3 from previous transfer, and it generally does. Fully set the
field 3 instead to clear those residual dirty bits.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 63f2086..4f24520 100644 (file)
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1288,7 +1288,7 @@ static int eqos_start(struct udevice *dev)
                struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
                rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
                                             (i * EQOS_MAX_PACKET_SIZE));
-               rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+               rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
        }
        eqos->config->ops->eqos_flush_desc(eqos->descs);
 
@@ -1482,7 +1482,7 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
         * writes to the rest of the descriptor too.
         */
        mb();
-       rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+       rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
        eqos->config->ops->eqos_flush_desc(rx_desc);
 
        writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);