nir: Remove nir_alu_dest::write_mask

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>

diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index bc6c99a..3aa38f1 100644 (file)
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -655,12 +655,6 @@ instr_init(nir_instr *instr, nir_instr_type type)
 }
 
 static void
-alu_dest_init(nir_alu_dest *dest)
-{
-   dest->write_mask = 0xf;
-}
-
-static void
 alu_src_init(nir_alu_src *src)
 {
    src_init(&src->src);
@@ -676,7 +670,6 @@ nir_alu_instr_create(nir_shader *shader, nir_op op)
 
    instr_init(&instr->instr, nir_instr_type_alu);
    instr->op = op;
-   alu_dest_init(&instr->dest);
    for (unsigned i = 0; i < num_srcs; i++)
       alu_src_init(&instr->src[i]);
 
@@ -2909,7 +2902,7 @@ nir_alu_instr_channel_used(const nir_alu_instr *instr, unsigned src,
    if (nir_op_infos[instr->op].input_sizes[src] > 0)
       return channel < nir_op_infos[instr->op].input_sizes[src];
 
-   return (instr->dest.write_mask >> channel) & 1;
+   return channel < nir_dest_num_components(instr->dest.dest);
 }
 
 nir_component_mask_t

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 0178bc5..c207800 100644 (file)
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1148,13 +1148,6 @@ typedef struct {
 typedef struct {
    /** Base destination */
    nir_dest dest;
-
-   /**
-    * Write-mask
-    *
-    * Ignored if dest.is_ssa is true
-    */
-   nir_component_mask_t write_mask;
 } nir_alu_dest;
 
 /** NIR sized and unsized types
@@ -2655,7 +2648,6 @@ nir_ssa_scalar_chase_alu_src(nir_ssa_scalar s, unsigned alu_src_idx)
 
    /* Our component must be written */
    assert(s.comp < s.def->num_components);
-   assert(alu->dest.write_mask & (1u << s.comp));
 
    out.def = alu->src[alu_src_idx].src.ssa;
 

diff --git a/src/compiler/nir/nir_builder.c b/src/compiler/nir/nir_builder.c
index 484a65e..a7f6ae7 100644 (file)
--- a/src/compiler/nir/nir_builder.c
+++ b/src/compiler/nir/nir_builder.c
@@ -115,7 +115,6 @@ nir_builder_alu_instr_finish_and_insert(nir_builder *build, nir_alu_instr *instr
 
    nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_components,
                      bit_size);
-   instr->dest.write_mask = nir_component_mask(num_components);
 
    nir_builder_instr_insert(build, &instr->instr);
 
@@ -331,7 +330,6 @@ nir_vec_scalars(nir_builder *build, nir_ssa_scalar *comp, unsigned num_component
     */
    nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_components,
                      comp[0].def->bit_size);
-   instr->dest.write_mask = nir_component_mask(num_components);
 
    nir_builder_instr_insert(build, &instr->instr);
 

diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index cb74c63..e098101 100644 (file)
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -512,7 +512,6 @@ nir_mov_alu(nir_builder *build, nir_alu_src src, unsigned num_components)
    nir_ssa_dest_init(&mov->instr, &mov->dest.dest, num_components,
                      nir_src_bit_size(src.src));
    mov->exact = build->exact;
-   mov->dest.write_mask = (1 << num_components) - 1;
    mov->src[0] = src;
    nir_builder_instr_insert(build, &mov->instr);
 

diff --git a/src/compiler/nir/nir_clone.c b/src/compiler/nir/nir_clone.c
index eabc040..0b03442 100644 (file)
--- a/src/compiler/nir/nir_clone.c
+++ b/src/compiler/nir/nir_clone.c
@@ -221,7 +221,6 @@ clone_alu(clone_state *state, const nir_alu_instr *alu)
    nalu->no_unsigned_wrap = alu->no_unsigned_wrap;
 
    __clone_dst(state, &nalu->instr, &nalu->dest.dest, &alu->dest.dest);
-   nalu->dest.write_mask = alu->dest.write_mask;
 
    for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
       __clone_src(state, &nalu->instr, &nalu->src[i].src, &alu->src[i].src);

diff --git a/src/compiler/nir/nir_lower_alu_width.c b/src/compiler/nir/nir_lower_alu_width.c
index 9ba2b81..46a479f 100644 (file)
--- a/src/compiler/nir/nir_lower_alu_width.c
+++ b/src/compiler/nir/nir_lower_alu_width.c
@@ -90,7 +90,6 @@ nir_alu_ssa_dest_init(nir_alu_instr *alu, unsigned num_components,
                       unsigned bit_size)
 {
    nir_ssa_dest_init(&alu->instr, &alu->dest.dest, num_components, bit_size);
-   alu->dest.write_mask = (1 << num_components) - 1;
 }
 
 static nir_ssa_def *
@@ -187,8 +186,6 @@ lower_alu_instr_width(nir_builder *b, nir_instr *instr, void *_data)
    unsigned num_src = nir_op_infos[alu->op].num_inputs;
    unsigned i, chan;
 
-   assert(alu->dest.write_mask != 0);
-
    b->exact = alu->exact;
 
    unsigned num_components = alu->dest.dest.ssa.num_components;

diff --git a/src/compiler/nir/nir_lower_bool_to_bitsize.c b/src/compiler/nir/nir_lower_bool_to_bitsize.c
index a176a74..9328d32 100644 (file)
--- a/src/compiler/nir/nir_lower_bool_to_bitsize.c
+++ b/src/compiler/nir/nir_lower_bool_to_bitsize.c
@@ -73,7 +73,6 @@ make_sources_canonical(nir_builder *b, nir_alu_instr *alu, uint32_t start_idx)
           */
          nir_alu_instr *conv_instr =
             nir_instr_as_alu(nir_builder_last_instr(b));
-         conv_instr->dest.write_mask = alu->dest.write_mask;
          conv_instr->dest.dest.ssa.num_components =
             alu->dest.dest.ssa.num_components;
          memcpy(conv_instr->src[0].swizzle,

diff --git a/src/compiler/nir/nir_lower_phis_to_scalar.c b/src/compiler/nir/nir_lower_phis_to_scalar.c
index 1a2638e..36d386a 100644 (file)
--- a/src/compiler/nir/nir_lower_phis_to_scalar.c
+++ b/src/compiler/nir/nir_lower_phis_to_scalar.c
@@ -203,7 +203,6 @@ lower_phis_to_scalar_block(nir_block *block,
       nir_alu_instr *vec = nir_alu_instr_create(state->shader, vec_op);
       nir_ssa_dest_init(&vec->instr, &vec->dest.dest,
                         phi->dest.ssa.num_components, bit_size);
-      vec->dest.write_mask = (1 << phi->dest.ssa.num_components) - 1;
 
       for (unsigned i = 0; i < phi->dest.ssa.num_components; i++) {
          nir_phi_instr *new_phi = nir_phi_instr_create(state->shader);
@@ -217,7 +216,6 @@ lower_phis_to_scalar_block(nir_block *block,
             nir_alu_instr *mov = nir_alu_instr_create(state->shader,
                                                       nir_op_mov);
             nir_ssa_dest_init(&mov->instr, &mov->dest.dest, 1, bit_size);
-            mov->dest.write_mask = 1;
             nir_src_copy(&mov->src[0].src, &src->src, &mov->instr);
             mov->src[0].swizzle[0] = i;
 

diff --git a/src/compiler/nir/nir_lower_shader_calls.c b/src/compiler/nir/nir_lower_shader_calls.c
index ba38606..d4415dd 100644 (file)
--- a/src/compiler/nir/nir_lower_shader_calls.c
+++ b/src/compiler/nir/nir_lower_shader_calls.c
@@ -1559,8 +1559,8 @@ nir_opt_trim_stack_values(nir_shader *shader)
                nir_alu_instr *alu = nir_instr_as_alu(use_src->parent_instr);
                nir_alu_src *alu_src = exec_node_data(nir_alu_src, use_src, src);
 
-               unsigned write_mask = alu->dest.write_mask;
-               u_foreach_bit(idx, write_mask)
+               unsigned count = nir_dest_num_components(alu->dest.dest);
+               for (unsigned idx = 0; idx < count; ++idx)
                   alu_src->swizzle[idx] = swiz_map[alu_src->swizzle[idx]];
             } else if (use_src->parent_instr->type == nir_instr_type_intrinsic) {
                nir_intrinsic_instr *use_intrin =

diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c b/src/compiler/nir/nir_lower_vars_to_ssa.c
index 99a41ec..9038d4f 100644 (file)
--- a/src/compiler/nir/nir_lower_vars_to_ssa.c
+++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
@@ -603,7 +603,6 @@ rename_variables(struct lower_variables_state *state)
             for (unsigned i = intrin->num_components; i < NIR_MAX_VEC_COMPONENTS; i++)
                mov->src[0].swizzle[i] = 0;
 
-            mov->dest.write_mask = (1 << intrin->num_components) - 1;
             nir_ssa_dest_init(&mov->instr, &mov->dest.dest,
                               intrin->num_components,
                               intrin->dest.ssa.bit_size);

diff --git a/src/compiler/nir/nir_lower_vec_to_regs.c b/src/compiler/nir/nir_lower_vec_to_regs.c
index dd878cd..9074ad5 100644 (file)
--- a/src/compiler/nir/nir_lower_vec_to_regs.c
+++ b/src/compiler/nir/nir_lower_vec_to_regs.c
@@ -178,7 +178,6 @@ try_coalesce(nir_builder *b, nir_ssa_def *reg, nir_alu_instr *vec,
    assert(bit_size == src_alu->dest.dest.ssa.bit_size);
    nir_ssa_dest_init(&src_alu->instr, &src_alu->dest.dest,
                      dest_components, bit_size);
-   src_alu->dest.write_mask = nir_component_mask(dest_components);
 
    /* Then we can store that ALU result directly into the register */
    b->cursor = nir_after_instr(&src_alu->instr);

diff --git a/src/compiler/nir/nir_opt_comparison_pre.c b/src/compiler/nir/nir_opt_comparison_pre.c
index ba089de..919cc1e 100644 (file)
--- a/src/compiler/nir/nir_opt_comparison_pre.c
+++ b/src/compiler/nir/nir_opt_comparison_pre.c
@@ -199,7 +199,6 @@ rewrite_compare_instruction(nir_builder *bld, nir_alu_instr *orig_cmp,
     * nir_search.c).
     */
    nir_alu_instr *mov_add = nir_alu_instr_create(bld->shader, nir_op_mov);
-   mov_add->dest.write_mask = orig_add->dest.write_mask;
    nir_ssa_dest_init(&mov_add->instr, &mov_add->dest.dest,
                      orig_add->dest.dest.ssa.num_components,
                      orig_add->dest.dest.ssa.bit_size);
@@ -208,7 +207,6 @@ rewrite_compare_instruction(nir_builder *bld, nir_alu_instr *orig_cmp,
    nir_builder_instr_insert(bld, &mov_add->instr);
 
    nir_alu_instr *mov_cmp = nir_alu_instr_create(bld->shader, nir_op_mov);
-   mov_cmp->dest.write_mask = orig_cmp->dest.write_mask;
    nir_ssa_dest_init(&mov_cmp->instr, &mov_cmp->dest.dest,
                      orig_cmp->dest.dest.ssa.num_components,
                      orig_cmp->dest.dest.ssa.bit_size);

diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c
index 0b4735e..65b85d1 100644 (file)
--- a/src/compiler/nir/nir_opt_if.c
+++ b/src/compiler/nir/nir_opt_if.c
@@ -1185,7 +1185,6 @@ clone_alu_and_replace_src_defs(nir_builder *b, const nir_alu_instr *alu,
                      alu->dest.dest.ssa.num_components,
                      alu->dest.dest.ssa.bit_size);
 
-   nalu->dest.write_mask = alu->dest.write_mask;
 
    for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
       nalu->src[i].src = nir_src_for_ssa(src_defs[i]);

diff --git a/src/compiler/nir/nir_opt_peephole_select.c b/src/compiler/nir/nir_opt_peephole_select.c
index 331f935..6830322 100644 (file)
--- a/src/compiler/nir/nir_opt_peephole_select.c
+++ b/src/compiler/nir/nir_opt_peephole_select.c
@@ -459,7 +459,6 @@ nir_opt_peephole_select_block(nir_block *block, nir_shader *shader,
 
       nir_ssa_dest_init(&sel->instr, &sel->dest.dest,
                         phi->dest.ssa.num_components, phi->dest.ssa.bit_size);
-      sel->dest.write_mask = (1 << phi->dest.ssa.num_components) - 1;
 
       nir_ssa_def_rewrite_uses(&phi->dest.ssa,
                                &sel->dest.dest.ssa);

diff --git a/src/compiler/nir/nir_opt_shrink_vectors.c b/src/compiler/nir/nir_opt_shrink_vectors.c
index 2341542..91acc4b 100644 (file)
--- a/src/compiler/nir/nir_opt_shrink_vectors.c
+++ b/src/compiler/nir/nir_opt_shrink_vectors.c
@@ -276,7 +276,6 @@ opt_shrink_vectors_alu(nir_builder *b, nir_alu_instr *instr)
 
    /* update dest */
    def->num_components = rounded;
-   instr->dest.write_mask = BITFIELD_MASK(rounded);
 
    return progress;
 }

diff --git a/src/compiler/nir/nir_opt_vectorize.c b/src/compiler/nir/nir_opt_vectorize.c
index 2f8449c..1947646 100644 (file)
--- a/src/compiler/nir/nir_opt_vectorize.c
+++ b/src/compiler/nir/nir_opt_vectorize.c
@@ -196,7 +196,6 @@ instr_try_combine(struct set *instr_set, nir_instr *instr1, nir_instr *instr2)
    nir_alu_instr *new_alu = nir_alu_instr_create(b.shader, alu1->op);
    nir_ssa_dest_init(&new_alu->instr, &new_alu->dest.dest, total_components,
                      alu1->dest.dest.ssa.bit_size);
-   new_alu->dest.write_mask = (1 << total_components) - 1;
    new_alu->instr.pass_flags = alu1->instr.pass_flags;
 
    /* If either channel is exact, we have to preserve it even if it's

diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c
index 92376ca..6c615b5 100644 (file)
--- a/src/compiler/nir/nir_search.c
+++ b/src/compiler/nir/nir_search.c
@@ -433,7 +433,6 @@ construct_value(nir_builder *build,
       nir_alu_instr *alu = nir_alu_instr_create(build->shader, op);
       nir_ssa_dest_init(&alu->instr, &alu->dest.dest, num_components,
                         dst_bit_size);
-      alu->dest.write_mask = (1 << num_components) - 1;
 
       /* We have no way of knowing what values in a given search expression
        * map to a particular replacement value.  Therefore, if the

diff --git a/src/compiler/nir/nir_serialize.c b/src/compiler/nir/nir_serialize.c
index a433bd8..430f0d9 100644 (file)
--- a/src/compiler/nir/nir_serialize.c
+++ b/src/compiler/nir/nir_serialize.c
@@ -791,9 +791,6 @@ read_alu(read_ctx *ctx, union packed_instr header)
 
    read_dest(ctx, &alu->dest.dest, &alu->instr, header);
 
-   unsigned dst_components = nir_dest_num_components(alu->dest.dest);
-   alu->dest.write_mask = u_bit_consecutive(0, dst_components);
-
    if (header.alu.packed_src_ssa_16bit) {
       for (unsigned i = 0; i < num_srcs; i++) {
          nir_alu_src *src = &alu->src[i];

diff --git a/src/compiler/nir/nir_split_64bit_vec3_and_vec4.c b/src/compiler/nir/nir_split_64bit_vec3_and_vec4.c
index 4eb2276..3c09dff 100644 (file)
--- a/src/compiler/nir/nir_split_64bit_vec3_and_vec4.c
+++ b/src/compiler/nir/nir_split_64bit_vec3_and_vec4.c
@@ -229,7 +229,6 @@ split_phi(nir_builder *b, nir_phi_instr *phi)
    nir_alu_instr *vec = nir_alu_instr_create(b->shader, vec_op);
    nir_ssa_dest_init(&vec->instr, &vec->dest.dest,
                      phi->dest.ssa.num_components, 64);
-   vec->dest.write_mask = (1 << phi->dest.ssa.num_components) - 1;
 
    int num_comp[2] = {2, phi->dest.ssa.num_components - 2};
 

diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c
index 62e152b..d382ff6 100644 (file)
--- a/src/compiler/nir/nir_validate.c
+++ b/src/compiler/nir/nir_validate.c
@@ -216,13 +216,6 @@ static void
 validate_alu_dest(nir_alu_instr *instr, validate_state *state)
 {
    nir_alu_dest *dest = &instr->dest;
-   unsigned dest_size = nir_dest_num_components(dest->dest);
-   /*
-    * validate that the instruction doesn't write to components not in the
-    * register/SSA value
-    */
-   validate_assert(state, !(dest->write_mask & ~nir_component_mask(dest_size)));
-
    validate_dest(&dest->dest, state, 0, 0);
 }
 

diff --git a/src/compiler/nir/tests/comparison_pre_tests.cpp b/src/compiler/nir/tests/comparison_pre_tests.cpp
index a4b4a3d..0661a64 100644 (file)
--- a/src/compiler/nir/tests/comparison_pre_tests.cpp
+++ b/src/compiler/nir/tests/comparison_pre_tests.cpp
@@ -505,7 +505,6 @@ TEST_F(comparison_pre_test, swizzle_of_same_immediate_vector)
    nir_builder_alu_instr_finish_and_insert(&bld, flt);
 
    flt->dest.dest.ssa.num_components = 1;
-   flt->dest.write_mask = 1;
 
    nir_if *nif = nir_push_if(&bld, &flt->dest.dest.ssa);
 
@@ -520,7 +519,6 @@ TEST_F(comparison_pre_test, swizzle_of_same_immediate_vector)
    nir_builder_alu_instr_finish_and_insert(&bld, fadd);
 
    fadd->dest.dest.ssa.num_components = 1;
-   fadd->dest.write_mask = 1;
 
    nir_pop_if(&bld, nif);
 
@@ -562,7 +560,6 @@ TEST_F(comparison_pre_test, non_scalar_add_result)
    nir_builder_alu_instr_finish_and_insert(&bld, flt);
 
    flt->dest.dest.ssa.num_components = 1;
-   flt->dest.write_mask = 1;
 
    nir_if *nif = nir_push_if(&bld, &flt->dest.dest.ssa);
 
@@ -577,7 +574,6 @@ TEST_F(comparison_pre_test, non_scalar_add_result)
    nir_builder_alu_instr_finish_and_insert(&bld, fadd);
 
    fadd->dest.dest.ssa.num_components = 2;
-   fadd->dest.write_mask = 3;
 
    nir_pop_if(&bld, nif);
 

diff --git a/src/compiler/nir/tests/mod_analysis_tests.cpp b/src/compiler/nir/tests/mod_analysis_tests.cpp
index dc7fc64..7b0ae39 100644 (file)
--- a/src/compiler/nir/tests/mod_analysis_tests.cpp
+++ b/src/compiler/nir/tests/mod_analysis_tests.cpp
@@ -59,7 +59,6 @@ nir_mod_analysis_test::nir_imul_vec2y(nir_builder *b, nir_ssa_def *src0, nir_ssa
    instr->src[1].swizzle[0] = 1;
 
    nir_ssa_dest_init(&instr->instr, &instr->dest.dest, 1, 32);
-   instr->dest.write_mask = 1;
 
    nir_builder_instr_insert(b, &instr->instr);
    return &instr->dest.dest.ssa;

diff --git a/src/compiler/nir/tests/opt_shrink_vectors_tests.cpp b/src/compiler/nir/tests/opt_shrink_vectors_tests.cpp
index 060a2e0..ac6a067 100644 (file)
--- a/src/compiler/nir/tests/opt_shrink_vectors_tests.cpp
+++ b/src/compiler/nir/tests/opt_shrink_vectors_tests.cpp
@@ -90,7 +90,6 @@ TEST_F(nir_opt_shrink_vectors_test, opt_shrink_vectors_load_const_trailing_compo
    nir_alu_instr *alu_instr = nir_instr_as_alu(alu_result->parent_instr);
    set_swizzle(&alu_instr->src[0], "x");
    alu_result->num_components = 1;
-   alu_instr->dest.write_mask = BITFIELD_MASK(1);
 
    nir_store_var(b, out_var, alu_result, 1);
 
@@ -122,14 +121,12 @@ TEST_F(nir_opt_shrink_vectors_test, opt_shrink_vectors_alu_trailing_component_on
    nir_ssa_def *alu_result = nir_build_alu1(b, nir_op_mov, in_def);
    nir_alu_instr *alu_instr = nir_instr_as_alu(alu_result->parent_instr);
    alu_result->num_components = 4;
-   alu_instr->dest.write_mask = BITFIELD_MASK(4);
    set_swizzle(&alu_instr->src[0], "xyxx");
 
    nir_ssa_def *alu2_result = nir_build_alu1(b, nir_op_mov, alu_result);
    nir_alu_instr *alu2_instr = nir_instr_as_alu(alu2_result->parent_instr);
    set_swizzle(&alu2_instr->src[0], "x");
    alu2_result->num_components = 1;
-   alu2_instr->dest.write_mask = BITFIELD_MASK(1);
 
    nir_store_var(b, out_var, alu2_result, 1);
 
@@ -163,7 +160,6 @@ TEST_F(nir_opt_shrink_vectors_test, opt_shrink_vectors_simple)
    nir_ssa_def *alu_result = nir_build_alu2(b, nir_op_fadd, in_def, imm_vec);
    nir_alu_instr *alu_instr = nir_instr_as_alu(alu_result->parent_instr);
    alu_result->num_components = 4;
-   alu_instr->dest.write_mask = BITFIELD_MASK(4);
    set_swizzle(&alu_instr->src[0], "xxxy");
    set_swizzle(&alu_instr->src[1], "ywyz");
 
@@ -229,7 +225,6 @@ TEST_F(nir_opt_shrink_vectors_test, opt_shrink_vectors_vec8)
    nir_ssa_def *alu_result = nir_build_alu2(b, nir_op_fadd, in_def, imm_vec);
    nir_alu_instr *alu_instr = nir_instr_as_alu(alu_result->parent_instr);
    alu_result->num_components = 8;
-   alu_instr->dest.write_mask = BITFIELD_MASK(8);
    set_swizzle(&alu_instr->src[0], "xxxxxxxy");
    set_swizzle(&alu_instr->src[1], "afhdefgh");
 
@@ -294,7 +289,6 @@ TEST_F(nir_opt_shrink_vectors_test, opt_shrink_phis_loop_simple)
    nir_ssa_def *fge = nir_fge(b, phi_def, loop_max);
    nir_alu_instr *fge_alu_instr = nir_instr_as_alu(fge->parent_instr);
    fge->num_components = 1;
-   fge_alu_instr->dest.write_mask = BITFIELD_MASK(1);
    fge_alu_instr->src[0].swizzle[0] = 1;
 
    nir_if *nif = nir_push_if(b, fge);
@@ -307,7 +301,6 @@ TEST_F(nir_opt_shrink_vectors_test, opt_shrink_phis_loop_simple)
    nir_ssa_def *fadd = nir_fadd(b, phi_def, increment);
    nir_alu_instr *fadd_alu_instr = nir_instr_as_alu(fadd->parent_instr);
    fadd->num_components = 1;
-   fadd_alu_instr->dest.write_mask = BITFIELD_MASK(1);
    fadd_alu_instr->src[0].swizzle[0] = 1;
 
    nir_ssa_scalar srcs[4] = {{0}};
@@ -403,7 +396,6 @@ TEST_F(nir_opt_shrink_vectors_test, opt_shrink_phis_loop_swizzle)
    nir_ssa_def *fge = nir_fge(b, phi_def, loop_max);
    nir_alu_instr *fge_alu_instr = nir_instr_as_alu(fge->parent_instr);
    fge->num_components = 1;
-   fge_alu_instr->dest.write_mask = BITFIELD_MASK(1);
    fge_alu_instr->src[0].swizzle[0] = 2;
 
    nir_if *nif = nir_push_if(b, fge);
@@ -416,7 +408,6 @@ TEST_F(nir_opt_shrink_vectors_test, opt_shrink_phis_loop_swizzle)
    nir_ssa_def *fadd = nir_fadd(b, phi_def, increment);
    nir_alu_instr *fadd_alu_instr = nir_instr_as_alu(fadd->parent_instr);
    fadd->num_components = 1;
-   fadd_alu_instr->dest.write_mask = BITFIELD_MASK(1);
    fadd_alu_instr->src[0].swizzle[0] = 2;
 
    nir_ssa_scalar srcs[4] = {{0}};
@@ -513,7 +504,6 @@ TEST_F(nir_opt_shrink_vectors_test, opt_shrink_phis_loop_phi_out)
    nir_ssa_def *fge = nir_fge(b, phi_def, loop_max);
    nir_alu_instr *fge_alu_instr = nir_instr_as_alu(fge->parent_instr);
    fge->num_components = 1;
-   fge_alu_instr->dest.write_mask = BITFIELD_MASK(1);
    fge_alu_instr->src[0].swizzle[0] = 1;
 
    nir_if *nif = nir_push_if(b, fge);
@@ -526,7 +516,6 @@ TEST_F(nir_opt_shrink_vectors_test, opt_shrink_phis_loop_phi_out)
    nir_ssa_def *fadd = nir_fadd(b, phi_def, increment);
    nir_alu_instr *fadd_alu_instr = nir_instr_as_alu(fadd->parent_instr);
    fadd->num_components = 1;
-   fadd_alu_instr->dest.write_mask = BITFIELD_MASK(1);
    fadd_alu_instr->src[0].swizzle[0] = 1;
 
    nir_ssa_scalar srcs[4] = {{0}};

diff --git a/src/compiler/nir/tests/range_analysis_tests.cpp b/src/compiler/nir/tests/range_analysis_tests.cpp
index 3ab0f0b..23aa7f2 100644 (file)
--- a/src/compiler/nir/tests/range_analysis_tests.cpp
+++ b/src/compiler/nir/tests/range_analysis_tests.cpp
@@ -61,7 +61,6 @@ ssa_def_bits_used_test::build_alu_instr(nir_op op,
    if (alu == NULL)
       return NULL;
 
-   alu->dest.write_mask = 1;
    alu->dest.dest.ssa.num_components = 1;
 
    return alu;

diff --git a/src/compiler/nir/tests/serialize_tests.cpp b/src/compiler/nir/tests/serialize_tests.cpp
index 6b99426..983a672 100644 (file)
--- a/src/compiler/nir/tests/serialize_tests.cpp
+++ b/src/compiler/nir/tests/serialize_tests.cpp
@@ -169,7 +169,6 @@ TEST_P(nir_serialize_all_test, alu_two_components_full_swizzle)
    nir_alu_instr *fma_alu = nir_instr_as_alu(fma->parent_instr);
 
    fma->num_components = GetParam();
-   fma_alu->dest.write_mask = (1 << GetParam()) - 1;
 
    memset(fma_alu->src[0].swizzle, 1, GetParam());
    memset(fma_alu->src[1].swizzle, 1, GetParam());

diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c
index cd454f9..97ecd97 100644 (file)
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -4067,7 +4067,6 @@ create_vec(struct vtn_builder *b, unsigned num_components, unsigned bit_size)
    nir_op op = nir_op_vec(num_components);
    nir_alu_instr *vec = nir_alu_instr_create(b->shader, op);
    nir_ssa_dest_init(&vec->instr, &vec->dest.dest, num_components, bit_size);
-   vec->dest.write_mask = (1 << num_components) - 1;
 
    return vec;
 }

diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c
index 679265c..feca639 100644 (file)
--- a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c
@@ -728,7 +728,6 @@ insert_vec_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader)
       }
    }
 
-   mov->dest.write_mask = (1 << num_components) - 1;
    nir_ssa_dest_init(&mov->instr, &mov->dest.dest, num_components, 32);
 
    /* replace vec srcs with inserted mov */

diff --git a/src/gallium/drivers/etnaviv/etnaviv_nir.c b/src/gallium/drivers/etnaviv/etnaviv_nir.c
index 2cee67a..57e1c8d 100644 (file)
--- a/src/gallium/drivers/etnaviv/etnaviv_nir.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_nir.c
@@ -132,7 +132,6 @@ etna_lower_io(nir_shader *shader, struct etna_shader_variant *v)
             for (unsigned i = tex->coord_components; i < 4; i++)
                vec->src[i].src = nir_src_for_ssa(src1->ssa);
 
-            vec->dest.write_mask = 0xf;
             nir_ssa_dest_init(&vec->instr, &vec->dest.dest, 4, 32);
 
             nir_tex_instr_remove_src(tex, src1_idx);
@@ -187,7 +186,6 @@ etna_lower_alu_impl(nir_function_impl *impl, bool has_new_transcendentals)
             mul->src[0].src = mul->src[1].src = nir_src_for_ssa(ssa);
             mul->src[1].swizzle[0] = 1;
 
-            mul->dest.write_mask = 1;
             nir_ssa_dest_init(&mul->instr, &mul->dest.dest, 1, 32);
 
             alu->src[0].swizzle[1] = 0;

diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp b/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp
index af959f5..4db01ba 100644 (file)
--- a/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp
+++ b/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp
@@ -898,7 +898,6 @@ Lower64BitToVec2::lower(nir_instr *instr)
       auto alu = nir_instr_as_alu(instr);
       alu->dest.dest.ssa.bit_size = 32;
       alu->dest.dest.ssa.num_components *= 2;
-      alu->dest.write_mask = (1 << alu->dest.dest.ssa.num_components) - 1;
       switch (alu->op) {
       case nir_op_pack_64_2x32_split:
          alu->op = nir_op_vec2;

diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp b/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp
index 5315707..2f0693e 100644 (file)
--- a/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp
+++ b/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp
@@ -487,7 +487,6 @@ NirLowerFSOutToVector::create_combined_vector(nir_builder *b,
    }
 
    nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_comp, 32);
-   instr->dest.write_mask = (1 << num_comp) - 1;
    nir_builder_instr_insert(b, &instr->instr);
    return &instr->dest.dest.ssa;
 }

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index d311c43..d71e62c 100644 (file)
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2078,8 +2078,6 @@ fs_visitor::get_nir_dest(const nir_dest &dest)
 nir_component_mask_t
 fs_visitor::get_nir_write_mask(const nir_alu_dest &dest)
 {
-   assert(dest.write_mask == nir_component_mask(dest.dest.ssa.num_components));
-
    nir_intrinsic_instr *store_reg = nir_store_reg_for_def(&dest.dest.ssa);
    if (!store_reg) {
       return nir_component_mask(dest.dest.ssa.num_components);

diff --git a/src/intel/compiler/brw_nir_lower_conversions.c b/src/intel/compiler/brw_nir_lower_conversions.c
index 52bbdf4..3650043 100644 (file)
--- a/src/intel/compiler/brw_nir_lower_conversions.c
+++ b/src/intel/compiler/brw_nir_lower_conversions.c
@@ -43,7 +43,6 @@ split_conversion(nir_builder *b, nir_alu_instr *alu, nir_alu_type src_type,
                  nir_rounding_mode rnd)
 {
    b->cursor = nir_before_instr(&alu->instr);
-   assert(alu->dest.write_mask == 1);
    nir_ssa_def *src = nir_ssa_for_alu_src(b, alu, 0);
    nir_ssa_def *tmp = nir_type_convert(b, src, src_type, tmp_type, nir_rounding_mode_undef);
    nir_ssa_def *res = nir_type_convert(b, tmp, tmp_type, dst_type, rnd);

diff --git a/src/intel/compiler/brw_nir_opt_peephole_ffma.c b/src/intel/compiler/brw_nir_opt_peephole_ffma.c
index c31a726..bd22622 100644 (file)
--- a/src/intel/compiler/brw_nir_opt_peephole_ffma.c
+++ b/src/intel/compiler/brw_nir_opt_peephole_ffma.c
@@ -224,7 +224,6 @@ brw_nir_opt_peephole_ffma_instr(nir_builder *b,
       mul_src[0] = nir_fneg(b, mul_src[0]);
 
    nir_alu_instr *ffma = nir_alu_instr_create(b->shader, nir_op_ffma);
-   ffma->dest.write_mask = add->dest.write_mask;
 
    for (unsigned i = 0; i < 2; i++) {
       ffma->src[i].src = nir_src_for_ssa(mul_src[i]);

diff --git a/src/intel/compiler/brw_nir_opt_peephole_imul32x16.c b/src/intel/compiler/brw_nir_opt_peephole_imul32x16.c
index 06ee5a0..eddbdfa 100644 (file)
--- a/src/intel/compiler/brw_nir_opt_peephole_imul32x16.c
+++ b/src/intel/compiler/brw_nir_opt_peephole_imul32x16.c
@@ -41,7 +41,6 @@ replace_imul_instr(nir_builder *b, nir_alu_instr *imul, unsigned small_val,
    b->cursor = nir_before_instr(&imul->instr);
 
    nir_alu_instr *imul_32x16 = nir_alu_instr_create(b->shader, new_opcode);
-   imul_32x16->dest.write_mask = imul->dest.write_mask;
 
    nir_alu_src_copy(&imul_32x16->src[0], &imul->src[1 - small_val], imul_32x16);
    nir_alu_src_copy(&imul_32x16->src[1], &imul->src[small_val], imul_32x16);

diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index d3bb1db..f48b704 100644 (file)
--- a/src/mesa/program/prog_to_nir.c
+++ b/src/mesa/program/prog_to_nir.c
@@ -179,7 +179,6 @@ ptn_get_src(struct ptn_compile *c, const struct prog_src_register *prog_src)
             assert(swizzle != SWIZZLE_NIL);
             nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
             nir_ssa_dest_init(&mov->instr, &mov->dest.dest, 1, 32);
-            mov->dest.write_mask = 0x1;
             mov->src[0] = src;
             mov->src[0].swizzle[0] = swizzle;
             nir_builder_instr_insert(b, &mov->instr);

diff --git a/src/microsoft/compiler/nir_to_dxil.c b/src/microsoft/compiler/nir_to_dxil.c
index 4ec9b2f..ca41b21 100644 (file)
--- a/src/microsoft/compiler/nir_to_dxil.c
+++ b/src/microsoft/compiler/nir_to_dxil.c
@@ -2879,7 +2879,6 @@ emit_alu(struct ntd_context *ctx, nir_alu_instr *alu)
    }
 
    /* other ops should be scalar */
-   assert(alu->dest.write_mask == 1);
    const struct dxil_value *src[4];
    assert(nir_op_infos[alu->op].num_inputs <= 4);
    for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {