clock-output-names = "axi";
};
- ahb1_mux: ahb1_mux@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
- clock-output-names = "ahb1_mux";
- };
-
ahb1: ahb1@01c20054 {
#clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-ahb-clk";
+ compatible = "allwinner,sun6i-a31-ahb1-clk";
reg = <0x01c20054 0x4>;
- clocks = <&ahb1_mux>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
clock-output-names = "ahb1";
};
#dma-cells = <1>;
/* DMA controller requires AHB1 clocked from PLL6 */
- assigned-clocks = <&ahb1_mux>;
+ assigned-clocks = <&ahb1>;
assigned-clock-parents = <&pll6 0>;
};