intel/compiler: adjust task payload offsets as late as possible

Otherwise passes which expect offsets to be in bytes (like
brw_nir_lower_mem_access_bit_sizes, called from brw_postprocess_nir)
may produce incorrect results.

Fixes 64-bit load/stores in task/mesh shaders.

Fixes: c36ae42e4cc ("intel/compiler: Use nir_var_mem_task_payload")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16196>

diff --git a/src/intel/compiler/brw_mesh.cpp b/src/intel/compiler/brw_mesh.cpp
index 2644536..e2e2305 100644 (file)
--- a/src/intel/compiler/brw_mesh.cpp
+++ b/src/intel/compiler/brw_mesh.cpp
@@ -171,13 +171,26 @@ brw_nir_adjust_task_payload_offsets_instr(struct nir_builder *b,
    }
 }
 
-static void
+static bool
 brw_nir_adjust_task_payload_offsets(nir_shader *nir)
 {
-   nir_shader_instructions_pass(nir, brw_nir_adjust_task_payload_offsets_instr,
-                                nir_metadata_block_index |
-                                nir_metadata_dominance,
-                                NULL);
+   return nir_shader_instructions_pass(nir,
+                                       brw_nir_adjust_task_payload_offsets_instr,
+                                       nir_metadata_block_index |
+                                       nir_metadata_dominance,
+                                       NULL);
+}
+
+static void
+brw_nir_adjust_payload(nir_shader *shader, const struct brw_compiler *compiler)
+{
+   /* Adjustment of task payload offsets must be performed *after* last pass
+    * which interprets them as bytes, because it changes their unit.
+    */
+   bool adjusted = false;
+   NIR_PASS(adjusted, shader, brw_nir_adjust_task_payload_offsets);
+   if (adjusted) /* clean up the mess created by offset adjustments */
+      NIR_PASS_V(shader, nir_opt_constant_folding);
 }
 
 const unsigned *
@@ -202,7 +215,6 @@ brw_compile_task(const struct brw_compiler *compiler,
       BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
 
    NIR_PASS_V(nir, brw_nir_lower_tue_outputs, &prog_data->map);
-   NIR_PASS_V(nir, brw_nir_adjust_task_payload_offsets);
 
    const unsigned required_dispatch_width =
       brw_required_dispatch_width(&nir->info, key->base.subgroup_size_type);
@@ -226,6 +238,8 @@ brw_compile_task(const struct brw_compiler *compiler,
       brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled,
                           key->base.robust_buffer_access);
 
+      brw_nir_adjust_payload(shader, compiler);
+
       v[simd] = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
                                &prog_data->base.base, shader, dispatch_width,
                                debug_enabled);
@@ -696,7 +710,6 @@ brw_compile_mesh(const struct brw_compiler *compiler,
       BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
 
    NIR_PASS_V(nir, brw_nir_lower_tue_inputs, params->tue_map);
-   NIR_PASS_V(nir, brw_nir_adjust_task_payload_offsets);
 
    brw_compute_mue_map(nir, &prog_data->map);
    NIR_PASS_V(nir, brw_nir_lower_mue_outputs, &prog_data->map);
@@ -735,6 +748,8 @@ brw_compile_mesh(const struct brw_compiler *compiler,
       brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled,
                           key->base.robust_buffer_access);
 
+      brw_nir_adjust_payload(shader, compiler);
+
       v[simd] = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
                                &prog_data->base.base, shader, dispatch_width,
                                debug_enabled);