}
else
{
- emit_move_insn (neg_bval, const1_rtx);
cond = gen_rtx_NE (VOIDmode, rval, oldval);
if (thumb1_cmpneg_operand (oldval, SImode))
- emit_unlikely_jump (gen_cbranchsi4_scratch (neg_bval, rval, oldval,
- label2, cond));
+ {
+ rtx src = rval;
+ if (!satisfies_constraint_L (oldval))
+ {
+ gcc_assert (satisfies_constraint_J (oldval));
+
+ /* For such immediates, ADDS needs the source and destination regs
+ to be the same.
+
+ Normally this would be handled by RA, but this is all happening
+ after RA. */
+ emit_move_insn (neg_bval, rval);
+ src = neg_bval;
+ }
+
+ emit_unlikely_jump (gen_cbranchsi4_neg_late (neg_bval, src, oldval,
+ label2, cond));
+ }
else
- emit_unlikely_jump (gen_cbranchsi4_insn (cond, rval, oldval, label2));
+ {
+ emit_move_insn (neg_bval, const1_rtx);
+ emit_unlikely_jump (gen_cbranchsi4_insn (cond, rval, oldval, label2));
+ }
}
arm_emit_store_exclusive (mode, neg_bval, mem, newval, use_release);
;; Constraints of this pattern must be at least as strict as those of the
;; cbranchsi operations in thumb1.md and aim to be as permissive.
(define_insn_and_split "@atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1"
- [(set (match_operand:CCSI 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out
+ [(set (match_operand:CCSI 0 "cc_register_operand" "=&c,&l,&l") ;; bool out
(unspec_volatile:CCSI [(const_int 0)] VUNSPEC_ATOMIC_CAS))
- (set (match_operand:SI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out
+ (set (match_operand:SI 1 "s_register_operand" "=&r,&l,&l*h") ;; val out
(zero_extend:SI
- (match_operand:NARROW 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua"))) ;; memory
+ (match_operand:NARROW 2 "mem_noofs_operand" "+Ua,Ua,Ua"))) ;; memory
(set (match_dup 2)
(unspec_volatile:NARROW
- [(match_operand:SI 3 "arm_add_operand" "rIL,lIL*h,J,*r") ;; expected
- (match_operand:NARROW 4 "s_register_operand" "r,r,r,r") ;; desired
+ [(match_operand:SI 3 "arm_add_operand" "rIL,lILJ*h,*r") ;; expected
+ (match_operand:NARROW 4 "s_register_operand" "r,r,r") ;; desired
(match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand") ;; mod_s
(match_operand:SI 7 "const_int_operand")] ;; mod_f
VUNSPEC_ATOMIC_CAS))
- (clobber (match_scratch:SI 8 "=&r,X,X,X"))]
+ (clobber (match_scratch:SI 8 "=&r,X,X"))]
"<NARROW:sync_predtab>"
"#"
"&& reload_completed"
arm_split_compare_and_swap (operands);
DONE;
}
- [(set_attr "arch" "32,v8mb,v8mb,v8mb")])
+ [(set_attr "arch" "32,v8mb,v8mb")])
(define_mode_attr cas_cmp_operand
[(SI "arm_add_operand") (DI "cmpdi_operand")])
;; Constraints of this pattern must be at least as strict as those of the
;; cbranchsi operations in thumb1.md and aim to be as permissive.
(define_insn_and_split "@atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1"
- [(set (match_operand:CCSI 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out
+ [(set (match_operand:CCSI 0 "cc_register_operand" "=&c,&l,&l") ;; bool out
(unspec_volatile:CCSI [(const_int 0)] VUNSPEC_ATOMIC_CAS))
- (set (match_operand:SIDI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out
- (match_operand:SIDI 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua")) ;; memory
+ (set (match_operand:SIDI 1 "s_register_operand" "=&r,&l,&l*h") ;; val out
+ (match_operand:SIDI 2 "mem_noofs_operand" "+Ua,Ua,Ua")) ;; memory
(set (match_dup 2)
(unspec_volatile:SIDI
- [(match_operand:SIDI 3 "<SIDI:cas_cmp_operand>" "<SIDI:cas_cmp_str>,lIL*h,J,*r") ;; expect
- (match_operand:SIDI 4 "s_register_operand" "r,r,r,r") ;; desired
+ [(match_operand:SIDI 3 "<SIDI:cas_cmp_operand>" "<SIDI:cas_cmp_str>,lILJ*h,*r") ;; expect
+ (match_operand:SIDI 4 "s_register_operand" "r,r,r") ;; desired
(match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand") ;; mod_s
(match_operand:SI 7 "const_int_operand")] ;; mod_f
VUNSPEC_ATOMIC_CAS))
- (clobber (match_scratch:SI 8 "=&r,X,X,X"))]
+ (clobber (match_scratch:SI 8 "=&r,X,X"))]
"<SIDI:sync_predtab>"
"#"
"&& reload_completed"
arm_split_compare_and_swap (operands);
DONE;
}
- [(set_attr "arch" "32,v8mb,v8mb,v8mb")])
+ [(set_attr "arch" "32,v8mb,v8mb")])
(define_insn_and_split "atomic_exchange<mode>"
[(set (match_operand:QHSD 0 "s_register_operand" "=&r,&r") ;; output