drm/i915: Allow the user to set bo into the DISPLAY cache domain

This is primarily for the benefit of the create2 ioctl so that the
caller can avoid the later step of rebinding the bo with new PTE bits.
After introducing WT (and possibly GFDT) cacheing for display targets,
not everything in the display is earmarked as UC, and more importantly
what is is controlled by the kernel.

Note that set_cache_level/get_cache_level for DISPLAY is not necessarily
idempotent; get_cache_level may return UC for architectures that have no
special cache domain for the display engine.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4064fdf..5f48ecc 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3477,6 +3477,10 @@ int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
                args->caching = I915_CACHING_CACHED;
                break;
 
+       case I915_CACHE_WT:
+               args->caching = I915_CACHING_DISPLAY;
+               break;
+
        default:
                args->caching = I915_CACHING_NONE;
                break;
@@ -3503,6 +3507,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
        case I915_CACHING_CACHED:
                level = I915_CACHE_LLC;
                break;
+       case I915_CACHING_DISPLAY:
+               level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
+               break;
        default:
                return -EINVAL;
        }