.has_uvs_pba_entries = true,
.has_uvs_vtx_entries = true,
.has_vdm_cam_size = true,
+ .has_vdm_degenerate_culling = true,
.common_store_size_in_dwords = 512U * 4U * 4U,
.isp_max_tiles_in_flight = 1U,
.has_uvs_pba_entries = true,
.has_uvs_vtx_entries = true,
.has_vdm_cam_size = true,
+ .has_vdm_degenerate_culling = true,
.has_xpu_max_slaves = true,
.common_store_size_in_dwords = 1344U * 4U * 4U,
bool has_uvs_pba_entries : 1;
bool has_uvs_vtx_entries : 1;
bool has_vdm_cam_size : 1;
+ bool has_vdm_degenerate_culling : 1;
bool has_xpu_max_slaves : 1;
bool has_xt_top_infrastructure : 1;
bool has_zls_subtile : 1;
unsigned int index_stride = 0;
pvr_csb_emit (csb, VDMCTRL_INDEX_LIST0, list0) {
+ const bool vertex_shader_has_side_effects =
+ cmd_buffer->state.gfx_pipeline->vertex_shader_state.stage_state
+ .has_side_effects;
+
list0.primitive_topology = pvr_get_hw_primitive_topology(topology);
/* First instance is not handled in the VDM state, it's implemented as
list0.index_base_addrmsb = index_buffer_addr;
}
+ list0.degen_cull_enable =
+ PVR_HAS_FEATURE(&cmd_buffer->device->pdevice->dev_info,
+ vdm_degenerate_culling) &&
+ !vertex_shader_has_side_effects;
+
list_hdr = list0;
}