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radv: don't lower vectorized instructions to 32bit
author
Daniel Schürmann
<daniel@schuermann.dev>
Mon, 27 Jun 2022 12:49:49 +0000
(14:49 +0200)
committer
Marge Bot
<emma+marge@anholt.net>
Mon, 27 Jun 2022 15:07:27 +0000
(15:07 +0000)
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
src/amd/vulkan/radv_pipeline.c
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diff --git
a/src/amd/vulkan/radv_pipeline.c
b/src/amd/vulkan/radv_pipeline.c
index
d22314c
..
68380cb
100644
(file)
--- a/
src/amd/vulkan/radv_pipeline.c
+++ b/
src/amd/vulkan/radv_pipeline.c
@@
-3990,6
+3990,11
@@
lower_bit_size_callback(const nir_instr *instr, void *_)
return 0;
nir_alu_instr *alu = nir_instr_as_alu(instr);
+ /* If an instruction is not scalarized by this point,
+ * it can be emitted as packed instruction */
+ if (alu->dest.dest.ssa.num_components > 1)
+ return 0;
+
if (alu->dest.dest.ssa.bit_size & (8 | 16)) {
unsigned bit_size = alu->dest.dest.ssa.bit_size;
switch (alu->op) {