arm64: dts: rockchip: add rk3328 dwc3 usb controller node

commit 44dd5e2106dc2fd01697b539085818d1d1c58df0 upstream.

RK3328 SoCs have one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB 3.0/2.0 OTG basing
on ID of USB3.0 PHY.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Cameron Nemo <cnemo@tutanota.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210209192350.7130-7-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 93c734d..de1e5e8 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -984,6 +984,25 @@
                status = "disabled";
        };
 
+       usbdrd3: usb@ff600000 {
+               compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
+               reg = <0x0 0xff600000 0x0 0x100000>;
+               interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
+                        <&cru ACLK_USB3OTG>;
+               clock-names = "ref_clk", "suspend_clk",
+                             "bus_clk";
+               dr_mode = "otg";
+               phy_type = "utmi_wide";
+               snps,dis-del-phy-power-chg-quirk;
+               snps,dis_enblslpm_quirk;
+               snps,dis-tx-ipgap-linecheck-quirk;
+               snps,dis-u2-freeclk-exists-quirk;
+               snps,dis_u2_susphy_quirk;
+               snps,dis_u3_susphy_quirk;
+               status = "disabled";
+       };
+
        gic: interrupt-controller@ff811000 {
                compatible = "arm,gic-400";
                #interrupt-cells = <3>;